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AgeCommit message (Expand)Author
2019-09-10base: Make Bloom Filter counting by defaultDaniel R. Carvalho
2019-09-10base: Make Bulk inherit from MultiBitSel Bloom FilterDaniel R. Carvalho
2019-09-10mem-ruby: Move Bloom Filters to baseDaniel R. Carvalho
2019-09-10mem: Mark MemObject as deprecated.Gabe Black
2019-09-09dev-arm: Reset HPPI when clearing an LPIGiacomo Travaglini
2019-09-09dev-arm: Add resetHppi method in the GICv3 cpu interfaceGiacomo Travaglini
2019-09-09dev-arm: Cleanup GICv3 initializationGiacomo Travaglini
2019-09-09dev-arm: Initialize GICD_TYPER once at construction timeGiacomo Travaglini
2019-09-09dev-arm: Writes to IGRPEN1_EL3 triggering updateGiacomo Travaglini
2019-09-09dev-arm: Fix GICv3 ITS cmdq wrappingGiacomo Travaglini
2019-09-09dev-arm: Fix mapping between IGRPEN1_EL3 and IGRPEN1_EL1Giacomo Travaglini
2019-09-09dev-arm: Implement message-based SPIsGiacomo Travaglini
2019-09-09dev: Scrub out some lingering uses of MemObject.Gabe Black
2019-09-07dev-arm: Add GICD_SGIR registerGiacomo Travaglini
2019-09-07python: Make the dot writer handle unconnected Port vector elements.Gabe Black
2019-09-06dev: Enable Terminal output's dump to stdoutGiacomo Travaglini
2019-09-06dev-arm: State update when setting MISCREG_ICC_IGRPENx registerGiacomo Travaglini
2019-09-06arch-arm, dev-arm: MISCREG_ICC_IGRPEN1_EL1 using AA64 bankingGiacomo Travaglini
2019-09-06arch-arm, dev-arm: MISCREG_ICC_AP1R0_EL1 using AA64 bankingGiacomo Travaglini
2019-09-06arch-arm, dev-arm: MISCREG_ICC_CTLR_EL1 using AA64 bankingGiacomo Travaglini
2019-09-06arch-arm: MISCREG_ICC_BPR1_EL1 using AA64 bankingGiacomo Travaglini
2019-09-06dev-arm: Add read/writeBanked helpers to GICv3Giacomo Travaglini
2019-09-06arch-arm: Add explicit AArch64 MiscReg bankingGiacomo Travaglini
2019-09-06arch-arm: Use same template across all MSR instGiacomo Travaglini
2019-09-06arch-arm: SySDC64 Instructions (CMO) using MiscRegIndexGiacomo Travaglini
2019-09-06dev: Fix segmentation fault in VirtIOBlockChun-Chen TK Hsu
2019-09-06arch-arm: fix GDB stub after SVECiro Santilli
2019-09-06dev-arm: Rewrite ICC_BPR0/ICC_BPR1 handlingGiacomo Travaglini
2019-09-06dev-arm: Add GICv3 unimplemented Hyp Active Priorities Group regsGiacomo Travaglini
2019-09-06dev-arm: Allow 32-bit access to GITS_TYPERGiacomo Travaglini
2019-09-06dev-arm: Cpu interface groupEnabled check for global enableGiacomo Travaglini
2019-09-06dev-arm: Check if INTID group is enabled when reading HPPIRxGiacomo Travaglini
2019-09-06dev-arm: Writing GICD_CTLR should trigger an updateGiacomo Travaglini
2019-09-06dev-arm: Rewrite GICv3 updateGiacomo Travaglini
2019-09-06dev-arm: Fix GICv3 IGRPMOD writesGiacomo Travaglini
2019-09-06arch-arm: SGI registers undecoded in AArch32Giacomo Travaglini
2019-09-06arch-arm: Fix read/setMiscReg for AArch32 GICv3 ICC regsGiacomo Travaglini
2019-09-06dev-arm: Fix SGI generationGiacomo Travaglini
2019-09-06dev-arm: Gicv3 ITS device tree autogenAdrian Herrera
2019-09-06dev-arm: modify GICv3 ITS default addrAdrian Herrera
2019-09-05arch-x86: Adding warning for movntiPouya Fotouhi
2019-09-05dev-arm: Improper translation slot release in SMMUv3Giacomo Travaglini
2019-09-05dev-arm: Implement invalidateASID in SMMUv3 WalkCacheJan-Peter Larsson
2019-09-05dev-arm: Implement invalidateVA/VAA in SMMUv3 WalkCacheAdrian Herrera
2019-09-05arch-x86: implement movntq/movntdq instructionsPouya Fotouhi
2019-09-04cpu: reset byte_enable across writeMem callsCiro Santilli
2019-09-04dev: Templatize PioPort.Gabe Black
2019-09-03ruby: Fix the way stall map size is checked for availabilitySrikant Bharadwaj
2019-09-03configs: Fix replacement policy assignmentDaniel R. Carvalho
2019-09-02stats: Create HDF5 stat files relative to simoutAndreas Sandberg
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