gem5 - gem5

Age	Commit message (Expand)	Author
2019-10-09	arch-mips,arch-riscv,base: Get rid of the unused HexFile class.	Gabe Black
2019-10-09	base: Rename Section to Segment, and some of its members.	Gabe Black
2019-10-08	base: Get rid of the unused global pointer in object files.	Gabe Black
2019-10-08	base: Ensure %p format arguments are printed as pointers.	Gabe Black
2019-10-07	fastmodel: Make CortexA76x1's interrupts use gem5's mechanisms.	Gabe Black
2019-10-07	configs: Isolate ISA related object lists	Daniel R. Carvalho
2019-10-07	kvm, arm: fix the size of MISCREG_FPSR and MISCREG_FPCR	Ciro Santilli
2019-10-07	config: skip access to branchPred in ARM KVM	Ciro Santilli
2019-10-05	base: ELF segment types are not bitfields.	Gabe Black
2019-10-04	kvm: Rename gettid() to build with glibc 2.30+	Tommaso Marinelli
2019-10-03	mem: Remove unused variable	Tommaso Marinelli
2019-10-03	tests: Fix a minor bug in fixture.py	Ayaz Akram
2019-10-03	dev, misc: Fixing "may be used unitialized" compilation error	Bobby R. Bruce
2019-10-03	sim-se: Fix invalid delete of params on clone	Jason Lowe-Power
2019-10-03	arch-arm: Annotate CM flag in AA64 CM Instructions	Giacomo Travaglini
2019-10-03	arch-arm: Set CM bit in DataAbort	Giacomo Travaglini
2019-10-02	sim: Mark System::getThreadContext method as const	Giacomo Travaglini
2019-10-02	dev-arm: Improve fault message on SMMUv3 translation fault	Marc Mari Barcelo
2019-10-02	dev-arm: Fix address used to update the SMMUv3 Walk Cache	Marc Mari Barcelo
2019-10-02	arch-arm: Create helper for sending events (SEV)	Giacomo Travaglini
2019-10-02	fastmodel: Get rid of the back channel mem port in FastModel::ArmCPU.	Gabe Black
2019-10-02	fastmodel: Implement a custom sendFunctional for CortexA76x1.	Gabe Black
2019-10-02	x86: Switch from MessageReq and Resp to WriteReq and Resp.	Gabe Black
2019-10-02	fastmodel: Let the EVS set an attribute for getSendFunctional to return.	Gabe Black
2019-10-01	style: normalize filename in SortedIncludes.fix()	Georg Kotheimer
2019-10-01	fastmodel: Add a gem5Cpu attribute to the CortexA76x1.	Gabe Black
2019-10-01	fastmodel: Add a utility class which makes it easier to watch signals.	Gabe Black
2019-10-01	fastmodel: Pull out and simplify the interrupt mechanism in the GIC.	Gabe Black
2019-10-01	mem-cache: Fix invalid whenReady	Daniel R. Carvalho
2019-10-01	configs: Port PlatformConfig to the common object list	Daniel R. Carvalho
2019-10-01	configs: Port MemConfig to the common object list	Daniel R. Carvalho
2019-10-01	configs: Port HWPConfig to the common object list	Daniel R. Carvalho
2019-10-01	configs: Port BPConfig to use the common object list	Daniel R. Carvalho
2019-09-30	configs: Port CPUConfig to use the common object list	Daniel R. Carvalho
2019-09-30	configs: Create a basic ObjectList	Daniel R. Carvalho
2019-09-30	configs: Remove is_atomic_cpu check	Daniel R. Carvalho
2019-09-30	mem-ruby: Remove inexistent functions from Util	Daniel R. Carvalho
2019-09-30	mem-ruby: Make bitSelect use bits<Addr>	Daniel R. Carvalho
2019-09-30	mem-ruby: Fix maskLowOrderBits	Daniel R. Carvalho
2019-09-30	mem-ruby: Remove shiftLowOrderBits	Daniel R. Carvalho
2019-09-30	mem-ruby: Remove maskHighOrderBits	Daniel R. Carvalho
2019-09-30	mem-ruby: Remove bitRemove	Daniel R. Carvalho
2019-09-30	cpu: Make use of DRAMCtrl::AddrMap in the traffic generators	Nikos Nikoleris
2019-09-30	misc: Added line wrapping functionality for Sim-Object desc	Bobby R. Bruce
2019-09-30	mem: Use new-style stats in the XBar models	Andreas Sandberg
2019-09-30	mem-cache: Switch to new-style stats	Andreas Sandberg
2019-09-30	mem: Convert DRAM controller to new-style stats	Andreas Sandberg
2019-09-28	ruby: 2x protocols has typo/syntax error that fails building	Timothy Hayes
2019-09-27	fastmodel: Add glue code which adapts fastmodels to run in gem5.	Gabe Black
2019-09-26	sim: Convert power modelling framework to new-style stats	Andreas Sandberg