Age | Commit message (Collapse) | Author |
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into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/head
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extra : convert_revision : 7181d8c2ee673322372484cf288a94ebd91b5265
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functions.
src/cpu/o3/alpha/cpu_impl.hh:
Pass ISA-specific O3 CPU to FullO3CPU as a constructor parameter instead of using setCPU functions.
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into zeep.pool:/z/saidi/work/m5.newmem
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deletePortRefs() is called on it with that port as a parameter.
In this way a MemoryObject can keep a functional port around and give it to anyone who wants to do functional accesses rather
than creating a new one each time.
src/mem/bus.cc:
src/mem/bus.hh:
src/mem/cache/cache_impl.hh:
only keep around one func port we give to anyone who wants it. Otherwise we can run out of port ids reasonably quickly if
a lot of functional accesses are happening (e.g. remote debugging, dprintk, etc)
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into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/head
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into zizzer.eecs.umich.edu:/tmp/newmem.1449b
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
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extra : convert_revision : 7be8ebe55a7b11552d78701520f93aa86db1e501
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multiops do alot more of what they're supposed to (excluding memory operands), and microops are slightly more implemented.
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The removed ones were unnecessary. The commented out ones could be useful in the future, should this problem get fixed. See flyspray task #243.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/o3/lsq_unit_impl.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/rob_impl.hh:
Remove/comment out DPRINTFs that were causing a segfault.
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into zeep.pool:/z/saidi/work/m5.newmem
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
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into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem-mcf
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instructions to return an instance of the right class. The code to decode register numbers and generate loads and stores still needs to be added. Also, a syntax for specifying operands as sources, destinations, or both needs to be established. Multipl microop instructions are also not handled, pending real macroop generation support.
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extra : convert_revision : 1a0a4b36afce8255e23e3cdd7a85c1392dda5f72
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Each statement has an optional label at the beginning, a capitilized microcode class name which is roughly equivalent to a mnemonic in a regular ISA, and then an optional series of operands seperated by white space. The operands are either a decimal constant, a label, or a code fragment surrounded by non nested {}s. Labels are a letter or underscore followed by letters, underscores, or digits. The syntax for describing code segments might need to be changed if a need arrises to have {}s in the code itself.
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into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem-vortex
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into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem-vortex
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into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem-gzip
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tgts_per_mshr of the caches to 20. This is needed otherwise things will potentially lock up when using the O3CPU because the caches can run out of targets, and then not respond.
Remove this hack once the caches eventually get fixed.
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extra : convert_revision : 8c61ac1b6182f57ebbe3bcfeddb5a4f4334d7bc0
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hooked up to its ports. This fixes the segfault Ali recently found when using sampling.
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
Update code so that the O3 CPU can handle not initially having anything hooked up to its ports.
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into ewok.(none):/home/gblack/m5/newmem-x86
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actually work.
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/head
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just directly exec the file and generate the flags
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into zeep.pool:/z/saidi/work/m5.newmem
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into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/clean2
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into zower.eecs.umich.edu:/home/gblack/m5/newmem-o3-spec
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into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/clean2
src/cpu/base_dyn_inst.hh:
Hand merge. Line is no longer needed because it's handled in the ISA.
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out-of-order interactions in the 21264.
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1. Move interrupt handling to a separate function to clean up main commit() function a bit. Also gate the function call off properly based on whether or not there are outstanding interrupts, and the system is not in PAL mode.
2. Better handling of updating instruction's status bits. Instructions are not marked "atCommit" until other stages view it (pushed off to IEW/IQ), and they have been properly handled (faults).
3. Don't consider the ROB "empty" for the purpose of other stages until the ROB is empty, all stores have written back, and there was no store commits this cycle. The last is necessary in case a store committed, in which case it would look like all stores have written back but in actuality have not.
src/cpu/o3/commit.hh:
Slightly modify how interrupts are handled. Also include some extra bools to keep track of state properly.
src/cpu/o3/commit_impl.hh:
Slightly modify how interrupts are handled. Also include some extra bools to keep track of state.
General correctness updates, most specifically for when commit broadcasts to other stages that the ROB is empty.
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