summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2019-10-09tests, misc: Updating TESTING.md to describe running unit testsBobby R. Bruce
Previously we did not have any documentation discussing how gem5's GTests were built and executed. TESTING.md has thereby been updated to highlight how this is done. These unit tests should be run prior to each new submission to Gerrit. This has been noted in TESTING.md also. Change-Id: If5867fa0a2e4f6ea0921191a51e779c19a28117a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21479 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-09tests: Migrated refcnt.cc test from src/unitttest to a gtestBobby R. Bruce
refcnt.cc was previously tested in src/unittest/refcnttest.cc. This has now been translated into a GTest as faithfully to the original as possible. Change-Id: I51f7a3d1e0a85b128c4eebd97cfe79b87406dc29 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21499 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-09system-arm: Initialize ICC_SRE_EL3 register of all CPUsChun-Chen TK Hsu
Fix a bug that only CPU0 initialized ICC_SRE_EL3 register. Change-Id: I625c9a25bada80b864e5eb5a8b8be14ee324b801 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21539 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-10-09arch-mips,arch-riscv,base: Get rid of the unused HexFile class.Gabe Black
A pointer to it was set up in the MIPS and RISCV system classes, but nothing ever set that pointer. The class was put in base/loader, but didn't have anything to do (as far as I can see) with loading anything it had a loadSegments method, but was not a subclass of ObjectFile. Change-Id: I4b711a31df20e20ffc306709227f60aa020fca15 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21464 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-10-09base: Rename Section to Segment, and some of its members.Gabe Black
ELF is, in my opinion, the most important object file format gem5 currently understands, and in ELF terminolgy the blob of data that needs to be loaded into memory to a particular location is called a segment. A section is a software level view of what's in a region of memory, and a single segment may contain multiple sections which happen to follow each other in memory. Change-Id: Ib810c5050723d5a96bd7550515b08ac695fb1b02 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21462 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-10-08base: Get rid of the unused global pointer in object files.Gabe Black
This was only ever read from Alpha, and nothing ever set it. It defaulted to zero, so this change just propogates that value through to the Alpha Process class. Change-Id: I569cf9d61a37322dbd88de1038a2af74c64bbe7a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21461 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-08base: Ensure %p format arguments are printed as pointers.Gabe Black
If the %p format is used, char * arguments should be printed as the hex value of their pointer, not as strings. Unfortunately blindly passing them to an ostream using << will not do that. This change adds some casting in that case to ensure that they're treated as numbers and not as strings. Change-Id: If02bae6d5e468b352266702fcba62b6beddffcbd Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21459 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-07fastmodel: Make CortexA76x1's interrupts use gem5's mechanisms.Gabe Black
This makes it easier to wire up CPUs to the interrupt controller, and makes things more modular. Change-Id: I8d3ab26e4bb588b8efb198ed145d0f58b7ee04cb Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21049 Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-07configs: Isolate ISA related object listsDaniel R. Carvalho
Some objects are not compiled when using NULL ISA, and therefore their object lists cannot exist. Change-Id: I93ec576229916c892de50bb6c73cd602e18a3654 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21439 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-07kvm, arm: fix the size of MISCREG_FPSR and MISCREG_FPCRCiro Santilli
Those registers are 32-bit instead of 64 in the KVM API. The Linux kernel 5.2 linux/Documentation/virtual/kvm/api.txt contains: 0x6020 0000 0010 00d4 FPSR 32 fp_regs.fpsr 0x6020 0000 0010 00d5 FPCR 32 fp_regs.fpcr The register itself is 64-bit in the ARM manual, but the top 32 are RES0. This fixes the following error when running ARM KVM early in the simulation: panic: KVM: Failed to set register (0x60300000001000d4) value (errno: 22) Change-Id: I8fe6e12df4809992173200a42e3ce5414748bdad Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21300 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-10-07config: skip access to branchPred in ARM KVMCiro Santilli
Prevents runtime error: AttributeError: object 'ArmV8KvmCPU' has no attribute 'branchPred' Change-Id: Ic5765fd560381cbacc2fa2fd2e6f79d98433c535 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21299 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-05base: ELF segment types are not bitfields.Gabe Black
The ELF segment type had been checked by bitwise &-ing it with the PT_LOAD constant to check if it was loadable. This is incorrect. The value is a flat integer, with different values selecting different types of segments. Change-Id: I644dd985bda4ad2d992557c90ffe8048c0ae6aac Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21460 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-10-04kvm: Rename gettid() to build with glibc 2.30+Tommaso Marinelli
glibc 2.30 introduced the function gettid() in sys/types.h to return the caller's thread ID. In order to avoid conflicts, the already present gettid() functions have been renamed to sysGettid(). This fixes a compilation error with X86 arch. Change-Id: I76c971465fc4b50e4decde8303185439082b2378 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21379 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-03mem: Remove unused variableTommaso Marinelli
The variable *sys in dram_ctrl.cc was only used in an assert() check, therefore it has been removed to allow building gem5.fast without errors. A typo in a comment in abstract_mem.hh has also been corrected. Change-Id: I2663545449ecfdb5a27c3574b79dd42beb4a49c8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21380 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-10-03tests: Fix a minor bug in fixture.pyAyaz Akram
debug is a part of test_log object. Signed-off-by: Ayaz Akram <yazakram@ucdavis.edu> Change-Id: I56d950483c1d86b76b4f652741d2323c1b078e3e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19768 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-03dev, misc: Fixing "may be used unitialized" compilation errorBobby R. Bruce
When compiling using "scons build/X86/base", "error: 'tx_queue_size' may be used uninitialized in this function" is received (cc1plus: all warnings treated as errors). tx_queue_size is now initialized to zero to avoid this compilation error. Change-Id: I0e2a4fd9ad6053c4c4124c83da9a7919778bcc52 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21399 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-03sim-se: Fix invalid delete of params on cloneJason Lowe-Power
The params pointer is kept by the SimObject and should not be deleted until gem5 exits. Added a to do to remember this object is leaked. Change-Id: I46cc23a09e4e9b6bc2fdcd961148324c41820815 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18068 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
2019-10-03arch-arm: Annotate CM flag in AA64 CM InstructionsGiacomo Travaglini
DC ZVA instruction is not classified as a cache maintenance instruction, and therefore its execution cannot cause this field to be set to 1. Change-Id: I0f30db1e6fc629dc52293edfb2bac4cf99ee49cc Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21306 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-10-03arch-arm: Set CM bit in DataAbortGiacomo Travaglini
The CM bit in a DataAbort ISS indicates whether the Data Abort came from a cache maintenance or address translation instruction. Change-Id: I8888520446550581c8dd0507a8989935db7047be Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21305 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-02sim: Mark System::getThreadContext method as constGiacomo Travaglini
Change-Id: Ic0ce1b098cfe0ce6ea37986a8a55002a5c18a66c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21304 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-02dev-arm: Improve fault message on SMMUv3 translation faultMarc Mari Barcelo
Change-Id: Ib1d7ae73951b52f2378f8bd50e804d3237f74074 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21303 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-02dev-arm: Fix address used to update the SMMUv3 Walk CacheMarc Mari Barcelo
Last level of SMMUv3 WalkCache should store the address without an offset. Change-Id: I1046bd8210500c2c38802acd41a4403e52fd3c90 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21302 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-02arch-arm: Create helper for sending events (SEV)Giacomo Travaglini
Events can be generated by devices, so we need an interface devices can use to notify events to PEs. Change-Id: I330575e7d116388d5f9260ef4400b0feaa861f3e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21301 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-02fastmodel: Get rid of the back channel mem port in FastModel::ArmCPU.Gabe Black
This was to support port proxies and getInstPort and getDataPort. With some recent upstream changes, getInstPort and getDataPort are only used for CPU switching which we can't support (TLM ports are bound permanently), and with the sendFunctional delegate for port proxies, we don't need to have a traditional gem5 port lying around. This gets rid of the "mem" port and all its plumbing. Change-Id: Ic68a40a26b24aa05b33da0510c9f4b7621cbf578 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21048 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-10-02fastmodel: Implement a custom sendFunctional for CortexA76x1.Gabe Black
Change-Id: I28094620106a8edd90e1144b4fb87ae5729ebf32 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21047 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-10-02x86: Switch from MessageReq and Resp to WriteReq and Resp.Gabe Black
Originally MessageReq was intended to mark a packet as a holding a message destined for a particular recipient and which would not interact with other packets. This is similar to the way a WriteReq would behave if writing to a device register which needs to be updated atomically. Also, while the memory system *could* recognize a MessageReq and know that it didn't need to interact with other packets, that was never implemented. Change-Id: Ie54301d1d8820e206d6bae96e200ae8c71d2d784 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20823 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-10-02fastmodel: Let the EVS set an attribute for getSendFunctional to return.Gabe Black
The iris CPU model doesn't necessarily know the best way to send functional packets (what port? what type is that port?), but only has a generic sc_module pointer to the EVS and so can't call specialized methods on it. There also isn't any common base class for EVSes to cast into in a generic way. This attribute mechanism lets the EVS set up its own sendFunctional implementation however it needs to using facilities that are built into generic sc_objects. Change-Id: I69bf364908c2a5360bd6ce7d3e49ce67c6f771b0 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21046 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-10-01style: normalize filename in SortedIncludes.fix()Georg Kotheimer
The filename affects the sorting result. Therefore check(), which normalizes the filename, detects an invalid sorting of includes, but fix() fails to fix the corresponding includes. Change-Id: I7d5a941c9ebea853004922d19e3b84f8ded2afa6 Signed-off-by: Georg Kotheimer <georg.kotheimer@mailbox.tu-dresden.de> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/10742 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-10-01fastmodel: Add a gem5Cpu attribute to the CortexA76x1.Gabe Black
This attribute is to let the fast model EVS CPU find and talk to the gem5 CPU in case it needs a pointer to one of its ThreadContexts for instance. Also move the code that finds the clock period attribute/event to the constructor. gem5 guarantees that the EVS is constructed before its pointer is passed to the iris CPU wrapper, and so the EVS will have had a chance to install those controls if it's going to. Change-Id: I389ef0ba0f9d528140f40444baa5091a9ec338cd Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21045 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-01fastmodel: Add a utility class which makes it easier to watch signals.Gabe Black
These signals come from the exported virtual subsystem and could signal interrupts, etc. The new SignalReceiver class makes it easier to watch those signals and perform some behavior when they change without having to bring along a lot of systemc baggage. Change-Id: I09651de1dd0e7340a61779aaf080c695ce299fd4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21043 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-01fastmodel: Pull out and simplify the interrupt mechanism in the GIC.Gabe Black
This change pulls out the SPI and PPI command structures and replaces them with a custom protocol which can deliver a SPI or PPI without having to bundle their parameters into a structure. Change-Id: I8f15c8b3182bd6560bf5ef0345b0bc64173def85 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21042 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-01mem-cache: Fix invalid whenReadyDaniel R. Carvalho
When a writeback needs to be allocated the whenReady field of the block is not set, and therefore its access latency calculation uses the previously invalidated value (MaxTick), significantly delaying execution. This is fixed by assuming that the data write portion of a write access is done regardless of previous writes, and that only the tag latency is important for the critical path latency calculation. Change-Id: I739132a2deab6eb4c46d084f4ee6dd65177873fd Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20068 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-10-01configs: Port PlatformConfig to the common object listDaniel R. Carvalho
Port PlatformConfig to use the common object list. Change-Id: If62e596bf1f28b49994da3a2800450d163383755 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20593 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-10-01configs: Port MemConfig to the common object listDaniel R. Carvalho
Port MemConfig to use the common object list. Change-Id: If421c2745ac3431718a5170314045b456fc64a90 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20592 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2019-10-01configs: Port HWPConfig to the common object listDaniel R. Carvalho
Port HWPConfig to use the common object list. Change-Id: I86db6b872808f754193dbf5814dd6c951c8f1980 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20591 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-10-01configs: Port BPConfig to use the common object listDaniel R. Carvalho
Port BPConfig to use the common object list. Change-Id: I5cbd1c67cf743778bc59b5aa3c3dea5ab397b66d Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20590 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-30configs: Port CPUConfig to use the common object listDaniel R. Carvalho
Factor out ObjectList functionality from CPUConfig. Change-Id: I34ca55142e14559e584d38b6cca3aa5c20923521 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20589 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-30configs: Create a basic ObjectListDaniel R. Carvalho
There are multiple files that reimplement the same functionality of listing and getting available modules for class instantiation. Create a base class that can be derived and reduce code duplication. Change-Id: I96bf47b1ffd10893691b0b95591969b38894dd65 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20588 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-30configs: Remove is_atomic_cpu checkDaniel R. Carvalho
Commit 224f2d50a9873d054f486d7661d947db76f4cf68 removed all instances of is_atomic_cpu. Change-Id: I1101fbdbc16dc5d093ab87d3817308176559a548 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20659 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-09-30mem-ruby: Remove inexistent functions from UtilDaniel R. Carvalho
Remove forward declaration of inexistent functions from RubySlicc_Util.sm. Change-Id: I548bd75cb570371fbdaccf914c5eb9a7b92313d1 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21086 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-30mem-ruby: Make bitSelect use bits<Addr>Daniel R. Carvalho
There is no need to replicate bits<Addr>' functionality. As a side effect, ADDRESS_WIDTH is no longer used and was removed Change-Id: Ia5679f3976c81f779665d82cb758850092f2a293 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21085 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-30mem-ruby: Fix maskLowOrderBitsDaniel R. Carvalho
The function was wrong when number = 63. Also, use the more reliable src/base/bitfield.hh's mbits when posible. maskLowOrderBits has only been kept because SLICC does not accept a templated function. Change-Id: I8dd680da02ceb9e614e2f9cbf8f1ac52cead8d45 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21084 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-30mem-ruby: Remove shiftLowOrderBitsDaniel R. Carvalho
There is no need to encapsulate a shift operation. Change-Id: Ie711d8d4975d1d9dde656cc2284a048410cfdadb Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21083 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-30mem-ruby: Remove maskHighOrderBitsDaniel R. Carvalho
Function was not being used. If needed, src/base/bitfield.hh's mbits can be used instead: maskHighOrderBits(addr, pos) == mbits<Addr>(addr, 64-pos, 0) Change-Id: I3abd041f8d256ec157ba7502182d8588721c2a05 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21082 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-30mem-ruby: Remove bitRemoveDaniel R. Carvalho
bitRemove is not being used anywhere. If needed, can be used as src/base/bitfield.hh's bits: bitRemove(addr, small, big) == ((bits<Addr>(addr, 63, big + 1) << small) | bits<Addr>(addr, small, 0)) Change-Id: I45fd3bc0271ccb659d6a94e3dd00ca095dfd6aa7 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21081 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-30cpu: Make use of DRAMCtrl::AddrMap in the traffic generatorsNikos Nikoleris
Use the enum defined in the memory controller rather than custom strings and int that are later converted to the DRAMCtrl::AddrMap enum. Change-Id: Ie5b19f915f9990fd2b7505d4d1b17b6fc2100f9e Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21080 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-30misc: Added line wrapping functionality for Sim-Object descBobby R. Bruce
Descriptions were previously printed on one line, unless explicitly broken when writing the description of the Sim-Object. In this commit, line wrapping is enabled when printing these descriptions. Developers, when writing the Sim-Object descriptions, may now over multiple lines with triple double-quotes and still have the description output correctly when viewing the Sim-Objects within the CLI. E.g.: X86System previously had the following load_addr_mask component which was output as: load_addr_mask default: 18446744073709551615 desc: Address to mask loading binaries with, if 0, system \ auto-calculates the mask to be the most restrictive, otherwise it obeys a \ custom mask. This was defined by the developer via: load_addr_mask = Param.UInt64(0xffffffffffffffff, "Address to mask loading binaries with, if 0, system " "auto-calculates the mask to be the most restrictive, " "otherwise it obeys a custom mask.") This is now displayed as: load_addr_mask default: 18446744073709551615 desc: Address to mask loading binaries with, if 0, system auto-calculates the mask to be the most restrictive, otherwise it obeys a custom mask. JiraID: Gem5-57 Built: Linux (GCC) Tested: Ran quick tests for X86, ARM, and RISC-V Change-Id: If012304e50af60f6ba10c1fa2b44da8bac1c09cf Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21179 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-30mem: Use new-style stats in the XBar modelsAndreas Sandberg
Migrate to new-world stats with an explicit hierarchy in all of the XBar models. Change-Id: I18b6746a1303ca415638e6d382fb4757607f1123 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21141 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-09-30mem-cache: Switch to new-style statsAndreas Sandberg
This change puts cache and tag stats into a Stats::Group struct. This makes it easier to identify stat updates (they are prefixed with stat.) and adds hierarchy information for output formats that need it. Change-Id: I2b8e9138f1cb977abb445ec864d80a79b588481d Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21140 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-30mem: Convert DRAM controller to new-style statsAndreas Sandberg
Note that this changes the stat format used by the DRAM controller. Previously, it would have a structure looking a bit like this: - system - dram: Main DRAM controller - dram_0: Rank 0 - dram_1: Rank 1 This structure can't be replicated with new-world stats since stats are confined to the SimObject name space. This means that the new structure looks like this: - system - dram: Main DRAM controller - rank0: Rank 0 - rank1: Rank 1 Change-Id: I7435cfaf137c94b0c18de619d816362dd0da8125 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21142 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-21 19:15:20 +0000