Age | Commit message (Expand) | Author |
2012-01-28 | Merge with the main repo. | Gabe Black |
2012-01-27 | ns_gige: Fix a missing curly brace in if-statement | Andreas Hansson |
2012-01-26 | configs: actually add ARMv7a-like cpu/cache file | Ronald Dreslinski |
2012-01-26 | configs: A more realistic configuration of an ARM-like processor | Ronald Dreslinski |
2012-01-25 | MEM: Fix fs.py by specifying the range size rather than end | Andreas Hansson |
2012-01-16 | Merge yet again with the main repository. | Gabe Black |
2012-01-12 | Fix memory corruption issue with CopyStringOut() | Mitchell Hayenga |
2012-01-25 | stats: Update stats for final tick and memory bandwidth patches | Ali Saidi |
2012-01-25 | sim: display final value of curTick in stats | Ali Saidi |
2012-01-25 | Mem: Add simple bandwidth stats to PhysicalMemory | Ali Saidi |
2012-01-23 | Config: Enable using O3 CPU and Ruby in SE mode | Nilay Vaish |
2012-01-23 | O3, Ruby: Forward invalidations from Ruby to O3 CPU | Nilay Vaish |
2012-01-23 | MemCmd: Add a command for invalidation requests to LSQ | Nilay Vaish |
2012-01-17 | MEM: Make the bus default port yet another port | Andreas Hansson |
2012-01-17 | MEM: Removing the default port peer from Python ports | Andreas Hansson |
2012-01-17 | MEM: Make the bus bridge unidirectional and fixed address range | Andreas Hansson |
2012-01-17 | MEM: Remove the functional ports from the memory system | William Wang |
2012-01-17 | MEM: Separate queries for snooping and address ranges | Andreas Hansson |
2012-01-17 | MEM: Remove Port removeConn and MemObject deletePortRefs | Andreas Hansson |
2012-01-17 | MEM: Remove the notion of the default port | Andreas Hansson |
2012-01-17 | MEM: Simplify ports by removing EventManager | Andreas Hansson |
2012-01-17 | CPU: Moving towards a more general port across CPU models | Andreas Hansson |
2012-01-17 | MEM: Add port proxies instead of non-structural ports | Andreas Hansson |
2012-01-17 | Ruby: Change the access permissions for MOESI hammer | Andreas Hansson |
2012-01-17 | Ruby: Change the access permissions for MOESI hammer | Andreas Hansson |
2012-01-17 | MEM: Add the system port as a central access point | Andreas Hansson |
2012-01-17 | MEM: Differentiate functional cache accesses from CPU and memory | Andreas Hansson |
2012-01-16 | stats: undo parser change from initparam change | Ali Saidi |
2012-01-16 | Alpha: warn_once about broken PAL breakpoints. | Steve Reinhardt |
2012-01-16 | debug: fix AllFlags::disable() | Steve Reinhardt |
2012-01-12 | inorder: MDU deadlock fix | Maximilien Breughe |
2012-01-12 | mips: compatibility between MIPS_SE and cross compiler from CodeSorcery | Deyuan Guo |
2012-01-12 | mips: Fix bugs in faults.cc/hh and tlb.cc for MIPS_FS | Deyuan Guo |
2012-01-12 | mips: Fix decoder of two float-convert instructions | Deyuan Guo |
2012-01-12 | mips: definition of MIPS64_QNAN in registers.hh | Deyuan Guo |
2012-01-12 | PerfectCacheMemory: Remove references to CacheMsg | Nilay Vaish |
2012-01-11 | Packet: Put back part of the assert | Ali Saidi |
2012-01-11 | Packet: Remove meaningless assert statement | Ali Saidi |
2012-01-11 | Ruby: Use map option for selecting b/w sparse and memory vector | Nilay Vaish |
2012-01-11 | Config: Add support for restoring using a timing CPU | Nilay Vaish |
2012-01-11 | Ruby: Resurrect Cache Warmup Capability | Nilay Vaish |
2012-01-11 | Ruby Debug Flags: Remove one, add another | Nilay Vaish |
2012-01-11 | Ruby Port: Add a list of cpu ports attached to this port | Nilay Vaish |
2012-01-11 | Ruby EventQueue: Remove unused functions | Nilay Vaish |
2012-01-11 | Ruby Sparse Memory: Add function for collating blocks | Nilay Vaish |
2012-01-11 | Ruby: Add infrastructure for recording cache contents | Nilay Vaish |
2012-01-11 | Ruby Memory Vector: Functions for collating and populating pages | Nilay Vaish |
2012-01-10 | Ruby: remove the files related to the tracer | Nilay Vaish |
2012-01-10 | hgfilesize: skip files that have been removed | Nathan Binkert |
2012-01-10 | MOESI Hammer: Update regression test output | Nilay Vaish |