gem5 - gem5

Age	Commit message (Expand)	Author
2019-06-10	python: Add binding for the new AddrRange c++ constructor	Nikos Nikoleris
2019-06-10	base: Extend unit tests for AddrRange	Nikos Nikoleris
2019-06-10	base: Extend AddrRange to support more flexible addressing	Nikos Nikoleris
2019-06-10	base: Fix ctz32 for systems where unsigned int is not 32bit	Nikos Nikoleris
2019-06-10	base: Add function to count trailing zeros in a 64-bit integer	Nikos Nikoleris
2019-06-10	scons: allow passing arbitrary CCFLAGS and LDFLAGS from the CLI	Ciro Santilli
2019-06-10	arch-arm: implement VMINNM scalar thumb	Ciro Santilli
2019-06-09	base: Provide a getter for Fiber::started boolean variable	Giacomo Travaglini
2019-06-09	base: Rename TestFiber into SwitchingFiber	Giacomo Travaglini
2019-06-07	arch-arm: Fix WalkerState,Descriptors default constructor	Giacomo Travaglini
2019-06-06	dev-arm: Implement a SMMUv3 model	Stanislaw Czerniawski
2019-06-06	mem: Option to toggle DRAM low-power states	Matthew Poremba
2019-06-05	mem-ruby: Enable set size increase	John Alsop
2019-06-04	base: Fix missing headers to CircularQueue	Daniel R. Carvalho
2019-06-04	Revert "mem-cache: Remove writebacks packet list"	Daniel Carvalho
2019-06-03	cpu: Added the Multiperspective Perceptron Predictor (8KB and 64KB)	Javier Bueno
2019-05-31	x86: fix movsd bug on %xmm register	Brandon Potter
2019-05-31	config, arm: memoryMode test	Willy Wolff
2019-05-31	arm: Fix decoding of CRC32 instructions in thumb32	Chun-Chen TK Hsu
2019-05-31	cpu-o3: Increase LSQ buffer sizes to match max vector length	Gabor Dozsa
2019-05-31	arch-arm: Treat SVE prefetch instructions as no-ops	Giacomo Gabrielli
2019-05-30	arch-arm: Add initial support for SVE gather/scatter loads/stores	Giacomo Gabrielli
2019-05-30	cpu: Fix rescheduling of progress check events	Tiago Muck
2019-05-30	arch: Add include guards to auto-gen. decode header	Giacomo Gabrielli
2019-05-30	cpu-o3: Add support for pinned writes	Giacomo Gabrielli
2019-05-30	arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy.	Gabe Black
2019-05-30	cpu: Store the translating proxy with the same pointer in SE or FS mode.	Gabe Black
2019-05-30	cpu, sim: Return PortProxy &s from all the proxy accessors.	Gabe Black
2019-05-30	kern: Replace an explicitly instantiated port proxy with one from the tc.	Gabe Black
2019-05-30	arch, base, sim: Demote (SE\|FS)TranslatingPortProxy &s to PortProxy &s.	Gabe Black
2019-05-30	mem: Remove the now unused Copy* methods from the FS port proxy.	Gabe Black
2019-05-30	arch, base, sim: Replace Copy(String)?(In\|Out) with equivalent code.	Gabe Black
2019-05-29	sim-se: const for loader's loadSection param	Brandon Potter
2019-05-29	cpu: Added correct return type for ROB::countInsts	Andrea Mondelli
2019-05-29	mem-cache: Accuracy-based rate control for prefetchers	Javier Bueno
2019-05-29	sim-se: add a release parameter to Process.py	Ciro Santilli
2019-05-29	mem-cache: Support for page crossing prefetches	Javier Bueno
2019-05-29	mem: Add a readString method to the PortProxy which takes a char *.	Gabe Black
2019-05-29	mem: Use a const T & in write<> to avoid an unnecessary copy.	Gabe Black
2019-05-29	arch, base, dev, sim: Remove now unnecessary casts from PortProxy methods.	Gabe Black
2019-05-29	mem, arm: Replace the pointer type in PortProxy with void *.	Gabe Black
2019-05-29	mem, arm: Move some helper methods into the base PortProxy class.	Gabe Black
2019-05-29	arm, mem: Move the SecurePortProxy subclass into it's own file.	Gabe Black
2019-05-28	mem: Parameterize coherent xbar sanity checks	Tiago Muck
2019-05-28	mem: Snoop filter support for large systems	Tiago Muck
2019-05-28	base: Add warn_if_once macro	Tiago Muck
2019-05-28	cpu: Remove assert causing issues with x86 Linux boot	Giacomo Gabrielli
2019-05-24	arch-arm: Fix fallthrough when trapping at EL2	Giacomo Travaglini
2019-05-23	arch-arm: Trap virtual accesses to GICv3 SGI registers	Giacomo Travaglini
2019-05-23	arch-arm: Expose haveGicv3CPUInterface to the ISA interface	Giacomo Travaglini