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2019-09-06dev: Fix segmentation fault in VirtIOBlockChun-Chen TK Hsu
GEM5 got a segmentation fault when the size is large in VirtIOBlock::write. This change uses a vector to avoid this segmentation fault. Signed-off-by: Chun-Chen TK Hsu <chunchenhsu@google.com> Change-Id: I26272686a6e7e39cdf2389657ecd38ce90261144 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20679 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06arch-arm: fix GDB stub after SVECiro Santilli
The SVE patches made registers longer by increasing NumVecElemPerVecReg, but the GDB XML was not updated to account for that, and as a result GDB connections were failing with: Remote 'g' packet reply is too long This commit introduces NumVecElemPerSimdVecReg which counts only the SIMD register sizes to get it back working. SVE GDB support is not added here. Change-Id: I4191b9f1999ae02b0308863db4cc9b5b16a27d6d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20468 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev-arm: Rewrite ICC_BPR0/ICC_BPR1 handlingGiacomo Travaglini
The patch is fixing BPR reads in AA32, by removing the line Gicv3::GroupId group = misc_reg == MISCREG_ICC_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1S; Where a read to ICC_BPR0 will return a G1S group. The patch is also fixing Security banking accesses. Change-Id: I28f1d1244c44d4b8b202d3141f8380943c7c1c86 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20620 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev-arm: Add GICv3 unimplemented Hyp Active Priorities Group regsGiacomo Travaglini
ICH_APxR1, ICH_APxR2, ICH_APxR3 are implemented only if supporting more than 6 bits of priority. Since this is not the case, they are currently unimplemented. According to spec, unimplemented registers are RAZ/WI. Change-Id: Ifd7f7a3d42b4575c2f7aff3b95d5a47ac1e61842 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20619 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev-arm: Allow 32-bit access to GITS_TYPERGiacomo Travaglini
Change-Id: I9d19174b38ba70f82050102f955ccc162965d1fb Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20618 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev-arm: Cpu interface groupEnabled check for global enableGiacomo Travaglini
Gicv3CPUInterface::groupEnabled should check for global enable flags at distributor level: - Gicv3Distributor.EnableGrp0 - Gicv3Distributor.EnableGrp1S - Gicv3Distributor.EnableGrp1NS Change-Id: I1c855b0e4c2bc8f1cd0a8f086b9450f516177b08 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20617 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev-arm: Check if INTID group is enabled when reading HPPIRxGiacomo Travaglini
If it is not enabled, it should return INTID_SPOURIOUS Change-Id: I4dfa8b9fcea874b4d281cd154dd38752b05e1d59 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20616 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev-arm: Writing GICD_CTLR should trigger an updateGiacomo Travaglini
This is the case where an interrupt is pending, but the distributor is masking it. As soon as the group gets enabled, the interrupt should be forwarded to the PE. Change-Id: Ie428780bde7e4726688adf78dfcc4d43d1b45261 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20615 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev-arm: Rewrite GICv3 updateGiacomo Travaglini
The GICv3 update methods are method which are invoked anytime the model needs to evaluate a change in its state, which most of the time means managing the state of an interrupt (forwarding it to a PE, deasserting it, etc). The way it is currently done is a little bit obscure and doesn't handle correctly IRQ prioritization. Example: An IRQ which is handled by the redistributor (PPI or LPI) was not competing with any pending interrupts coming from the distributor (SPIs) once raised by a peripheral. Also the way the pending state of an interrupt was removed at the cpu interface level wasn't happening in place where this was actually happening (E.g. when activating it), but happened with a weird fullUpdate semantic, where if there was a pending interrupt in a cpu interface, all cpu interfaces had their pending interrupt (if any) been disabled. With this patch, state update always starts at the distributor, and it goes down until the cpu interface where a Gicv3CPUInterface::update method selects the winning interrupt coming from distributor/redistributor to be forwarded to the PE. Change-Id: I1c517cbc4bf107cc2d7ae7beb2692e3cf5187a40 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20614 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev-arm: Fix GICv3 IGRPMOD writesGiacomo Travaglini
Writes to IGRPMOD were not right shifting the value, which resulted in interrupts having a IGRPMOD value > 1, whereas the only allowed values are 0 and 1. Change-Id: Id491bd1b184d6e5abeeea25ea272eeb91792ccf7 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20613 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06arch-arm: SGI registers undecoded in AArch32Giacomo Travaglini
Change-Id: I64d3e639e1beaa507263637d59499aafeb5a19f8 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20612 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06arch-arm: Fix read/setMiscReg for AArch32 GICv3 ICC regsGiacomo Travaglini
The readMiscReg/setMiscReg methods were not forwarding register reads/writes to the cpu interface when in AArch32. Change-Id: Ide983e793b8033a88d31fe6ea87eaeffe9b093f5 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20611 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-06dev-arm: Fix SGI generationGiacomo Travaglini
The patch is fixing the following aspects of SGIs * The conditons over which an SGI can be forwarded to a PE * SGIs in AArch32 (see below) It is in fact refactoring SGI generation under a common method in the cpu interface. It is abandoning the implicit fallthrough mechanism not only for cosmetic reasons, but also because checking "misc_reg ==" was only working if the register was an AArch64 one (e.g. MISCREG_ICC_SGI0R_EL1) and not the AArch32 counterpart (MISCREG_SGI0R). Change-Id: I6fedfb80388666f4f1d20f6abef378a9f093aa83 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20610 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev-arm: Gicv3 ITS device tree autogenAdrian Herrera
This patch adds device tree automatic generation for Gicv3 ITS. Change-Id: Ic01500ffa691b331f527c5c2c785ff715660b0c2 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20609 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev-arm: modify GICv3 ITS default addrAdrian Herrera
The current default base address for GICv3 ITS stated in RealView is 0x2c120000. The redistributors base address is 0x2c010000; each instantiated core has an associated redistributor with memory region size 0x40000 (with GICv4 extension, enabled by default). With 8 cores, the redistributor range spans to 0x2c210000, creating a conflict with the ITS address space. This patch changes the ITS base address to 0x2e010000 which guarantees no overlapping with the redistributor. Change-Id: I7dc1af9e69ac037f85ae96f0985554f1fb8372a0 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20608 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-05arch-x86: Adding warning for movntiPouya Fotouhi
We are ignoring the non-temporal hint here, and implementing this instruction as a cacheable instruction. This change adds a warning to let user know about this workaround. Change-Id: I2e40437a44282fe9cf7772a25a8870bd8729a6ed Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20428 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-09-05dev-arm: Improper translation slot release in SMMUv3Giacomo Travaglini
The SMMUv3SlaveInterface is using the xlateSlotsRemaining to model a limit on the number of translation requests it can receive from the master device. Patch https://gem5-review.googlesource.com/c/public/gem5/+/19308/2 moved the resource acquire/release inside the SMMUTranslationProcess constructor/destructor, for the sake of having a unique place for calling the signalDrainDone. While this is convenient, it breaks the original implementation, which was freeing resources AFTER a translation has completed, but BEFORE the final memory access (with the translated PA) is performed. In other words the xlateSlotsRemaining is only modelling translation slots and should be release once the PA gets produced. The patch fixes this mismatch by restoring the resource release in the right place (while keeping the acquire in the constructor) and by adding a pendingMemAccess counter, which is keeping track of a complete device memory request (translation + final access) and will be used by the draining logic Change-Id: I708fe2d0b6c96ed46f3f4f9a0512f8c1cc43a56c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Adrian Herrera <adrian.herrera@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20260 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-05dev-arm: Implement invalidateASID in SMMUv3 WalkCacheJan-Peter Larsson
This patch fixes a bug where issuing a invalidate-by-ASID command (CMD_TLBI_NH_ASID) to the SMMU would cause Gem5 to crash. Change-Id: I5b8343a17e43762fe3917560ae401a20be1e05b8 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20259 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-05dev-arm: Implement invalidateVA/VAA in SMMUv3 WalkCacheAdrian Herrera
This patch implements VA/VAA invalidations in the SMMUv3 model. As per SMMUv3.0 spec, if leaf bit is specified in the invalidation command, only leaf entries within the walk cache need to be invalidated, otherwise entries with intermediate translations are also invalidated. Change-Id: I0eb1e1f1d8c00671a3c23d2a8fb756f2020d8d46 Reviewed-by: Michiel van Tol <michiel.vantol@arm.com> Reviewed-by: Marc Mari Barcelo <marc.maribarcelo@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20258 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-05arch-x86: implement movntq/movntdq instructionsPouya Fotouhi
Non-temporal quadword/double-quadword move instructions. This change ignores the non-temporal hint and instructions are implemented to send cacheable request to memory. This would have some "performance" impact (i.e. having some cache pollution) to get better "correctness" in behavior. Change-Id: I2052ac0970f61a54bafb7332762debcb7103202d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20288 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-09-04cpu: reset byte_enable across writeMem callsCiro Santilli
data_write_req byteEnable which is used in ARM SVE partial writes was not being zeroed between writes. As a result, non-SVE memory write instructions such as STP that followed SVE memory write instructions could still have the write mask active. This could lead to wrong simulation behaviour, and to an assertion failure: src/mem/packet.hh:1211: void Packet::writeData(uint8_t*) const: Assertion `req->getByteEnable().size() == getSize()' failed. '` Change-Id: I74b5a82675e9923b0ffdf2c1dd9afb00c91cb204 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20448 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-04dev: Templatize PioPort.Gabe Black
When creating a base class which needs to be a SimObject, it's necessary to decide ahead of time whether to use PioDevice or BasicPioDevice in the hierarchy because they inherit from SimObject. If they were added into the hierarchy later, then the original class would inherit from SimObject, as would PioDevice. That would create a diamond inheritance structure which would require virtual inheritance, and that's a can of worms we'd rather not get into. A big part of the PioPort mechanism is the PioPort itself which holds a pointer to its parent device and delegates reads/writes to it. It does that with a PioDevice pointer, and PioDevice declares virtual functions for all the callbacks the port can call into. Instead of that, this change templatizes PioPort based on the class of the device that holds it. That will let you use a PioPort on *any* class, as long as it has the methods PioPort depends on. That removes the need to create an inheritance diamond to add a PioPort down the line since PioDevice is no longer strictly required. The PioDevice and BasicPioDevice classes are still around since they still provide some additional functionality and there are existing classes which depend on them. Change-Id: I753afc1e0fa54b91217d54c1f8743c150537e960 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20568 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-03ruby: Fix the way stall map size is checked for availabilitySrikant Bharadwaj
To ensure that enqueuer observes the practical availability. We check the message buffer queue size at the start of the cycle. We also add the size of the stall queue to consider the total queue size. However, messages can be moved from regular queue to stall map. This leads to messages being considered twice leading to false flow control. This patch fixes it by storing the stall map size at the beginning of the cycle and considering it for checking availability. Change-Id: I6ea94f34fe5279b91f74e106d43263e55ec4bf06 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20389 Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-09-03configs: Fix replacement policy assignmentDaniel R. Carvalho
Commit d207e9ccee411877fdeac80bb68a27900560f50f reworked the tags to split the replacement policies, however the name of the variable that contains the replacement policy changed between patch revisions, which was not updated accordingly in the configs files. Change-Id: I2072529e2c7d54197c371bcaa323bfd9f34ec3ba Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20548 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-02stats: Create HDF5 stat files relative to simoutAndreas Sandberg
When using the HDF5 stats backend, we currently pass the filename from the command line straight to the HDF5 library. This behaviour is different from the expected behaviour when using plain text stat files where relative paths are resolved relative to simout. This change adds support for resolving hdf5 paths relative to simout. Change-Id: I09cb0b7468735e697125eda7f04c5a85725ca8d0 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20508 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-09-02stats: Catch exceptions by const referenceDoğukan Korkmaztürk
Catching exceptions by value causes -Werror=catch-value= to be triggered during a build process. This change replaces the values with const references in the catch blocks. Change-Id: Iddabb595c5916d8120dcdb08e2c2f36ff21c3c9b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20528 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-02stats: Add support for listing available formatsAndreas Sandberg
Add a command line option to list available stat formats and their documentation. Change-Id: I7f5f2272d9b0176639f59f2efedb9cab2f7da5b9 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19670 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-30arm,kvm: Fix python imports from global namespaceGiacomo Travaglini
Change-Id: I31bd3563c2427efd7e520f714b1ca6f480fa4e85 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20491 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-29mem-cache: Use SatCounter for RRPVDaniel R. Carvalho
Use SatCounter in RRIP's RRPV. As such, move validation functionality to a proper variable. Change-Id: I142db2b7f6cd518ac3a2b68c9ed48005402b3464 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20452 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-29base: Add function to saturate SatCounterDaniel R. Carvalho
Create a saturation function for the SatCounter that makes its internal counter reach its maximum value. Change-Id: Ibd30fa27c4ae2714dd48e3eba85addd035fb737c Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20451 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-29stats: Add beta support for HDF5 stat dumpsAndreas Sandberg
This changeset add support for stat dumps in the HDF5 file format. HDF5 is a binary data format that represents data in a file-system-like balanced tree. It has native support for N-dimensional arrays and binary data (e.g., frame buffers). It has the following benefits over traditional text stat files: * Efficient storage of time series (multiple stat dumps) * Fast lookup of stats * Plenty of existing tooling (e.g., Python libraries and graphical viewers) * File format can be used to store frame buffers together with normal stats. Drawbacks: * Large startup cost (single stat dump larger than text equivalent) * Stat dumps are slower than text Known limitations: * Distributions and histograms aren't supported. HDF5 stat output can be enabled using the 'h5' URL scheme when overriding the stat file name on gem5's command line. The following parameters are supported: * chunking (unsigned): Number of time steps to pre-allocate (default: 10) * desc (bool): Output stat descriptions (default: True) * formulas (bool): Output derived stats (default: True) Example gem5 command line: ./build/ARM/gem5.opt \ --stats-file="h5://stats.h5?desc=False;formulas=False" \ configs/example/fs.py Example Python stat consumer that computes IPC: import h5py f = h5py.File('stats.h5', 'r') group = f['/system/cpu'] for i, c in zip(group['committedInsts'], group['numCycles']): print i, c, i / c Change-Id: I351c6cbff2fb7bef9012f47876ba227ed288975b Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/8121 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
2019-08-29mem: Convert CommMonitor to the new stat frameworkAndreas Sandberg
Change-Id: I851c29909f3e6923c0233505a4d0f2d266bc254f Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19371 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-08-29cpu: Convert traffic gen to use new statsAndreas Sandberg
Change-Id: Ife690a137c2dcfb6bcc8b22df996c84f0d231618 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19370 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-08-29stats: Add support for partial stat dumpsAndreas Sandberg
Add support for partial stat dumps by passing an optional 'root' keyword argument to m5.stats.dump(). Specifying root slightly changes the semantics of the dump command. For legacy reasons, gem5 only allows one stat dump per tick. This is likely a limitation introduced as a hack to prevent automatic dumping at the end of simulation from interfering with explicit dumping from a simulation script. This restriction does not apply when specifying a root. However, these stat dumps will still prevent an additional stat dump in the same tick with an unspecified root. N.B.: This new API /only/ works for new-style stats that have an explicit hierarchy. Legacy stats will not be dumped if a root is specified. Change-Id: Idc8ff448b9f70a796427b4a5231e7371485130b4 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19369 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-29stats: Add support for hierarchical statsAndreas Sandberg
This change makes the stat system aware of the hierarchical nature of stats. The aim is to achieve the following goals: * Make the SimObject hierarchy explicit in the stat system (i.e., get rid of name() + ".foo"). This makes stat naming less fragile and makes it possible to implement hierarchical formats like XML/HDF5/JSON in a clean way. * Make it more convenient to split stats into a separate struct/class that can be bound to a SimObject. This makes the namespace cleaner and makes stat accesses a bit more obvious. * Make it possible to build groups of stats in C++ that can be used in subcomponents in a SimObject (similar to what we do for checkpoint sections). This makes it easier to structure large components. * Enable partial stat dumps. Some of our internal users have been asking for this since a full stat dump can be large. * Enable better stat access from Python. This changeset implements solves the first three points by introducing a class (Stats::Group) that owns statistics belonging to the same object. SimObjects inherit from Stats::Group since they typically have statistics. New-style statistics need to be associated with a parent group at instantiation time. Instantiation typically sets the name and the description, other parameters need to be set by overriding Group::regStats() just like with legacy stats. Simple objects with scalar stats can typically avoid implementing regStats() altogether since the stat name and description are both specified in the constructor. For convenience reasons, statistics groups can be merged into other groups. This means that a SimObject can create a stat struct that inherits from Stats::Group and merge it into the parent group (SimObject). This can make the code cleaner since statistics tracking gets grouped into a single object. Stat visitors have a new API to expose the group structure. The Output::beginGroup(name) method is called at the beginning of a group and the Output::endGroup() method is called when all stats, and sub-groups, have been visited. Flat formats (e.g., the text format) typically need to maintain a stack to track the full path to a stat. Legacy, flat, statistics are still supported after applying this change. These stats don't belong to any group and stat visitors will not see a Output::beginGroup(name) call before their corresponding Output::visit() methods are called. Change-Id: I9025d61dfadeabcc8ecf30813ab2060def455648 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19368 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2019-08-28mem-ruby: Define BloomFilter namespaceDaniel R. Carvalho
Define a BloomFilter namespace and put all BloomFilter related code in it. As a side effect the BloomFilter classes have been renamed to remove the "BloomFilter" suffix. Change-Id: I3ee8cc225bf3b820e561c3e25a6bf38e0012e3a8 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18874 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-28mem-ruby: Make H3 inherit from MultiBitSelBloomFilterDaniel R. Carvalho
Make MultiBitSelBloomFilter a generic BloomFilter that maps multiple entries to an address, and therefore uses multiple hash functions. This allows the common functionality of both filters to be merged into one, since they only differ in the hash functions being used. Change-Id: I0984067b710a208715f5f2727b8c4312feb6529b Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18873 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-28mem-ruby: Finish implementing BloomFilter mergeDaniel R. Carvalho
Not all Bloom Filters had their union functionality implemented. This change adds them. Change-Id: I86af18d3c5eabd0da8280b57a88789b3af803c04 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18872 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-08-28mem-ruby: Remove NonCountingBloomFilterDaniel R. Carvalho
Make BlockBloomFilter accept having a single bitfield, in which case it behaves exactly as the NonCountingBloomFilter, and thus the latter can be removed. Change-Id: I56d96a89290c933293ce434bbe0e8bcd4bbcaa42 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18871 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-28mem-ruby: Make MultiGrainBloomFilter genericDaniel R. Carvalho
Allow combining any number of Bloom Filters in the MultiGrain. Change-Id: I73ae33063e1feed731af6f625d2f64245f21df18 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18869 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-28mem-ruby: Parameterize xor bits in BlockBloomFilterDaniel R. Carvalho
Parameterize bitfield ranges in BlockBloomFilter such that the hash is applied between masked bitfields of an address. Change-Id: I008bd873458e9815e98530e308491adb65bb34cb Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18870 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-08-28cpu: Make get(Data|Inst)Port return a Port and not a MasterPort.Gabe Black
No caller uses any of the MasterPort specific properties of these function's return values, so we can instead return a reference to the base Port class. This makes it possible for the data and inst ports to be of any port type, not just gem5 style MasterPorts. This makes life simpler for, for example, systemc based CPUs which might have TLM ports. It also makes it possible for any two CPUs which have compatible ports to be switched between, as long as the ports they use support being unbound. Unfortunately that does not include TLM or systemc ports which are bound permanently. Change-Id: I98fce5a16d2ef1af051238e929dd96d57a4ac838 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20240 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-08-28cpu, mem: Add new getSendFunctional method to the base CPU.Gabe Black
This returns a sendFunctional delegate references which can be used to send functional accesses directly, or more likely when constructing a PortProxy subclass. In those cases only the functional capabilities of those ports are needed so there's no reason to require a full port which supports all three protocols. Also, this removes the last remaining use of get(Data|Inst)Port which relies on those returning a port which supports the gem5 protocols, except the default implementations of this new function. If a CPU doesn't have traditional gem5 style ports, it can override this function to do whatever other behavior is necessary and return its real ports through get(Data|Inst)Port. Change-Id: Ide4da81e3bc679662cd85902ba6bd537cce54a53 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20237 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-08-28mem: Make PortProxy use a delegate for a sendFunctional function.Gabe Black
The only part of the MaserPort the PortProxy uses is the sendFunctional function which is part of the functional protocol. Rather than require a MasterPort which comes along with a lot of other mechanisms, this change slightly adjusts the PortProxy to only require that function through the use of a delegate. That allows lots of flexibility in how the actual packet gets sent and what sends it. In cases where code constructs a PortProxy and passes its constructor an unbound MasterPort, the PortProxy will create a delegate to the sendFunctional method on its own. This should also make it easier for objects which don't have traditional gem5 style ports, for instance systemc models, to implement just the little bit of the protocol they need, rather than having to stub out a whole port class, most of which will be ignored. Change-Id: I234b42ce050f12313b551a61736186ddf2c9e2c7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20229 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-28cpu: Move the instruction port into o3's fetch stage.Gabe Black
That's where it's used, and that avoids having to pass it around using the top level getInstPort accessor. Change-Id: I489a3f3239b3116292f3dcd78a3945fb468c6311 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20239 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-08-28cpu: Move O3's data port into the LSQ.Gabe Black
That's where it's used, and putting it there avoids having to pass around the port using the top level getDataPort function. Change-Id: I0dea25d0c5f4bb3f58a6574a8f2b2d242784caf2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20238 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-08-28mem: Eliminate the Base(Slave|Master)Port classes.Gabe Black
The Port class has assumed all the duties of the less generic Base*Port classes, making them unnecessary. Since they don't add anything but make the code more complex, this change eliminates them. Change-Id: Ibb9c56def04465f353362595c1f1c5ac5083e5e9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20236 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-08-27cpu, dev, mem: Use the new Port methods.Gabe Black
Use getPeer, takeOverFrom, and << to simplify the use of ports in some areas. Change-Id: Idfbda27411b5d6b742f5e4927894302ea6d6a53d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20235 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-08-27sim: Add a << overload for the Port class which prints its name.Gabe Black
This makes it easier/less verbose to print the name of a port, it's most important and identifying feature, in a DPRINTF or other stream based output. Change-Id: I050d102844612577f9a83d550e619736507a6781 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20234 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-08-27sim: Add a takeOverFrom method to the base Port class.Gabe Black
This makes it easier, safer, and less verbose to swap out ports when a CPU takes over for another CPU, for instance. Change-Id: Ice08e4dcb4b04dc66b1841331092a78b4f6f5a96 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20233 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
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