summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2019-05-29cpu: Added correct return type for ROB::countInstsAndrea Mondelli
- return size_t (unsigned) according to the .size() return type - fixed typo in doc (source of warning with some compilers) Change-Id: I48ee2e317cf41011a6fcb5ca45aef67e75329bfa Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18948 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-29mem-cache: Accuracy-based rate control for prefetchersJavier Bueno
Added a mechanism to control the number of prefetches generated based in the effectiveness of the prefetches generated so far. Change-Id: I33af82546f74a5b5ab372c28574b76dd9a1bd46a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18808 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-05-29sim-se: add a release parameter to Process.pyCiro Santilli
Set the default release to that single value for all ISAs. glibc has checks for the kernel version based on uname, and refuses to start any syscall emulation programs if those checks don't pass with error: FATAL: kernel too old The ideal solution to this problem is to actually implement all missing system calls for the required kernel version and bumping the release accordingly. However, it is very hard to implement all missing syscalls and verify compliance. Previously, we have simply bumped the version manually from time to time when major glibc versions started breaking. This commit alleviates the problem in two ways. Firstly, having a single kernel version for all versions means that it is easier to bump all versions at once. Secondly, it makes it is possible to set the release with a parameter, which in turn can be set from the command line with: se.py --param 'system.cpu[:].workload[:].release = "4.18.0"' Change-Id: I9e3c31073bfe68735f7b0775c8e299aa62b98222 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17849 Maintainer: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-29mem-cache: Support for page crossing prefetchesJavier Bueno
Prefetchers can now issue hardware prefetch requests that go beyond the boundaries of the system page. Page crossing references will need to look up the TLBs to be able to compute the physical address to be prefetched. Change-Id: Ib56374097e3b7dc87414139d210ea9272f96b06b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14620 Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-05-29mem: Add a readString method to the PortProxy which takes a char *.Gabe Black
This version takes a char * instead of an std::string &, and a maximum length to fill in like strncpy. This is intended to be a replacement for the CopyStringOut function. Change-Id: Ib661924a3fa7e05761d572ffecbe2c0cc8659d48 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18574 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-05-29mem: Use a const T & in write<> to avoid an unnecessary copy.Gabe Black
If the type T is complex/large, the it makes sense to access it in place and not copy it and then not modify it. Change-Id: Idd24be4fbba636375637ff72b1ba5ee32eb76215 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18573 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-05-29arch, base, dev, sim: Remove now unnecessary casts from PortProxy methods.Gabe Black
Change-Id: Ia73b2d86a10d02fa09c924a4571477bb5f200eb7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18572 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-29mem, arm: Replace the pointer type in PortProxy with void *.Gabe Black
The void * type is for pointers which point to an unknown type. We should use that when handling anonymous buffers in the PortProxy functions, instead of uint8_t * which points to bytes. Importantly, C/C++ doesn't require you to do any casting to turn an arbitrary pointer type into a void *. This will get rid of lots of tedious, verbose casting throughout the code base. Change-Id: Id1adecc283c866d8e24524efd64f37b079088bd9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18571 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-29mem, arm: Move some helper methods into the base PortProxy class.Gabe Black
These were originally in the SETranslatingPortProxy class, but they're not specific to SE mode in any way and are an unnecessary divergence between the SE and FS mode translating port proxies. Change-Id: I8cb77531cc287bd15b2386410ffa7b43cdfa67d0 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18570 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-29arm, mem: Move the SecurePortProxy subclass into it's own file.Gabe Black
The idea of a "secure" memory area/access is specific to ARM and shouldn't be in the common mem directory, although it's built in to the generic memory protocol at this point. Regardless, it should minimially be in its own file like the virtual and physical port proxy classes are. Change-Id: I140d4566ee2deded784adb04bcf6f11755a85c0c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18569 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-28mem: Parameterize coherent xbar sanity checksTiago Muck
Parameters can be used to change coherent xbar limits for the routing table and outstanding snoops. We need the ability to tweak these values as the current defaults may be violated in simulations with large core counts. Change-Id: Idb64b8c105683d02d8beba5bce13b815181ba824 Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18789 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-28mem: Snoop filter support for large systemsTiago Muck
Changed SnoopMask to use std::bitset instead of uint64 so we can simulate larger systems without having to workaround limitations on the number of ports. No noticeable performance drop was observed after this change. The size of the bitset is currently set to 256 which should fit most needs. Change-Id: I216882300500e2dcb789889756e73a1033271621 Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18791 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-28base: Add warn_if_once macroTiago Muck
Change-Id: Ie68f3b07a35ed2e6b0eee20b3b34050542fcdc6c Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18420 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-28cpu: Remove assert causing issues with x86 Linux bootGiacomo Gabrielli
Change-Id: I5e0b189ced0dd59ac6dbbb2c498c068e132b9b93 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18910 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-24arch-arm: Fix fallthrough when trapping at EL2Giacomo Travaglini
This had been caused by the introduction of GICv3 registers trapping in commit 32a23114c14cebc5ec0067ac739144b50e412219 Change-Id: I5073e2891f3ff5c5a9e05d3456dad6f4f8ffba0d Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18909 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-23arch-arm: Trap virtual accesses to GICv3 SGI registersGiacomo Travaglini
According to GICv3 documentation, a virtual write (which means HCR.IMO/FMO = 1) to ICC_SGI0R_EL1, ICC_SGI1R_EL1, ICC_ASGI1R_EL1 should trap to EL2. Change-Id: Ie7a952c2ff08590bb0c6e3854df567d714c2dc94 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17990 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-23arch-arm: Expose haveGicv3CPUInterface to the ISA interfaceGiacomo Travaglini
Change-Id: I36232b7618ad875983f34b741c51f12ddb9ae166 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17989 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-23arch-arm: Change mcrMrc15TrapToHyp signatureGiacomo Travaglini
This patch is moving MiscRegs reading inside the mcrMrc15TrapToHyp helper function. Rather than passing registers as arguments, we are just passing a ThreadContext pointer Change-Id: I6636dd3a4f92f757479d8a8d2c47de050a0b9eae Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17988 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-22mem: Add invalid context id check on LLSC checksTiago Muck
If the request's address is in the LLSC list, its context Id was being fetched unconditionally, which could cause the assert at Request::contextId() to fail. Change-Id: Iae9791f81c8fe9a7fcd842cd8ab7db18f34f2808 Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18792 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-22sim-se: remove comment for code that movedBrandon Potter
The page table code must have moved from this class, because the comment no longer accurately reflects upon any of the surrounding code. Change-Id: If08a4298c1237a541d9875ddeaf3d3ecfd98e9db Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12300 Maintainer: Brandon Potter <Brandon.Potter@amd.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-05-22dev-arm: Provide a GICv3 ITS ImplementationGiacomo Travaglini
This patch introduces the GICv3 ITS module, which is in charge of translating MSIs into physical (GICv3) and virtual (GICv4) LPIs. The patch is only GICv3 compliant, which means that there is no direct virtual LPI injection (this also means V* commands are unimplemented) Other missing features are: * No 2level ITS tables (only flat table supported) * Command errors: when there is an error in the ITS, it is IMPLEMENTATION DEFINED on how the ITS behaves. There are three possible scenarios (see GICv3 TRM) and this implementation only supports one of these (which is, aborting the command and jumping to the next one). Furter patches could make it possible to select different reactions * Invalidation commands (INV, INVALL) are only doing the memory table walks, assuming the current Gicv3Redistributor is not caching any configuration table entry. Change-Id: If4ae9267ac1de7b20a04986a2af3ca3109743211 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18601 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-21sim-se: change syscall function signatureBrandon Potter
The system calls had four parameters. One of the parameters is ThreadContext and another is Process. The ThreadContext holds the value of the current process so the Process parameter is redundant since the system call functions already have indirect access. With the old API, it is possible to call into the functions with the wrong supplied Process which could end up being a confusing error. This patch removes the redundancy by forcing access through the ThreadContext field within each system call. Change-Id: Ib43d3f65824f6d425260dfd9f67de1892b6e8b7c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12299 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-21sim-se: remove /sys from special pathsTony Gutierrez
Currently, the open system call implementation in SE mode treats /sys/ as a special path that is opened using a special open handler. The ROC runtime, however, reads several files in /sys/ that are supported via path redirection. Here we remove /sys/ from the special files so that the necessary files may be read via path redirection. Change-Id: Ifdab38ea1e6cc486ad43aec96b6e032fe63f137d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12127 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-21scons: Move the marshal binary to the build directoryChun-Chen TK Hsu
The current marshal binary is in $BUILD/python/ directory which makes the dynamic linker fail to find shared libraries with rpath information when the marshal is executing. Moving $BUILD/python/marshal to $BUILD/marshal solves this problem. This is because the marshal binary is built with the same flags as gem5 binary. And if one adds rpath information with add_local_rpath() in some SConscripts, the marshal binary will also link to those shared libraries and have the same rpath information. So it must be in the same directory as gem5 binary such that the dynamic linker could find those shared libraries with the rpath information. Signed-off-by: Chun-Chen TK Hsu Change-Id: I98d9c3e0180abefe6b2b6a78ee5a96324038eb53 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18888 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-20misc: Added dot_writer for Ruby's network topologyTiago Muck
Change-Id: Ic71ca7bc2eb4174d70afa368bc9cc987f3df89e9 Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17548 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-20mem-cache: Add multi-prefetcher adaptorAndreas Sandberg
This patch adds a meta-prefetcher that enables gem5's cache models to connect to multiple prefetchers. Sub-prefetchers still use the probes-based interface and training can be controlled independently. However, when the cache requests a prefetch packet, the adaptor traverses the priority list of prefetchers and uses the first prefetcher that is able to generate a prefetch. Kudos to Mitch Hayenga for the original version of this patch. Change-Id: I25569a834997e5404c7183ec995d212912c5dcdf Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18868 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-20sim: Make the Process create function use the object loader mechanism.Gabe Black
This gets rid of the big mass of #if-s around headers and around the code which creates an object file. As a nice side bonus, this also means that in addition to supporting multiple OS/arch combinations simultaneously, the object file loader could support multiple ISAs simultaneously as well, since each could load and set up its object file loaders indepedently and without the base process classes knowledge/involvement. Change-Id: I0a19ad06e30e9062a96d27f00b66756eb3a595ba Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18631 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-05-20x86: Add an object file loader for linux.Gabe Black
Change-Id: I283dd1f52fd020ad3c226eb00fc9216ee034c67f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18630 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-20sparc: Add an object file loader for linux and solaris.Gabe Black
Change-Id: I76bcbc06714f7d538f03a8311994a868de3640f1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18629 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-20riscv: Add an object file loader for linux.Gabe Black
Change-Id: I3accca91cc4e02fa8e3a1169590cbe6696cf05e2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18628 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com>
2019-05-20power: Add an object file loader for linux.Gabe Black
Change-Id: I64ce81e98a6dc96754554d0fdcd7d16b8a2752d4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18587 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Sandipan Das <sandipan@linux.ibm.com>
2019-05-20mips: Add an object file loader for linux.Gabe Black
Change-Id: Icae6430a210076117cf2ceadce52d6efbe58a5f3 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18586 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-18arm: Add an object file loader for linux and freebsd.Gabe Black
Change-Id: Ie5fd187a4897aa608ffc12278b23d3ee8c0f323c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18585 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-05-18alpha: Add an object file loader for linux.Gabe Black
Change-Id: I91c4019567bdf74b2517fda597121a6ad107cb86 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18584 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-18base: Add a type for keeping track of object file loaders.Gabe Black
This avoids having a big pile of #if-s in sim/process.cc and allows dynamically adding new types of object file loaders which might recognize new arch/OS combinations. Change-Id: Ie3b9c1aa2974d30a61afc4fcc529ffd6a74d43e0 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18583 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-18arch, base, cpu, dev, mem, sim: Remove #if 0-ed out code.Gabe Black
This code will be preserved through version control, but otherwise creates clutter and will rot in place since it's never compiled. Change-Id: Id265f6deac445116843956ea5cf1210d8127274e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18608 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-17configs: Generalize FileSystemConfig for non se.pyJason Lowe-Power
This patch updates the FileSystemConfig so it works with more kinds of config scripts (e.g., the Learning gem5 scripts). There are 4 main changes: - Added system as a parameter to the config_filesystem function so the function can search the system for the number of CPUs instead of relying on options from Options.py - Instead of calling redirect_paths everywhere config_filesystem is used, now it is implicitly called. - Cleaned up the Ruby scripts a bit to remove redundant calls to config_filesystem - Added a config_filesystem call to the Ruby Learning gem5 script (currently the only Learning gem5 script that requires it). In the future, I think it would be better to move the config_filesystem call into simulate.py, probably into the instantiate function. I tried to use the per-CPU configuration parameters instead of options from Options.py, but that's not possible until after the SimObject params have been finalized in instantiate. Change-Id: Ie6501a7435cfb3ac9d2b45be3722388b34063b1e Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18848 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-17arch-arm: implement VMINNM and VMAXNM scalar versionCiro Santilli
ARMv8.2 16-bit versions have not yet been implemented, but a placeholders were created for them. Refactor the nearby decoding tree to closely match the ARM spec A32 decode table. That piece of the tree can also be called from thumb which decodes it in the same way, although the thumb decode table has a different terminology The old code didn't match neither A32 or T32 terminologies, so it is better to at least match one of them to help verify correctness. Change-Id: Iabbbca2932557cf6c98ce36690c385c3ddf39ed8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18690 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-17arch-arm: implement VMINNM and VMAXNM SIMD versionCiro Santilli
This instruction is backported from aarch64. In order to use the existing fplibMinNum backend, we first move VMIN and VPMIN to use fplib. Adding VMINNM is then trivial. Change-Id: I404daabeb6079f60e51a648a06d5b3e54f1c24a9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18689 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-17arch-arm: rename operands to match spec in isa/formats/fp.isaCiro Santilli
Matches ARM DDI 0487D.a decoding tables. Change-Id: I48338ef956a04308d55d1022229ebe0962a8fe5d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18688 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-14mem-ruby: MOESI_CMP_dir cleanupTiago Muck
Removed unused states and actions Change-Id: I3dc684c78d4b92d219e71522ddb706a13f9874d1 Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18415 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: John Alsop <johnathan.alsop@amd.com> Reviewed-by: Matthew Poremba <matthew.poremba@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-14mem-ruby: Cache latencies for MOESI_CMP_dirTiago Muck
Modified both L1 and L2 controllers to take into account the cache latency parameters. Default values in the configuration script updated as well. Change-Id: I72bb8dd29ee0b02da06e1addf13b266fe4d1e979 Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18414 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-14mem-ruby: Hit latencies defined by the controllersTiago Muck
Removed the icache/dcache hit latency parameters from the Sequencer. They were replaced by the mandatory queue enqueue latency that is now defined by the top-level cache controller. By default, the latency is defined by the mandatory_queue_latency parameter. When the latency depends on specific protocol states or on the request type, the protocol may override the mandatoryQueueLatency function. Change-Id: I72e57a7ea49501ef81dc7f591bef14134274647c Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18413 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-14mem-ruby: Do not change blocked msg enqueue infoTiago Muck
Updating the message counter and enqueue times when adding blocked messages back to the queue does not make a lot of sense since these messages are not new arrivals. More importantly, this may lead to starvation. See the scenario below: 1) Request A for a blocked line X arrives 2) A is handled; X is blocked so A is stalled 3) Request B for X arrives; Reponse for X arrives 4) Response is handled; X unblocked; A added back to the request queue 5) B is handled ahead of A (since A's arrival was updated); X may become blocked again If new requests keep comming for X, A may will be stalled forever. Change-Id: Icad79f3f716a870e91cb3455437b8b3c35f130ac Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18412 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Matthew Poremba <matthew.poremba@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-14mem-ruby: Unique ranks for MOESI_CMP_dir in portsTiago Muck
Setting different values for the rank parameter for all inputs ports. If left unset, it defaults to 0. This may cause issues since the rank is used as an index in the controller's list of stalled buffers. Change-Id: Ie8ff660b7450df959292311040aebf802657efcf Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18411 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-14mem-ruby: Change MOESI_CMP_Dir L2 addressingTiago Muck
L1 controller selects the L2 to message based on the assigned address ranges instead of explicitly interleaving bits in the L1 controller. This simplifies the L1 controller implementation a bit and allows for more flexibility when changing the address->controller mapping. Change-Id: Ie67999bb977566939432a5045f65dbd2da81816a Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18410 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-14mem-ruby: Fix MOESI_CMP_dir debug msgTiago Muck
Change-Id: I3fd32bd2e81dbf9a8ea49a43727564b8a9d64767 Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18409 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-14mem-ruby: Prevent response stalls on MOESI_CMP_directoryTiago Muck
When a message triggers a transition that has actions which allocate TBEs, the generated code automatically includes a check for the TBETable size before executing any action. If the table is full, the transition returns TransitionResult_ResourceStall and no more messages from the buffer are handled (until the next cycle). This behavior may lead to deadlocks in the MOESI_CMP_directory protocol since events triggered by the response queue may allocate TBEs (e.g. L2 replacements triggered by the response queue). If the table is full, the queue is stalled preventing other responses from freeing TBEs. This patch fixes this by handling WRITEBACK_DIRTY_DATA/CLEAN_DATA messages as requests and WB_ACK/WB_NACK as responses. All controllers are changed to work with the new types. With this fix, responses are always handled first in all controllers, and no response triggers TBE allocations. Change-Id: I377c0ec4f06d528e9f0541daf3dcc621184f2524 Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18408 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Matthew Poremba <matthew.poremba@amd.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: John Alsop <johnathan.alsop@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-14arch-arm: Do not check MustBeOne flag for TLB requests from the prefetcherJavier Bueno
Allow TLB requests generated from prefetchers to override the MustBeOne arch flag. This allows the prefetchers to issue requests without having to know architecutre-specific flags. Change-Id: Id83e0c93f3d1a614da11c4f344ab4dc594423672 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18768 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-14configs: Fix duplicate branchPred reference in Simulation.pyJavier Bueno
Change-Id: I5ef5fb7ebc5fc2a4776adc43643c4df27efc341c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18769 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 21:38:05 +0000