summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2019-10-02fastmodel: Implement a custom sendFunctional for CortexA76x1.Gabe Black
Change-Id: I28094620106a8edd90e1144b4fb87ae5729ebf32 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21047 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-10-02x86: Switch from MessageReq and Resp to WriteReq and Resp.Gabe Black
Originally MessageReq was intended to mark a packet as a holding a message destined for a particular recipient and which would not interact with other packets. This is similar to the way a WriteReq would behave if writing to a device register which needs to be updated atomically. Also, while the memory system *could* recognize a MessageReq and know that it didn't need to interact with other packets, that was never implemented. Change-Id: Ie54301d1d8820e206d6bae96e200ae8c71d2d784 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20823 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-10-02fastmodel: Let the EVS set an attribute for getSendFunctional to return.Gabe Black
The iris CPU model doesn't necessarily know the best way to send functional packets (what port? what type is that port?), but only has a generic sc_module pointer to the EVS and so can't call specialized methods on it. There also isn't any common base class for EVSes to cast into in a generic way. This attribute mechanism lets the EVS set up its own sendFunctional implementation however it needs to using facilities that are built into generic sc_objects. Change-Id: I69bf364908c2a5360bd6ce7d3e49ce67c6f771b0 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21046 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-10-01style: normalize filename in SortedIncludes.fix()Georg Kotheimer
The filename affects the sorting result. Therefore check(), which normalizes the filename, detects an invalid sorting of includes, but fix() fails to fix the corresponding includes. Change-Id: I7d5a941c9ebea853004922d19e3b84f8ded2afa6 Signed-off-by: Georg Kotheimer <georg.kotheimer@mailbox.tu-dresden.de> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/10742 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-10-01fastmodel: Add a gem5Cpu attribute to the CortexA76x1.Gabe Black
This attribute is to let the fast model EVS CPU find and talk to the gem5 CPU in case it needs a pointer to one of its ThreadContexts for instance. Also move the code that finds the clock period attribute/event to the constructor. gem5 guarantees that the EVS is constructed before its pointer is passed to the iris CPU wrapper, and so the EVS will have had a chance to install those controls if it's going to. Change-Id: I389ef0ba0f9d528140f40444baa5091a9ec338cd Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21045 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-01fastmodel: Add a utility class which makes it easier to watch signals.Gabe Black
These signals come from the exported virtual subsystem and could signal interrupts, etc. The new SignalReceiver class makes it easier to watch those signals and perform some behavior when they change without having to bring along a lot of systemc baggage. Change-Id: I09651de1dd0e7340a61779aaf080c695ce299fd4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21043 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-01fastmodel: Pull out and simplify the interrupt mechanism in the GIC.Gabe Black
This change pulls out the SPI and PPI command structures and replaces them with a custom protocol which can deliver a SPI or PPI without having to bundle their parameters into a structure. Change-Id: I8f15c8b3182bd6560bf5ef0345b0bc64173def85 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21042 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-01mem-cache: Fix invalid whenReadyDaniel R. Carvalho
When a writeback needs to be allocated the whenReady field of the block is not set, and therefore its access latency calculation uses the previously invalidated value (MaxTick), significantly delaying execution. This is fixed by assuming that the data write portion of a write access is done regardless of previous writes, and that only the tag latency is important for the critical path latency calculation. Change-Id: I739132a2deab6eb4c46d084f4ee6dd65177873fd Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20068 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-10-01configs: Port PlatformConfig to the common object listDaniel R. Carvalho
Port PlatformConfig to use the common object list. Change-Id: If62e596bf1f28b49994da3a2800450d163383755 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20593 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-10-01configs: Port MemConfig to the common object listDaniel R. Carvalho
Port MemConfig to use the common object list. Change-Id: If421c2745ac3431718a5170314045b456fc64a90 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20592 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2019-10-01configs: Port HWPConfig to the common object listDaniel R. Carvalho
Port HWPConfig to use the common object list. Change-Id: I86db6b872808f754193dbf5814dd6c951c8f1980 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20591 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-10-01configs: Port BPConfig to use the common object listDaniel R. Carvalho
Port BPConfig to use the common object list. Change-Id: I5cbd1c67cf743778bc59b5aa3c3dea5ab397b66d Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20590 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-30configs: Port CPUConfig to use the common object listDaniel R. Carvalho
Factor out ObjectList functionality from CPUConfig. Change-Id: I34ca55142e14559e584d38b6cca3aa5c20923521 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20589 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-30configs: Create a basic ObjectListDaniel R. Carvalho
There are multiple files that reimplement the same functionality of listing and getting available modules for class instantiation. Create a base class that can be derived and reduce code duplication. Change-Id: I96bf47b1ffd10893691b0b95591969b38894dd65 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20588 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-30configs: Remove is_atomic_cpu checkDaniel R. Carvalho
Commit 224f2d50a9873d054f486d7661d947db76f4cf68 removed all instances of is_atomic_cpu. Change-Id: I1101fbdbc16dc5d093ab87d3817308176559a548 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20659 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-09-30mem-ruby: Remove inexistent functions from UtilDaniel R. Carvalho
Remove forward declaration of inexistent functions from RubySlicc_Util.sm. Change-Id: I548bd75cb570371fbdaccf914c5eb9a7b92313d1 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21086 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-30mem-ruby: Make bitSelect use bits<Addr>Daniel R. Carvalho
There is no need to replicate bits<Addr>' functionality. As a side effect, ADDRESS_WIDTH is no longer used and was removed Change-Id: Ia5679f3976c81f779665d82cb758850092f2a293 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21085 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-30mem-ruby: Fix maskLowOrderBitsDaniel R. Carvalho
The function was wrong when number = 63. Also, use the more reliable src/base/bitfield.hh's mbits when posible. maskLowOrderBits has only been kept because SLICC does not accept a templated function. Change-Id: I8dd680da02ceb9e614e2f9cbf8f1ac52cead8d45 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21084 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-30mem-ruby: Remove shiftLowOrderBitsDaniel R. Carvalho
There is no need to encapsulate a shift operation. Change-Id: Ie711d8d4975d1d9dde656cc2284a048410cfdadb Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21083 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-30mem-ruby: Remove maskHighOrderBitsDaniel R. Carvalho
Function was not being used. If needed, src/base/bitfield.hh's mbits can be used instead: maskHighOrderBits(addr, pos) == mbits<Addr>(addr, 64-pos, 0) Change-Id: I3abd041f8d256ec157ba7502182d8588721c2a05 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21082 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-30mem-ruby: Remove bitRemoveDaniel R. Carvalho
bitRemove is not being used anywhere. If needed, can be used as src/base/bitfield.hh's bits: bitRemove(addr, small, big) == ((bits<Addr>(addr, 63, big + 1) << small) | bits<Addr>(addr, small, 0)) Change-Id: I45fd3bc0271ccb659d6a94e3dd00ca095dfd6aa7 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21081 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-30cpu: Make use of DRAMCtrl::AddrMap in the traffic generatorsNikos Nikoleris
Use the enum defined in the memory controller rather than custom strings and int that are later converted to the DRAMCtrl::AddrMap enum. Change-Id: Ie5b19f915f9990fd2b7505d4d1b17b6fc2100f9e Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21080 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-30misc: Added line wrapping functionality for Sim-Object descBobby R. Bruce
Descriptions were previously printed on one line, unless explicitly broken when writing the description of the Sim-Object. In this commit, line wrapping is enabled when printing these descriptions. Developers, when writing the Sim-Object descriptions, may now over multiple lines with triple double-quotes and still have the description output correctly when viewing the Sim-Objects within the CLI. E.g.: X86System previously had the following load_addr_mask component which was output as: load_addr_mask default: 18446744073709551615 desc: Address to mask loading binaries with, if 0, system \ auto-calculates the mask to be the most restrictive, otherwise it obeys a \ custom mask. This was defined by the developer via: load_addr_mask = Param.UInt64(0xffffffffffffffff, "Address to mask loading binaries with, if 0, system " "auto-calculates the mask to be the most restrictive, " "otherwise it obeys a custom mask.") This is now displayed as: load_addr_mask default: 18446744073709551615 desc: Address to mask loading binaries with, if 0, system auto-calculates the mask to be the most restrictive, otherwise it obeys a custom mask. JiraID: Gem5-57 Built: Linux (GCC) Tested: Ran quick tests for X86, ARM, and RISC-V Change-Id: If012304e50af60f6ba10c1fa2b44da8bac1c09cf Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21179 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-30mem: Use new-style stats in the XBar modelsAndreas Sandberg
Migrate to new-world stats with an explicit hierarchy in all of the XBar models. Change-Id: I18b6746a1303ca415638e6d382fb4757607f1123 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21141 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-09-30mem-cache: Switch to new-style statsAndreas Sandberg
This change puts cache and tag stats into a Stats::Group struct. This makes it easier to identify stat updates (they are prefixed with stat.) and adds hierarchy information for output formats that need it. Change-Id: I2b8e9138f1cb977abb445ec864d80a79b588481d Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21140 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-30mem: Convert DRAM controller to new-style statsAndreas Sandberg
Note that this changes the stat format used by the DRAM controller. Previously, it would have a structure looking a bit like this: - system - dram: Main DRAM controller - dram_0: Rank 0 - dram_1: Rank 1 This structure can't be replicated with new-world stats since stats are confined to the SimObject name space. This means that the new structure looks like this: - system - dram: Main DRAM controller - rank0: Rank 0 - rank1: Rank 1 Change-Id: I7435cfaf137c94b0c18de619d816362dd0da8125 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21142 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com>
2019-09-28ruby: 2x protocols has typo/syntax error that fails buildingTimothy Hayes
MOESI_hammer and MOESI_CMP_token contain incorrect lines. Change-Id: I1f9ac429d0f4dcb0241f21c8c9b831bee7aa37a4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21259 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-27fastmodel: Add glue code which adapts fastmodels to run in gem5.Gabe Black
Fast Models are models written by ARM which emulate different components of a computer system. They can be combined into small subsystems and then exported as systemc modules. To enable this code, you'll need to set USE_ARM_FASTMODEL variable to true. This CL does not include the fast models themselves, or a license to use them or the associated tools. To build these fast models, you'll need to set some scons variables. These variables should be set as described in the fast model distribution. * PVLIB_HOME * MAXCORE_HOME * ARMLMD_LICENSE_FILE Some minor patches to source filesdistributed with the fast model code may be necessary since their use of systemc is not necessarily 100% standards compliant. Change-Id: Id53814b95d8aa320da4d4f2159be0736fc12eb73 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20799 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-26sim: Convert power modelling framework to new-style statsAndreas Sandberg
Change-Id: I1dd3ea3d37bb4464637222aa5bc5d88cc7d9b66a Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21143 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2019-09-26stats: Add a preDumpStats() callback to Stats::GroupAndreas Sandberg
Some objects need to know that we are about to dump stats to perform prepare statistics. This is currently done by registering a callback with the stat system. Expose this callback as a virtual method in Stats::Group to make this pattern more convenient. Change-Id: I5aa475b7d04c288e45f5f413ab7a1907b971dae5 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21139 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2019-09-26stats: Don't output index in vectors of length 1Andreas Sandberg
New-world stats didn't implement the old gem5 quirk where the index of an element in a vector of size 1 is ignored. This affects the object path when printed in a stat file. Implement the same quirk as the original code to make sure names of old- and new-world stats are compatible. Change-Id: I12696d40baaed2d0bb1ef061e87c3b1d0f4bb4b1 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21163 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2019-09-26stats: Correctly print new-style dist stat namesAndreas Sandberg
The text stat printer didn't output fully qualified names for new-style dist stats. Fix that. Change-Id: I61bc7403fbd760bbbb0641e8e593781e6d03a4ed Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21162 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2019-09-25mem-ruby: prevent cacheProbe being called multiple timesJing Qu
The cacheProbe() function will return the victim entry, and it gets called for multiple times in trigger function in a single miss. This will cause a problem when we try to add a new replacement policy to the Ruby system. Certain policy, like RRIP, will modify the block information every time the getVictim() function gets called. To prevent future problems, we need to store the victim entry, so that we only call it once in one miss. Change-Id: Ic5ca05f789d9bbfb963b8e993ef707020f243702 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21099 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-24ext: Updated Pybind11 to version 2.4.1.Bobby R. Bruce
This updates Pybind11 from version 2.2.1 to version 2.4.1. This fixes warning/error received when "<experiment/optional>" is used when compiling using c++14 with clang. It should be noted that "ext/pybind11/include/pybind11/std.h" has been changed to include a fix added by commit ba42457254cc362eddc099f22b60d469cc6369e0. This is necessary to avoid build errors. Built: Linux (gcc, c++11) and MacOS (clang, c++14). Tested: Ran quick tests for X86, ARM, and RISC-V. Deprecates: https://gem5-review.googlesource.com/c/public/gem5/+/21019 Change-Id: Ie9783511cb6be50136076a55330e645f4f36d075 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21119 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-24cpu: Fix checker cpu instantiationNikos Nikoleris
This change uses the params as instantiated from the default constructor to create the checker cpu. If any of these parameters are invalid for the checker cpu, the simulation will exit with a warning. Change-Id: I0e58ed096c9ea5f413f2e9b64d8d184d9b0fc84e Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21079 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-23cpu, mem: Changing AtomicOpFunctor* for unique_ptr<AtomicOpFunctor>Jordi Vaquero
This change is based on modify the way we move the AtomicOpFunctor* through gem5 in order to mantain proper ownership of the object and ensuring its destruction when it is no longer used. Doing that we fix at the same time a memory leak in Request.hh where we were assigning a new AtomicOpFunctor* without destroying the previous one. This change creates a new type AtomicOpFunctor_ptr as a std::unique_ptr<AtomicOpFunctor> and move its ownership as needed. Except for its only usage when AtomicOpFunc() is called. Change-Id: Ic516f9d8217cb1ae1f0a19500e5da0336da9fd4f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20919 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-21mem: Delete the now unused Message*Port classes.Gabe Black
This port type is no longer used. Change-Id: If4abbb774819644bea58fd82e00dfdec8f79b5a6 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20822 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-09-21x86: Templatize the IntMasterPort.Gabe Black
This makes the IntMasterPort usable with any class, making it possible to avoid inheriting from IntDevice. It also makes IntMasterPort inherit directly from QueuedMasterPort, skipping over MessageMasterPort. Change-Id: I9d218556c838ea567ced5f6fa4d57a3ec9d28d31 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20821 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-09-21x86: Templatize IntSlavePort.Gabe Black
This makes the device IntSlavePort calls back into based on a template parameter so that IntDevice doesn't have to be in the inheritance hierarchy to use it. It also makes IntSlavePort inherit from SimpleTimingPort directly, skipping over MessageSlavePort. Change-Id: Ic3213edc9c3ed5e506ee1e9f5e082cd47d7c7998 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20820 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-09-21x86: Turn the local APIC into a PioDevice instead of a BasicPioDevice.Gabe Black
This will let us accept several address ranges through our pio port instead of just one, and that will in turn let us accept interrupt requests and pio requests through the same port. Change-Id: I70b78c8cd0edca7fe58b3d4cd241e41d9e0f2c20 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20819 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-20gpu-compute: Fix overriden errorsJing Qu
When building Gem5 with GPU protocols, overriden errors were thrown from files in gpu-compute. After adding override to the files, the errors were resolved and Gem5 builds successfully. Change-Id: Iab3a0768caf82c226e8bbee5690a834bf92d1e03 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20939 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-20dev, x86: Delete the now unused X86 specific interrupt pins/lines.Gabe Black
Change-Id: I3915f0ad673119b551dcc4c5cedec180a9b88735 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20702 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-20dev, x86: Convert x86 devices to the generic int pins.Gabe Black
Change-Id: I4551ad00cf205c31555c90b53e87bc206a8d8729 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20701 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-20arch-x86: ignore non-temporal hint for movntps/movntpd SSE instsPouya Fotouhi
Making the implementation of movntps/movntpd consistent with other non-temporal instructions. We are ignoring the hint here, and implementing those instructions as cacheable instructions. This change adds a warning to let user know about this workaround. Also, this change add the address check for second part of move. Change-Id: I811652b24cf39ca2f5c5d4c9e9e417f69190b55c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20408 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-19dev: Terminal output's dump name conflictsAndrea Mondelli
The recently Terminal dump options name introduced in patch 1c72e90 conflict with MacOS stdio.h header. From stdio.h: #define stdin __stdinp #define stdout __stdoutp #define stderr __stderrp To remove this conflict, the TerminalDump options are renamed. Change-Id: I1b60fa1031328fc32d6a58bf7889b6e479d95219 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20959 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-19arch-x86: Change warn to warn_once for NT instructionsHoa Nguyen
Change-Id: I50353716f2a913b9b106b140644d95991879f662 Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21039 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-19python: Don't try to bind a stat group to the NULL simobject.Gabe Black
That is a SimObject like object which is used when a SimObject parameter is purposefully left empty, vs. being accidentally left empty through a typo or accidental ommission. It doesn't have a getCCObject method, and attempting to use it anyway causes gem5 to crash. Change-Id: Ie86321fbdbcc41cf88b7009184423acd7b64484b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21059 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-19misc: Update MAINTAINERSJason Lowe-Power
Change-Id: I13ca12d4dd170ce3db03d851829df9bc62d1a74c Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20999 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-19dev-arm: Conditionally enable HDLcd when doing DTB autogenGiacomo Travaglini
This is a preparation change for a real DTB autogen implementation Change-Id: Ia0c1c5e65ea96036e55455eb4222cec12944d33a Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20331 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-19dev-arm: Add HDLcd DTB autogenerationGiacomo Travaglini
A Display has been defined. Its sole purpose is to generate the device tree node to be referenced by the HDLcd device. The encoder parameters are based on the existing node defined in: system/arm/dt/armv8.dts Change-Id: I6cdeb0437dce207dbd0f2c65c16b224245eb74e1 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20330 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-06 20:41:45 +0000