gem5 - gem5

Age	Commit message (Expand)	Author
2019-04-30	arch: cpu: Track kernel stats using the base ISA agnostic type.	Gabe Black
2019-04-30	alpha: Implement HWREI in the ISA.	Gabe Black
2019-04-30	alpha: Add some control registers to the ISA operands list.	Gabe Black
2019-04-30	sim-se: add socket ioctls	Brandon Potter
2019-04-30	systemc: Add a distinct async_request_update mechanism.	Gabe Black
2019-04-29	cpu: Get rid of the (read\|set)RegOtherThread methods.	Gabe Black
2019-04-29	mips: Implement readRegOtherThread and setRegOtherThread directly.	Gabe Black
2019-04-29	cpu: Include debug flags regardless of whether the ISA is null.	Gabe Black
2019-04-29	sim-se: create Proc out files in out dir	Steve Reinhardt
2019-04-29	arch-arm: Faults DebugFlag now printing inst opcode if available	Giacomo Travaglini
2019-04-29	arch-arm: Report real instruction encoding when Undefined	Giacomo Travaglini
2019-04-28	arch, sim: Simplify the AuxVector type.	Gabe Black
2019-04-28	mem: Remove the ISA specialized versions of port proxy's read/write.	Gabe Black
2019-04-28	mem: Minimize the use of MemObject.	Gabe Black
2019-04-27	python: Get rid of the VectorPort constructor.	Gabe Black
2019-04-27	python: Replace the Master/Slave Ports with Request/Response ports.	Gabe Black
2019-04-26	arch-arm: updateMiscReg not setting isHyp in aarch64	Giacomo Travaglini
2019-04-26	arm: Factor some repetition out of the ProcessInfo constructor.	Gabe Black
2019-04-25	arm: Fix some style issues in stacktrace.cc.	Gabe Black
2019-04-25	x86: Refactor the ProcessInfo constructor.	Gabe Black
2019-04-25	configs: faux-filesystem fix w/ ruby in se mode	David Hashe
2019-04-25	x86: Fix some style issues in stacktrace.cc.	Gabe Black
2019-04-25	sim-se: add a faux-filesystem	David Hashe
2019-04-25	arch-arm: Remove un-needed hyp flag in TLBI operations	Giacomo Travaglini
2019-04-25	arch-arm: Correct target EL field in TLBI operations	Giacomo Travaglini
2019-04-25	dev-arm: Move GICv3 (Re)Ditributor address in Realview.py	Giacomo Travaglini
2019-04-25	dev-arm: Limit number of max PE in GICv3 to 128	Giacomo Travaglini
2019-04-25	dev-arm: Add GICv4 extension switch in GICv3	Giacomo Travaglini
2019-04-25	dev-arm: Check for maximum number of supported PE in GICv3	Giacomo Travaglini
2019-04-24	config: Add flag options to set the hardware prefetchers to use	Javier Bueno
2019-04-24	cpu,mem: missing override specifier	Andrea Mondelli
2019-04-24	systemc: Use the new TLM socket types in the TLM bridge SimObjects.	Gabe Black
2019-04-24	systemc: Add Port types for initiator and target sockets.	Gabe Black
2019-04-24	dev: Use the new Port role mechanism to make an EtherInt Port type.	Gabe Black
2019-04-24	python: Generalize the Port.splice function.	Gabe Black
2019-04-24	python: Generalize the dot_writer to handle non Master/Slave roles.	Gabe Black
2019-04-24	python: Make Port roles a more generic concept.	Gabe Black
2019-04-23	python: fix tracing after Python 3 refactor	Ciro Santilli
2019-04-22	sim-se: Enhance clone for X86KvmCPU	Alexandru Dutu
2019-04-22	mem-cache: Fix fix of replacement count	Daniel
2019-04-22	cpu: Eliminate the ProxyThreadContext class.	Gabe Black
2019-04-22	configs: Use param to get number of processors	Po-Hao Su
2019-04-19	mem-cache: Fix increasing replacement count	Daniel R. Carvalho
2019-04-19	mem-cache: Remove blk_addr from Queue::trySatisfyFunctional	Daniel R. Carvalho
2019-04-19	mem-cache: Add match functions to QueueEntry	Daniel R. Carvalho
2019-04-19	mem: Add packet matching functions	Daniel R. Carvalho
2019-04-19	mem-cache: Move Target to QueueEntry	Daniel R. Carvalho
2019-04-19	mem-cache: Assert Entry inherits from QueueEntry in Queue	Daniel R. Carvalho
2019-04-19	mem: Make DRAMCtrl::decodeAddr const	Daniel R. Carvalho
2019-04-19	mem: Allow packet to provide its own addr range	Daniel R. Carvalho