Age | Commit message (Collapse) | Author |
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Change Mem template parameter to MemType while we're at it.
dev/io_device.hh:
Change Bus template parameter to BusType (to avoid confusion with Bus class).
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SConscript:
Add zlib to the build always
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base/socket.cc:
Make panic print a more worthwhile message
dev/tsunami.hh:
Change max number of tsunami cpus to be 64
dev/tsunamireg.h:
Add new registers and register blocks for 64 cpu tsunami
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the SYSTEM_DETAIL configuration assumes that it's a TWO_SYSTEM. make it not do that
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now that we've changed the memory system defined names, fix this file
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Fix the Boot Detailed case so that IntrControl and AlphaConsole's cpu's are defined.
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Uncacheables don't change the request cmd, so use req->cmd instead of mshr->originalCmd]
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into zizzer.eecs.umich.edu:/z/stever/bk/m5
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Update profile-top to print 2 or 4 graphs depending on a command line
option
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/pcidev.hh:
Print a warning if two devices are sharing the same interrupt
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All that needs to be done is comment out the stuff you don't care
about in the header files in the mem/config.
For now, the default is to leave everything on.
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into zizzer.eecs.umich.edu:/.automount/ziff/z/binkertn/research/m5/latest
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in some places). use the constructor for setting the size.
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ipkb stat and formulas from the command line.
util/stats/info.py:
no need to raise an attribute error if two values aren't found
in the exact same set of runs. Would be good to check that each
run is the same though.
util/stats/stats.py:
more graph tweaking
command to execute a formula from the command line.
add interrupts per kilobyte of data
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//Still need to add similar stats to the cache
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characterization, and dropped packets.
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base/loader/ecoff_object.cc:
Only warn (not die) if we can't load symbols from an ecoff object.
sim/debug.cc:
Compile in functioning debug_break unless NDEBUG,
not only if DEBUG. Print warning if we hit breakpoint
when compiled with NDEBUG.
sim/debug.hh:
Compile in functioning debug_break unless NDEBUG,
not only if DEBUG.
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interrupt line.
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into ziff.eecs.umich.edu:/z/binkertn/research/m5/latest
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into zizzer.eecs.umich.edu:/.automount/ziff/z/binkertn/research/m5/latest
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/clean
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Changed SimpleCPU to not due functional access until the cache returns
Updated config file to use a simple cpu for second cpu in dual mode.
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
Update cache completion event to perform the functional read upon completion
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into ziff.eecs.umich.edu:/z/binkertn/research/m5/latest
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into ziff.eecs.umich.edu:/z/binkertn/research/m5/latest
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