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2019-08-05arch-arm: Rewrite MSR immediate instruction classGiacomo Travaglini
MSR <pstatefield>, #imm is used for setting a PSTATE field using an immediate. Current implementation has the following flaws: * There is no base MSR immediate definition: all the existing PSTATE fields have a different class definition * Those implementation make use of a generic data64 base class which results in a wrong disassembly (pstate register is printed as an integer register). This patch is fixing this by defining a new base class (MiscRegImmOp64) and new related templates. In this way, we aim to ease addition of new PSTATE fields (in ARMv8.x) Change-Id: I71b630ff32abe1b105bbb3ab5781c6589b67d419 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19728 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-05systemc: Provide Port wrapper classes for sc_portChun-Chen TK Hsu
Add Port wrappers for sc_port, sc_interface, and sc_export. Change-Id: Ib70cb7466461c8d32e3a260bf2a2d60a6ded87c3 Signed-off-by: Chun-Chen TK Hsu <chunchenhsu@google.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19788 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-02mem-ruby: Remove assertion with incorrect assumptionPouya Fotouhi
Current code assumes that only one cacheline would either be in RW. This is not true for GPU protocols, and may not be true for some CPU-only protocols with state violations. Change-Id: I70db4fbb4e80663551e8635307bb937a4db8dc63 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19708 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-02sim-se: small refactor on pipe syscallBrandon Potter
Change-Id: I02ffb1c4af980554ff12ac7d11d32ba80fe261c5 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12308 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-02mem: Move eraseIfNullEntry to when holder is updatedDaniel R. Carvalho
The entry should only be tested for deletion when holder is updated. Change-Id: I5a10b6fa876912709b7467860d43c23c60f38568 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19750 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-02mem: Encapsulate retry variables of SnoopFilterDaniel R. Carvalho
Group all variables related to the restoration of a snoop filter entry due to a crossbar retry. Change-Id: I4e03edb3afd06563b7a5812959739876709eceeb Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19749 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-01sim-se: small performance optimizationBrandon Potter
A local variable was being set inside a loop when it should have been set outside the loop. This changeset moves the variable to the appropriate place. Change-Id: If7655b501bd819c39d35dea4c316b4b9ed3173a2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17108 Maintainer: Brandon Potter <Brandon.Potter@amd.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-08-01sim-se: fstat64 bugfixBrandon Potter
The fstat64 system call does an upcast on entries in the file descriptor array to check if the file descriptor has a backing host-filesystem file opened. It does so because it needs to pass the host fd into the fstat call (since we rely on the host filesystem to service filesystem system calls). The upcast was overly specific. This changeset alters the system call to use the most general base class of the file descriptor entries that can satisfy the code. Change-Id: I10daf820257cea4d678ee6917e01e9cc9cd1cf5e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17110 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-08-01sim-se: add new option to getrlimit syscallBrandon Potter
The NPROC option was not serviced by the getrlimit syscall. This changeset adds in the necessary code to service the option. Change-Id: I679d3949c3bbb0628188f4e33034028d7726fdcb Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17109 Maintainer: Brandon Potter <Brandon.Potter@amd.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
2019-07-31mem-cache: mark block as dirty when handling SW prefetchTiago Mück
This addresses the issue described in 64687ee mem-cache: Mark block as dirty after a SWPrefetchEXResp. Previous patch misses cases when the prefetch response is ReadExResp or UpgradeResp. Also, marking the block as dirty in serviceMSHRTargets instead of in handleFill covers cases when the prefetch is coalesced with other requests. Change-Id: I2b377fdd240eb0f09e720b6bb284dee6545925ce Signed-off-by: Tiago Mück <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19688 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-31mem-cache: Fix set and way of sub-entriesDaniel R. Carvalho
Set and way of sub-entries were not being set previously. They must be set after the sub-blocks have been assigned to the main block. Change-Id: I7b6921b8437b29c472d691cd78cf20f2bb6c7e07 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19669 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-30dev-arm: Rewrite SMMUv3 CommandsGiacomo Travaglini
This patch is rewriting the SMMUv3::processCommand method for the following reasons: * Command names were not matching spec * Command encoding/opcode was wrong The patch is not adding any new command: there is still a subset of unimplemented commands; those are: * CMD_TLBI_EL3_ALL * CMD_TLBI_EL3_VA * CMD_TLBI_EL2_ALL * CMD_TLBI_EL2_VA * CMD_TLBI_EL2_VAA * CMD_TLBI_EL2_ASID which require StreamWorld support, and * CMD_ATC_INV * CMD_PRI_RESP * CMD_RESUME * CMD_STALL_TERM which require in sequence: ATS, PRI, Stall Model support Change-Id: Ia2dd47b5588738402d9584a00cfc88c94c253ad0 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Michiel van Tol <michiel.vantol@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19668 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-30configs, arch-arm: Check if gic has cpu_addr attributeChun-Chen TK Hsu
Add this check because Gicv3 does not have the cpu_addr attribute. Test: Change VExpress_GEM5_V1() to VExpress_GEM5_V2() and run the following command to boot Debian. M5_PATH=$PWD/fs_files ./build/ARM/gem5.opt ./configs/example/arm/fs_bigLITTLE.py \ --dtb $PWD/fs_files/binaries/armv8_gem5_v2_1cpu.dtb \ --kernel $PWD/fs_files/binaries/vmlinux \ --disk $PWD/fs_files/disks/disk.img \ --cpu-type atomic --big-cpus 1 --little-cpus 0 Change-Id: I23595ae5238dc7cc915ab09300f91aa5e8c24fdc Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19648 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-30system-arm: Add irq for hypervisor timer in device treeChun-Chen TK Hsu
ARM fast model CPU cannot get timer interrupts without this IRQ setting in the device tree. Change-Id: I084c475c04285f4f40eb38a80ddd038207e4764f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19650 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-07-30system-arm: Initialize ICC_SRE_EL3 registerChun-Chen TK Hsu
Fast model CPU will throw exceptions if ICC_SRE_EL3 is not initialized before accessing other interrupt controller system registers. Change-Id: I638f77aa7a3a4ad92abf2554d039c37601fbd44f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19649 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-07-28cpu: Fix the type of the effective mem request sizeGabor Dozsa
A memory request size can be larger than 255 bytes (e.g. SVE with 2048-bit vector length) which could cause overflow in the 'uint8_t effSize' variable. Change-Id: I77e0d02a49ea7f81cacfa5be7e4ae40434af3109 Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19175 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-07-28cpu-o3: Fix too strict assert condition in writeback()Gabor Dozsa
The assert() in the LSQ writeback() only allowed ReExec faults. However, a SplitRequest which completed the translation in PartialFault state (i.e. any but the very first cacheline translation failed) may end up here. The assert() condition is extended accordingly. The patch also removes the superfluous/unused Complete/Squashed states from the LSQ request. (The completion of the request is recorded in the flags still.) Change-Id: Ie575f4d3b4d5295585828ad8c7d3f4c7c1fe15d0 Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19174 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-07-27arch-arm: Fix reg dependency for SVE gather microopsGabor Dozsa
The first microop of an SVE gather creates a copy of the source vecreg into AA64FpUreg0. The subsequent microops must refer to this copy as a source in order to establish the correct register dependencies. Change-Id: I84d8c331f9f9ebca609948a15f686a7cde67dc31 Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19172 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-27arch-arm: Fix tracing code for SVE gatherGabor Dozsa
Printing the entire contents of the dest vecreg for each gather microop is suboptimal as it creates false positive differences between Atomic and O3 traces. This fix prints only the memory data which a microop loads from memory. Change-Id: Idd8e0b26a96f9c9cc0b69360174bedf6a9f6dcb5 Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19171 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-27arch-arm: Add SVE LD1RQ[BHWD]Javier Setoain
Add both scalar+scalar and scalar+immediate versions. Change-Id: If5fa1a71ab0dab93f9d35b544ea0899ece858bea Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19170 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-07-27arch-arm: Fix decoding for SVE memory instructionsAdrià Armejach
Some SVE memory instructions are missing the makeSP function for register operands that can be the SP register. This leads to segmentation faults on the application side as the wrong register is decoded. Change-Id: Ic71abc845e0786a60d665231b5f7b024d2955f4b Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19169 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-07-27arch-arm: Add support for SVE load/store structuresJavier Setoain
Change-Id: I4d9cde18dfc3d478eacc156de6a4a9721eb9e2ff Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13524 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-07-27cpu: Add first-/non-faulting load support to Minor and O3Gabor Dozsa
Some architectures allow masking faults of memory load instructions in some specific circumstances (e.g. first-faulting and non-faulting loads in Arm SVE). This patch adds support for such loads in the Minor and O3 CPU models. Change-Id: I264a81a078f049127779aa834e89f0e693ba0bea Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19178 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-25dev-arm: Fix SMMUv3 CMDQ wrappingGiacomo Travaglini
SMMU circular queues have a wrap bit which is used in order to distinguish between an empty queue and a full queue. According to SMMUv3 spec: Each index has a wrap flag, represented by the next higher bit adjacent to the index value contained in PROD and CONS. This bit must toggle each time the index wraps off the high end and back onto the low end of the buffer. It is the responsibility of the owner of each index, producer or consumer, to toggle this bit when the owner updates the index after wrapping. It is intended that software reads the register, increments or wraps the index (toggling wrap when required) and writes back both wrap and index fields at the same time. Change-Id: Idfeb397141f3627c2878caaeaa2625fadf671d2a Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com> Reviewed-by: Adrian Herrera <adrian.herrera@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19311 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-07-25dev-arm: Polish SMMUv3 CMDQ setupGiacomo Travaglini
The patch is aiming to be spec compliant when it comes to setup the SMMU command queue (while CR0.CMDQEN = 0), in the following ways: * Writes to CMDQ_CONS (read index) are allowed during initialization * Writes to CMDQ_BASE (cmdq pointer) are allowed during initialization According to spec, If they happen when the command queue is in fuction (CR0.CMDQEN = 1), behaviour is constrained unpredictable, with the following options 1) The write is ignored 2) The register takes the value and it is unpredictable whether it affects the SMMU command queue internal state. In the model/patch we go for option 1. Change-Id: I1c55bc571a8b3a1c0b0a525e429ab7b1480544ff Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19633 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-25dev-arm: Define enum masks for SMMU_CR0 registerGiacomo Travaglini
The configuration register is a vital register in the SMMU, and using enum masks will make the code more readable/understandable Change-Id: Ia117db56c457fe876ae38be391c386e502f34384 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19632 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-25dev-arm: TnSZ fields need to be cached in SMMUv3::ConfigCacheGiacomo Travaglini
Otherwise a hit after a table walk will result in a 0 value being read from the ConfigCache. Change-Id: I9813998acce44c93c5ce203f252ca80c10ba8f38 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com> Reviewed-by: Adrian Herrera <adrian.herrera@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19631 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-25dev-arm: SMMUv3 Table walks using TnSZGiacomo Travaglini
TnSZ is needed when selecting the starting level of a table walk, since it directly affects the number of IA bits. This has been implemented by adding T0SZ and S2T0SZ to the translation context. T1SZ is not used at the moment since the current model doesn't support TTB1. Change-Id: I75663475c4dc01e5986cd93f8deafcdf7b1ece82 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19630 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-25dev-arm: Use override keyword for SMMUv3 PTOPSGiacomo Travaglini
Replacing the "virtual" keyword Change-Id: I0e7b4b683ea222827a67c3a81f0deea0e906c7e5 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19629 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-25dev-arm: Add 16K granule support to SMMUv3 modelMichiel Van Tol
Added the necessary PageTableOps that match the 16K granule translation regime. Change-Id: I46ef07939cb4bdc8c0bbbeeeb6a50a9ab0d64de0 Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19628 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-23mem-ruby: Adding a new slicc statement - to not evict locked cachelinesPouya Fotouhi
Ruby caches block incoming ports with messages on a locked address to make sure the line would not be replaced by others. But they do not check the lock upon capacity/conflict misses. This change adds a new slicc statement "check_on_cache_probe" which takes two arguments (mandatoryQueue for the controller, and the line subject to eviction - i.e. address returned by cacheProbe). If the line is locked, incoming message is delayed for 1 cycle and the controller skips this request (i.e. does not trigger an event). Coherence protocols should be updated accordingly. One use case for MESI Two Level will be added in a separate change. Signed-off-by: Pouya Fotouhi <pfotouhi@ucdavis.edu> Change-Id: I79ca2d45518de7a4e382b520a11f8e221b0cb803 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16808 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-07-22arch-x86: Don't free PTW state with inflight requestsMatthew Poremba
If a page table walk is squashed, the walker state is being deleted in the squash code. If there are in flight requests, the deleted walker state values may be clobbered, leading to undefined behavior. This adds a squashed boolean to the walker state which is set if a walk is squashed while requests are still in flight. When packets for the in flight request return, we check if the walk was squashed and return that the walk is complete once the number of in flight requests reaches zero. The walker state is then freed by the PTW. Change-Id: I57a64b1548b83a8a9e8441fc9d6f33e9842df2b3 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19568 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-19arch-arm: Implement ARMv8.1-HPD, Hierarchical permission disableGiacomo Travaglini
According to the armarm: ARMv8.1-HPD introduces the facility to disable the hierarchical attributes, APTable, PXNTable, and UXNTable, in the translation tables. This disable has no effect on the NSTable bit. This feature is mandatory in ARMv8.1 implementations. This feature is added only to the VMSAv8-64 translation regimes. ARMv8.2 extends this to the AArch32 translation regimes, see ARMv8.2-AA32HPD. The ID_AA64MMFR1_EL1.HPDS field identifies the support for ARMv8.1-HPD. Change-Id: Ibbf589b82f2c1e4437b43252f8f633e8f6fb0b80 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19610 Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-19arch-arm: Add HPD bit for TCR_EL2/EL3Giacomo Travaglini
This is controlling Hierarchical Permissions for EL3 and for EL2 when HCR_EL2.E2H = 0. Change-Id: I9d6615ff4980cc56a28dc32088cf1524155f0fa4 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19609 Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-19arch-arm: Clean Fault generation when processing Long DescriptorGiacomo Travaglini
A new shared method has been introduced: generateLongDescFault Change-Id: I7eb6fa1347a6c2cf9cb11fd9f2137d983c4f7a40 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19608 Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-19dev-arm: clang compatibility fix, added missing overridesMatteo Andreozzi
Change-Id: I5ee5ff788570178bb1d68878a26ac9e3ce636d8e Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19588 Reviewed-by: Matteo Andreozzi <matteo.andreozzi@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-18arch-arm: Add first-/non-faulting load instructionsGabor Dozsa
First-/non-faulting loads are part of Arm SVE. Change-Id: I93dfd6d1d74791653927e99098ddb651150a8ef7 Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19177 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-18sim: Add getter to fault virtual addressGabor Dozsa
Change-Id: Ifd493aee9e78b0b4ddcc71e90f48679543acb861 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19176 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-17mem-cache: Create CPack compressorDaniel R. Carvalho
Implementation of C-Pack, as described in "C-Pack: A High- Performance Microprocessor Cache Compression Algorithm". C-Pack uses pattern matching schemes to detect and compress frequently appearing data patterns. As in the original paper, it divides the input in 32-bit words, and uses 6 patterns to match with its dictionary. For the patterns, each letter represents a byte: Z is a null byte, M is a dictionary match, X is a new value. The patterns are ZZZZ, XXXX, MMMM, MMXX, ZZZX, MMMX. Change-Id: I2efc9db2c862620dcc1155300e39be558f9017e0 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11105 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-17arch-arm: Use ExceptionLevel type in TlbEntryGiacomo Travaglini
Replacing uint8_t with ExceptionLevel type in the arm TlbEntry. The variable is representing the translation regime it is targeting. Change-Id: Ifcd6e86c5d73f752e8476a2b7fda9ea74a0c7a3b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19488 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-16arch-x86: add unconditional tag to calls/returnsHoa Nguyen
The branch predictor checks whether an instruction is unconditional branch before adding it or checking the RAS. With this change, the RAS is significantly more effective for short running x86 workloads. Change-Id: I60af5f2f583b898ad77f79f4b0478d6cda88fc21 Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19448 Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Gabe Black <gabeblack@google.com>
2019-07-16dev-arm: Fix SMMUv3 ContextDescriptor pointer shiftGiacomo Travaglini
The context descriptor pointer in the STE starts at the sixth LSB Change-Id: Ifa346b350785b788e9d1e093b662cb26433adfb8 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Christo Smallwood <christo.smallwood@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19469 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-16cpu: isDrained renamed to isCpuDrainedGiacomo Travaglini
cpu models inheriting from BaseCPU implement a draining checker called isDrained. This hides the base Drainable::isDrained method and might create confusion in the reader. This patch is renaming it to isCpuDrained in order to avoid any ambiguity Change-Id: Ie5221da6a4673432c2403996e42d451cae960bbf Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19468 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-13mem: Check response only when needed in CommMonitorChun-Chen TK Hsu
CommMonitor checks pkt->isResponse() for all packets in recvAtomic(). This assertion fails when packets don't need response, such as WritebackDirty. This change fixes this. Signed-off-by: Chun-Chen TK Hsu Change-Id: I168e349e179b14fa5472698d9300478dc89693fb Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19428 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-13cpu-o3: Set packet data type for IPR readPouya Fotouhi
This change assigns packet data type to static for IPR read. Caused by change (e13d6dc9c0d7a4ae0215f1ee6793eb32570c5169), and has been reported a few times in the mailing list. Change-Id: I0f02c20a16824e220df876e9e552bbc1c9636f95 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19449 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-10dev-arm: A9SCU fixupTiago Muck
Shifting instead of expensive power. Change-Id: I164933257db125e18721c5b8bcaf9702030ebf40 Signed-off-by: Tiago Mück <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19408 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-08cpu: Added the Multiperspective Perceptron Predictor with TAGE (8KB and 64KB)Javier Bueno Hedo
Described by the following article: Jiménez, D. "Multiperspective perceptron predictor with TAGE." Championship Branch Prediction (CBP-5) (2016). Change-Id: Ica3c121a4c94657d9015573085040e8a1984b069 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19188 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>
2019-07-08cpu-o3: Reset fault status for mem access in pushRequestGabor Dozsa
Reset the fault status always before translation is initiated in pushRequest() in the LSQ. This avoids the problem when a strictly ordered load needs to be re-executed multiple times. If the translation is delayed at one of those attempts then the internal panicFault (from the previous execution attempt) can get fired at commit. Change-Id: I0c22b2f7afd6e2cb00bc359a4a01042efd2d01d2 Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19388 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-06mem-ruby: Fix MultiGrainBloomFilter accessingDaniel R. Carvalho
When accessing the page filter the page hash should be used instead of the hash of the base filter. Change-Id: I17b7c64f2a0d654c7d9a77a7bfb435385d81032c Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18739 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-07-06mem-ruby: Remove Bloom Filters' ruby dependencyDaniel R. Carvalho
Substitute the common ruby header by base's bitfield to eliminate all ruby dependency in Bloom Filters. As a side note, BulkBloomFilter now assumes addresses are 64 bit long. Change-Id: Ibdb1f926ddcc06c848851c1e6a34863541808360 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18738 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-01 07:48:36 +0000