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AgeCommit message (Expand)Author
2019-12-11cpu: Replace empty byteEnable check with Request::isMaskedGiacomo Travaglini
2019-12-11cpu: Fix coding style (byteEnable->byte_enable)Giacomo Travaglini
2019-12-11cpu: Add byteEnable assertions to readMem and initateMemReadGiacomo Travaglini
2019-12-10sim,arch: Collapse the ISA specific versions of m5Syscall.Gabe Black
2019-12-10arch,cpu,sim: Push syscall number determination up to processes.Gabe Black
2019-12-10x86: Stop manually clearing RFLAGS.RF after a system call.Gabe Black
2019-12-10arch: Get rid of the now unused setSyscallArg.Gabe Black
2019-12-10arch: Stop using setSyscallArg to set argc and argv.Gabe Black
2019-12-10sim: Add a wrapper/subclass for SyscallDesc which uses GuestABI.Gabe Black
2019-12-10sim: Add a mechanism to translate ABIs to call host funcs from a TC.Gabe Black
2019-12-10sim: Get rid of the now unused SyscallDesc flags and methods.Gabe Black
2019-12-10arch: Use ignoreWarnOnceFunc instead of the WarnOnce flag.Gabe Black
2019-12-10sim: Reintroduce the ignoreWarnOnceFunc syscall handler.Gabe Black
2019-12-10sim: Make the syscalls use the SyscallReturn suppression mechanism.Gabe Black
2019-12-10dev-arm: GenericTimer, configurable base and low freqsAdrian Herrera
2019-12-10dev-arm: GenericTimer, freq as 32-bit valueAdrian Herrera
2019-12-10arch-arm: Disambuiguate NumFloatV7ArchRegs usageGiacomo Travaglini
2019-12-10arch-arm: Unify VLdmStm behaviour when reg out of indexGiacomo Travaglini
2019-12-10arch-arm: Fix NumVecV7ArchRegs value (64->16)Giacomo Travaglini
2019-12-10arch-arm: Reorder arch/arm/registers.hh constantsGiacomo Travaglini
2019-12-10arch-arm: Replace NumFloatV8ArchRegs with NumVecV8ArchRegsGiacomo Travaglini
2019-12-09tests: AArch64 Linux as quick regressions (instead of AArch32)Giacomo Travaglini
2019-12-09mem: Add Request::isMasked to check for byte strobingGiacomo Travaglini
2019-12-09mem: Add byteEnable copy to Request copy constructorGiacomo Travaglini
2019-12-09tests: Increase jenkins test timeout to 4 hours.Rahul Thakur
2019-12-08arch-riscv: set MaxMiscDestRegs to 2Alec Roelke
2019-12-07scons: Set the partial linking group for EXTRAS dirs.Gabe Black
2019-12-07scons: Fixes to improve python 3 support.Gabe Black
2019-12-06util: Add a git commit-msg hookDaniel R. Carvalho
2019-12-06kvm,arm: Update the KVM ARM v8 CPU to use vector regs.Gabe Black
2019-12-06arch-riscv: fix asmtest concurrent issues.Xin Ouyang
2019-12-05arch-x86: missing override specifierAndrea Mondelli
2019-12-05arch-x86: Adding LDDQU instructionmarjanfariborz
2019-12-04sim: Add a suppression mechanism to the SyscallReturn class.Gabe Black
2019-12-04sim: Small style fixes in sim/syscall_return.hh.Gabe Black
2019-12-04sim: Change the syscall executor to a std::function.Gabe Black
2019-12-04sparc: Fix the getresuidFunc prototype.Gabe Black
2019-12-04sparc: Fix the predecoder's moreBytes method.Gabe Black
2019-12-03systemc: Purposefully *expose* bind in the initiator socket.Gabe Black
2019-12-03fastmodel: Switch the diagnostic pragmas to GCC from clang.Gabe Black
2019-12-03misc: CONTRIBUTING.md to advise linking Jira Issues in commitsBobby R. Bruce
2019-12-03cpu,sim-se: move error checks in syscall methodsBrandon Potter
2019-12-03systemc,fastmodel: Use the gem5_scons error and warning functions.Gabe Black
2019-12-03systemc: Suppress a spurious clang warning in the systemc headers.Gabe Black
2019-12-03systemc: Fix up some lingering Accellera specific code in TLM v1.Gabe Black
2019-12-03base: add the FmtStackTrace debug optionCiro Santilli
2019-12-03sim-se: Avoid function overloading for syscall implementationGiacomo Travaglini
2019-12-03systemc: Add a bunch of missing overrides to the systemc headers.Gabe Black
2019-12-03fastmodel: Suppress a spurious warning on clang for amba_pv.h.Gabe Black
2019-12-01arch-riscv: Fix disassembling of immediate for c.lui instructionIan Jiang
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