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2020-02-25learning-gem5: timing readsimple-object-demoIru Cai
Change-Id: I566aa3e6e14c9d1784eaf93ede88c98a52a1fa71
2020-02-11learning-gem5: memory access example for simple objectIru Cai
Change-Id: I63a68239ac73b2bce3dea5692deac29a3467d27b
2020-02-04arch-arm: AArch64 reg access HCR_EL2.E2H filterAdrian Herrera
Some AArch64 system registers report UNDEFINED behaviours if accessed from EL2 or EL3 in a non-EL2 Host enabled (HCR_EL2.E2H == 0) environment. Examples of these are seen in the Generic Timer system registers, namely CNTP_CTL_EL02 or CNTKCTL_EL12. This patch provides an ISA filter for specifying the above condition. Change-Id: I240f9afdb000faf5d3c9274ba12bd4cc41fe8604 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24664 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-02-04arch-arm: reg access permissions highest EL helperAdrian Herrera
This patch implements a helper function to filter a register access permissions by the highest EL implemented by the system. This filtering is convenient to follow the architecture pseudocode. Change-Id: Iedfb2d8624c926f2f0a9326f8b1b073ea9424ab9 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24663 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-02-04arch-arm: Split translateFs to distinguish when MMU is on/offGiacomo Travaglini
This patch is splitting the big translateFs method so that it is using different methods when the MMU is on/off Change-Id: I198851bdbedf8a8e69730693ff87ffb9ed535ea3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24985 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-02-01arch,sim: Merge initCPU into the ISA System classes.Gabe Black
Those classes are already ISA specific, so we can just move initCPU's contents there and take it out of utility.hh, utility.cc, and the base System's initState. Change-Id: I28f0d0b50d83efe5116b0b24d20f8182a02823e7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24905 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-02-01arch,sim: Merge initCPU and startupCPU.Gabe Black
These two functions were called in exactly one place one right after the other, and served similar purposes. This change merges them together, and cleans them up slightly. It also removes checks for FullSystem, since those functions are only called in full system to begin with. Change-Id: I214f7d2d3f88960dccb5895c1241f61cd78716a8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24904 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-02-01sim,cpu: Move the call to initCPU into System.Gabe Black
The call to initCPU was moved into initState in the base CPU class since it should only really be called when starting a simulation fresh. Otherwise checkpointed state will be loaded over the state of the CPU anyway, so there's no reason to set up anything else. Unfortunately that made it possible for the System level initialization and the CPU initialization to happen out of order, effectively letting initCPU clobber the state the System might have set up to prepare for executing a kernel for instance. To work around that issue, the call was moved to init which would necessarily happen before initState, restoring the original ordering. This change moves the change *back* into initState, but of the System class instead of the CPU class. This makes it possible to guarantee that OS initialization happens after initCPU since that's also done by System subclasses, and they control when they call initCPU of the base class. This also slightly simmplifies when initCPU is called since we shouldn't need to check whether a context is switched out or not. If it's registered with the System object, then it should be in a currently swapped in CPU. This also puts the initCPU and startupCPU calls right next to each other. A future change will take advantage of that and merge the calls together. Also, because there are already ISA specific subclasses of System which already have specialized versions of initState, we should be able to move the code in initCPU and startupCPU directly into those subclasses. That will give those subclasses more flexibilty if, for instance, they want all CPUs to start running in the BIOS like they would on a real system, or if they want only the BSP to be active as if the BIOS had already paused the APs before passing control to a bootloader or OS. This will also remove another two TheISA:: style functions, reducing the number of global dependencies on a single ISA. Change-Id: Ic56924660a5b575a07844a198f69a0e7fa212b52 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24903 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-02-01arch,base,cpu: Add some default constructors/operators explicitly.Gabe Black
Having them implicitly is apparently deprecated and throws a warning in gcc 9, breaking the build. Change-Id: Id4e3074966d1ffc6dd1aed9397de5eea84400027 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24926 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-02-01base: Delete an inet.hh accessor which is unused and makes gcc 9 upset.Gabe Black
This accessor will return a pointer to an unaligned uint32_t. Since it's not used and it's not clear how to fix it trivially, this change just deletes it. Change-Id: I08bc62276d639cc728411f3a8a23be385000ebab Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24925 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-02-01scons: Disable spurious "array-bounds" warnings for protobuf cc files.Gabe Black
These files are generated and so, even if they're wrong, there isn't anything we can do about it. Change-Id: I933057a04f09dd1c22b525a102278bbdc5fbc22b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24924 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-02-01scons: Add a mechanism to append flags when building particular files.Gabe Black
This could be used to tweak settings for a particular file if it needed special treatment. I plan to use this for protobuf files which generate code that produce a warning in gcc 9 which turns into an error. Change-Id: I53e2dac48cd68f0cc8ad9031d8484c5036d6e4a6 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24923 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-31configs: allow fs.py and fs_bigLITTLE.py to work without M5_PATHCiro Santilli
The requirement to have an environment variable exported to run a program is not common, and many new users trip up on it. Before this commit, M5_PATH was a requirement to run those scripts, or else simulation would fail with: IOError: Can't find a path to system files. After this patch, as long as users indicate all required files with command line options, M5_PATH is not needed. This patch changes the M5_PATH semantics slightly to more closely match PATH and so be more intuitive to users: after this commit, if the given path contains a slash /, then the path is not searched for inside M5_PATH, which is exactly how PATH works. Users can then select images in the CWD with a leading ./ just as done for executables. This is backwards incompatible if users were already specifying their paths as ./, but this interface feels saner, because otherwise writing on the CLI e.g.: --disk-image path/to/my.disk would previously fail to find the disk, even if it existed, which is very counter-intuitive. The following will still fail however: --disk-image my.disk which is not ideal, but for now is a comprise between backwards compatibility of having an M5_PATH and what users expect from CLI interfaces. Change-Id: Ic91e1cc20557b35b69490b6dc420e7d324fae1fc Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23672 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-31configs: fs.py can take multiple disk images on most ISAsCiro Santilli
All ISAs except SPARC can now take multiple disk images by passing the --disk-image option multiple times. Before this patch, several ISAs automatically mounted a secondary disk called "linux-bigswap2.img", which had to be in M5_PATH even if the end user did not want more than one disk. This was the case for for example for X86 but not ARM. This change was done to: * allow ARM to have a second disk image in fs.py, which was not possible, and allow other ISAs like X86 and ARM to take any number of disk images * provide a simpler, more intuitive CLI interface that does not require magic disk images to be present in M5_PATH to work for ISAs such as X86. Linux does not need that secondary image to boot correctly, so it is more friendly to support a minimal setup that requires the least amount of binaries to boot, and let supply the second image manually only if they need it. * make fs.py --disk-image work more similarly across all ISAs SPARC was left with a single disk only because its setup was a bit more complex and would require further testing. Change-Id: I8b6e08ae6daf0a5b6cd1d57d285a9677f01eb7ad Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23671 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-31config: add --bootloader to fs.py and fs_bigLITTLE.pyCiro Santilli
This allows explicitly selecting which bootloader to use. Before this commit, the bootloader had a fixed basename which had to be present inside M5_PATH. Change-Id: I02919207d6f175854017ae7b603d811da63d618e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23670 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2020-01-31dev-arm: add boot_loader param to RealView setupBootLoaderCiro Santilli
This serves as a basis to select different bootloaders at runtime in future commits. Change-Id: I2ad0006fae9ad38ec1a6b1f11063be955a4dd2ea Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23669 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2020-01-31mem: Make slicc generate some default methods explicitly.Gabe Black
Implicitly using the default copy constructor and assignment operator is apparently deprecated, and gcc 9 will warn about it, breaking the build. Change-Id: Ida7a8a577e9d1cde9841eac7eee1af74563f1e27 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24927 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com> Reviewed-by: John Alsop <johnathan.alsop@amd.com> Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
2020-01-29misc: Updated old gem5 website URLs with new gem5 website URLsBobby R. Bruce
Jira: https://gem5.atlassian.net/browse/GEM5-272 Change-Id: Ieadb6dd7a44dde4b0be647c91896551822b06a57 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24503 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-29cpu: move initCPU calls from initState to initAyaz Akram
This commit moves the initCPU calls from initState to init of base cpu (which were added in commit 0b8d02dec492215aa). This is a temporary fix to solve the problem of X86System initState getting called before initState of base cpu. Jira Issue: https://gem5.atlassian.net/browse/GEM5-292 Change-Id: I7434cd811536175562cfa2646f4326907fadad8c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24884 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-27system-arm: AArch64 boot, init CNTFRQ_EL0Adrian Herrera
CNTFRQ_EL0 should be initialised to a uniform value in all cores present in the system. Previously, this was only done if EL3 was present, however architecture states CNTFRQ_EL0 may be written from the highest EL implemented. This patch moves this initilization outside of the EL3-only one. Change-Id: Ibaa197de53d531ba898e5137ba4f46a8c9554699 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24683 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-25sim: Add a GuestABI mechanism to allocate space for a return value.Gabe Black
Some ABIs (including 32 bit ARM, 64 bit x86) allocate their argument registers differently depending on their return value. For instance, if the value needs to be returned in memory because it's too big, the caller could pass a pointer to where the result should be stored when the function returns. This pointer acts like an invisible first argument, offsetting where all the normal arguments actually live. This change adds a mechanism to handle that case. The Result templates can now declare an allocate() static method which is given a ThreadContext *, and a reference to the Position object. It can perform any adjustment it needs to before the normal argument extraction starts. Change-Id: Ibda9095f0e8c9882742d24f5effe309ccb514188 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23747 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2020-01-24tests: Removed 70.twolf testsBobby R. Bruce
In an effort to cleanup the old tests, and migrate useful tests to be executed via `test/main.py`, it has been decided that the `test/quick/70.twolf` tests should be removed. Jira: https://gem5.atlassian.net/browse/GEM5-109 Change-Id: I19f2e20298e14a92f49adf0b8369e1fa09e0c1bc Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24383 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-24tests: Removed old quick/se/00.hello test resourcesBobby R. Bruce
Change-Id: I0579e2b7a131c679fd7488457595f046702d64ef Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24326 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-24tests: Removed the old ALPHA testsBobby R. Bruce
Jira: https://gem5.atlassian.net/browse/GEM5-109 Change-Id: Id24c84c70d977f7dbd2815b862af9b7eab638aca Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24388 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-24tests: Removed 50.vortex testsBobby R. Bruce
In an effort to cleanup the old tests, and migrate useful tests to be executed via `test/main.py`, it has been decided that the `test/long/se/50.vortex` tests should be removed. Jira: https://gem5.atlassian.net/browse/GEM5-109 Change-Id: I9c40ca74aad11a80bd2a91bd67c9561ffa76e78f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24387 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-24tests: Removed 60.bzip2 testsBobby R. Bruce
In an effort to cleanup the old tests, and migrate useful tests to be executed via `test/main.py`, it has been decided that the `test/quick/60.bzip2` tests should be removed. Jira: https://gem5.atlassian.net/browse/GEM5-109 Change-Id: I8469814a2f4715655960b9049182e426e10380ed Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24385 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-24tests: Removed 30.eon testsBobby R. Bruce
In an effort to cleanup the old tests, and migrate useful tests to be executed via `test/main.py`, it has been decided that the `test/long/se/30.eon` tests should be removed. Jira: https://gem5.atlassian.net/browse/GEM5-109 Change-Id: Ieb32196a5f0ed3b3375ede5aec6f8fb8d162a865 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24386 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-24tests: Removed 40.perlbmk testsBobby R. Bruce
In an effort to cleanup the old tests, and migrate useful tests to be executed via `test/main.py`, it has been decided that the `test/long/se/40.perlbmk` tests should be removed. Jira: https://gem5.atlassian.net/browse/GEM5-109 Change-Id: I3c7ea79717c90acf0656f30b878eb3f9f33fdb70 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24403 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-24tests: Removed 20.parser testsBobby R. Bruce
In an effort to cleanup the old tests, and migrate useful tests to be executed via `test/main.py`, it has been decided that the `test/long/se/70.twolf` tests should be removed. Jira: https://gem5.atlassian.net/browse/GEM5-109 Change-Id: Ie0c0cd310ee51a37e80a84af3bf1cb603061da7c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24384 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-23cpu: Fix ExeTraceRecord::traceInst.Gabe Black
A recent-ish change modified ExeTraceRecord::traceInst to make it more consistent with DPRINTF-s by using dprintf_flag to print the trace string. The generated string was passed as the format however, and that means that all % characters in the output (from register names, for example) are interpreted as format characters, mangling the output and making cprintf angry since there are no corresponding arguments. This change sets the format to "%s" instead, and passes the trace string as the first argument. The argument won't be parsed for format specifiers, and so should no longer get mangled. Change-Id: I8fa9c2c22179a5b55104a618a4af4080a3931c5f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24643 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-23sim: Move findFreeContext to System.Gabe Black
This method searches through the ThreadContexts stored in the system, and has no concrete connection to Process other than it happened to be used by a Process in the clone system call. By moving it, we can use its functionality in classes other than Process. Change-Id: Ic6899c335dc13841c6fe948ea3a4f8ad67e562bb Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24285 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-23sim: Eliminate the breakAtKernelFunction function.Gabe Black
It looks like this function is supposed to allow you to set up a PC based event which will trigger when the simulator executes a particular kernel function. That event doesn't actually do anything, but you can set a breakpoint there with gdb when debugging gem5 itself. There are a couple of problems with this function. First, it assumes that you want to set the breakpoint based on the first system in your simulation. Frequently simulations have only one system, but there isn't any rule that says they must, or any way to pick a different system. Second, this function assumes that you're in FS mode, that there is a kernel, and that there is a kernel symbol table to look symbols up in. On top of that, this function is a bit redundant since you can just use gdb to debug the kernel inside a simulated system. Change-Id: I8dadbd42fc7d4ccba2a035a2a72e6ede4b872f3c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24644 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-23dev-arm: SP805 peripherals in VExpress_GEM5_BaseAdrian Herrera
This patch adds the SP805 watchdog peripherals to the VExpress_GEM5_Base platform. Change-Id: I5c597d4d169359c1bde4bc4c7b3403091c772808 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24206 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2020-01-23tests: Removing 10.mcf testsBobby R. Bruce
10.mcf depends upon the proprietary SPEC benchmarks. It has been decided that tests which rely on them should be removed. Change-Id: If7ce915072643294bb4eb683ca1647d1022ee352 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24325 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-23cpu: Consolidate and move the CPU's calls to TheISA::initCPU.Gabe Black
TheISA::initCPU is basically an ISA specific implementation of reset logic on architectural state. As such, it only needs to be called if we're not going to load a checkpoint, ie in initState. Also, since the implementation was the same across all CPUs, this change collapses all the individual implementations down into the base CPU class. Change-Id: Id68133fd7f31619c90bf7b3aad35ae20871acaa4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24189 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2020-01-22scons: fix --gold-linker build after --as-neededCiro Santilli
The build was failing with: /usr/bin/ld: unrecognized option '--as-needed -fuse-ld=gold' and --verbose confirms that a single quoted CLI parameter was being executed: "-Wl,--as-needed -fuse-ld=gold" This happened because at Ifb001786a66b0dd9b29865e39a5740313002f250 --as-needed was added, and because it is the second option to happen before the following main.subst, it exposed the fact that the existing main.subst was wrong, because it returns a string instead of the expected array. Change-Id: I619d242d60fe9d27438638ac11c2b92512881f26 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24624 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-22dev-arm: add Watchdog Module SP805 modelAdrian Herrera
This provides a model of the Arm Watchdog Module SP805. This is based on the public TRM rev. r1p0 (ARM DDI 0270B). Integration test harness is not supported. Auto-generation of device tree entries is provided. Change-Id: I6157cec2212d0a1d2685bcfa983d2acbae1f3377 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24205 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-22dev-arm: VExpress_GEM5_Base, add refclock 32KHzAdrian Herrera
This patch adds the reference 32KHz clock to VExpress_GEM5_Base derived platforms. This is in preparation for supporting the SP805 Watchdog. I/O voltage domain and platform clock domain coupling is transferred to the __init__ method for correctness. Change-Id: Ic743fd986793f1e43b75fa60260c9b43b2737763 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24204 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-22tests: Fix python line break in m5_exit testGiacomo Travaglini
A bug has been introduced with the new test url. The line break should have used a backslash or (this is the recommended way by PEP8) the implied line continuation via parenthesis. This error was preventing the test to be loaded with the error message: Exception thrown while loading "/tmpfs/src/git/jenkins-gem5-prod/tests/gem5/m5_util/test_exit.py" Ignoring all tests in this file. and was not producing a failure (the test was not run: it was jus ignored). Change-Id: I0afe252d66d2f6546caaf5e7be811f34f88df82c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24625 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-22fastmodel: Implement CC reg accessors.Gabe Black
Change-Id: I4d8a7eaa097446b6aa3483880c2a7ed1a2e0d97c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23790 Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-22arm: Remove checkpointing from the ARM TLBs.Gabe Black
All of the state being checkpointed would either be provided by the config directly, or would be brought into the TLB through normal fill operations. Having this state in the checkpoint complicates the checkpoint and significantly decreases compatibility with other TLB implementations, or even variations of the same TLB, for instance if the size was changed. Change-Id: I4ea079dd01ff18fbc458b3aaaf88519dbcfdd869 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24389 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-22arch: Get rid of the unused (and mostly undefined) zeroRegisters.Gabe Black
Change-Id: Iadf56e4e742506af7ae4b617d2dc5a56439aa407 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24188 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-21misc: Updated CONTRIBUTING.md to discuss branchesBobby R. Bruce
There are some circumstances in which branches may be beneficial. Though, in general, they should be discouraged. Therefore, CONTRIBUTING.md has been enhanced to outline under what circumstances creation of new branches is allowed and how they may be created and used. Change-Id: I2df8b38868e5c8146b068d9e7e957abbe3cf3b38 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24263 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-21tests: Add a timeout to getremotetimeGiacomo Travaglini
The helper is meant to check if the local binary is younger than the remote binary (on gem5.org). If the call fails it is giving up and it is just using the local regression (producing a warning). The code is not handling the blocking behaviour of the connection: simulaton might stall indefinitely The patch is addressing this by providing a 10 seconds timeout. Change-Id: I8f9c2e555c9a55d850a66d02f8e55f56ceda2ca3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24531 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2020-01-21dev-arm: add FixedClock SimObjectAdrian Herrera
This patch adds a simple fixed-rate clock implementation based on SrcClockDomain. This provides RealView-derived platform users with a convenient way for auto-generating their platform clocks in the DTB. Change-Id: Ifade0cc8ed1b9e3423745698442cac5d8b99ab63 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24223 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-21tests: Adding --bin-path option to select tests bin directoryGiacomo Travaglini
So far lots of tests will download binaries inside the gem5 directory. The path is also specific to the test being run. This doesn't play well with an environment where gem5 is cloned from scratch for every build, or if several gem5 are cloned in a single machine. Binaries will be automatically downloaded every time this happens. This patch is adding a --bin-path option, so that it's possible to setup a fixed directory with all pre-downloaded binaries. By default it is set to None to preserve original behaviour. Change-Id: I42fb25e3ce0a495c73672b15a097b1bd2607795c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24525 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-21tests: fs/linux/arm passing M5_PATH via commandlineGiacomo Travaglini
This will make it configurable from the testing framework Change-Id: If82d5e44927c67a1eaecf41505d1d55a6469a4cf Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24524 Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2020-01-21mem-cache: Fix invalidation of prefetchersDaniel R. Carvalho
Add an invalidation function to the AssociativeSet, so that entries can be properly invalidated by also invalidating their replacement data. Both setInvalid and reset have been merged into invalidate to indicate users that they are using an incorrect approach by generating compilation errors, and to match CacheBlk's naming convention. Change-Id: I568076a3b5adda8b1311d9498b086c0dab457a14 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24529 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-20arch-arm: Fix EL2 target exception level for SP alignment fault.Jordi Vaquero
This commit fixes the target exception Level EL2 for alignmemt fault, it is based on HCR_EL2.tge bit. Change-Id: Ief78b2aa0c86f1c3d9a5d3ca00121d163a9d6a86 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24303 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-18tests: Updated tests to download from http://dist.gem5.orgBobby R. Bruce
Previously some tests, and test resources, downloaded content from http://gem5.org . This is being migrated to http://dist.gem5.org. http://dist.gem5.org should be used to store and retrieve resources going forward. Change-Id: I7162c76b9b8dc07657a6ba50d643fc93c9824fdf Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24548 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-02 23:18:07 +0000