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2007-04-13take a first stab at the release notesAli Saidi
AUTHORS: add sparc full system support to my list of accolades --HG-- extra : convert_revision : 1d3afaae2502306e44cd7fb251e763931a7e3ae9
2006-08-17AUTHORS:Lisa Hsu
minor change AUTHORS: minor change --HG-- extra : convert_revision : b638f14f0541ff5d48546c7fcd27d1bf0bdf615f
2006-08-16Add checkpointing and configuration stuff to the people that worked on itNathan Binkert
--HG-- extra : convert_revision : 565f0144d3aa6194665e49e3b0ad314c5d671bba
2006-08-16Added in SPARC ISA specifically. Thanks to whoever fleshed out my entry.Gabe Black
--HG-- extra : convert_revision : acb123227c7efbb46cc25e0ca69f7b2e2ec5b9c1
2006-08-16AUTHORS:Korey Sewell
fix 'reorganization' typo and added o3cpu multiple isa support to list AUTHORS: fix 'reorganization' typo and added o3cpu multiple isa support to list --HG-- extra : convert_revision : cd5d0ba69b37add0f10135e5772a57a7aacdf06e
2006-08-16Tweak my author listRon Dreslinski
--HG-- extra : convert_revision : ab79756d1c7fb4f8bfde86ef396597856a7ceb54
2006-08-16Add ppls contributions from looking at Authors header... Probably missed ↵Ali Saidi
stuff so look it over. Merge zizzer:/bk/newmem into zeep.pool:/z/saidi/tmp/m5.newmem AUTHORS: merge kevin's changes in --HG-- extra : convert_revision : 86344b6d89d90ec7002584d48736e29a9a3c72e5
2006-08-16I threw together the authors file from looking at the Authors of files.Ali Saidi
Feel free to change as you see fit AUTHORS: I threw together the authors file from looking at the Authors of files --HG-- extra : convert_revision : c13b52c60bbc429b29c64b5bebf5bf4971274a8d
2006-08-16Merge ksewell@zizzer:/bk/newmemKorey Sewell
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3 --HG-- extra : convert_revision : 8b6f649623cecec0964cff6fce6f4e6a041ae9a1
2006-08-16AUTHORS:Korey Sewell
add in contributions AUTHORS: add in contributions --HG-- extra : convert_revision : 93b5a74d3ab35cdba1d0c12b04e5cb27e5906b11
2006-08-16Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem --HG-- extra : convert_revision : 9eb38f53b5cab92e53a832d0e24e74ef68210abf
2006-08-16Add in contributions.Kevin Lim
--HG-- extra : convert_revision : 2f71f772f8fba536aa2d8f2beb6039b3fda9bbfc
2006-08-16Added the SPARC ISA as a contribution.Gabe Black
--HG-- extra : convert_revision : 74b061a14436425b2ac475bb498d71105bfa8e01
2006-08-16AUTHORS:Lisa Hsu
author file contribution AUTHORS: author file contribution --HG-- extra : convert_revision : f4a08695fb4bf37df6144529c5791c75c11a0515
2006-06-30Make O3CPU model independent of the ISAKorey Sewell
Use O3CPU when building instead of AlphaO3CPU. I could use some better python magic in the cpu_models.py file! AUTHORS: add middle initial SConstruct: change from AlphaO3CPU to O3CPU src/cpu/SConscript: edits to build O3CPU instead of AlphaO3CPU src/cpu/cpu_models.py: change substitution template to use proper CPU EXEC CONTEXT For O3CPU Model... Actually, some Python expertise could be used here. The 'env' variable is not passed to this file, so I had to parse through the ARGV to find the ISA... src/cpu/o3/base_dyn_inst.cc: src/cpu/o3/bpred_unit.cc: src/cpu/o3/commit.cc: src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/decode.cc: src/cpu/o3/fetch.cc: src/cpu/o3/iew.cc: src/cpu/o3/inst_queue.cc: src/cpu/o3/lsq.cc: src/cpu/o3/lsq_unit.cc: src/cpu/o3/mem_dep_unit.cc: src/cpu/o3/rename.cc: src/cpu/o3/rob.cc: use isa_specific.hh src/sim/process.cc: only initi NextNPC if not ALPHA src/cpu/o3/alpha/cpu.cc: alphao3cpu impl src/cpu/o3/alpha/cpu.hh: move AlphaTC to it's own file src/cpu/o3/alpha/cpu_impl.hh: Move AlphaTC to it's own file ... src/cpu/o3/alpha/dyn_inst.cc: src/cpu/o3/alpha/dyn_inst.hh: src/cpu/o3/alpha/dyn_inst_impl.hh: include paths src/cpu/o3/alpha/impl.hh: include paths, set default MaxThreads to 2 instead of 4 src/cpu/o3/alpha/params.hh: set Alpha Specific Params here src/python/m5/objects/O3CPU.py: add O3CPU class src/cpu/o3/SConscript: include isa-specific build files src/cpu/o3/alpha/thread_context.cc: NEW HOME of AlphaTC src/cpu/o3/alpha/thread_context.hh: new home of AlphaTC src/cpu/o3/isa_specific.hh: includes ISA specific files src/cpu/o3/params.hh: base o3 params src/cpu/o3/thread_context.hh: base o3 thread context src/cpu/o3/thread_context_impl.hh: base o3 thead context impl --HG-- rename : src/cpu/o3/alpha_cpu.cc => src/cpu/o3/alpha/cpu.cc rename : src/cpu/o3/alpha_cpu.hh => src/cpu/o3/alpha/cpu.hh rename : src/cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc rename : src/cpu/o3/alpha_cpu_impl.hh => src/cpu/o3/alpha/cpu_impl.hh rename : src/cpu/o3/alpha_dyn_inst.cc => src/cpu/o3/alpha/dyn_inst.cc rename : src/cpu/o3/alpha_dyn_inst.hh => src/cpu/o3/alpha/dyn_inst.hh rename : src/cpu/o3/alpha_dyn_inst_impl.hh => src/cpu/o3/alpha/dyn_inst_impl.hh rename : src/cpu/o3/alpha_impl.hh => src/cpu/o3/alpha/impl.hh rename : src/cpu/o3/alpha_params.hh => src/cpu/o3/alpha/params.hh rename : src/python/m5/objects/AlphaO3CPU.py => src/python/m5/objects/O3CPU.py extra : convert_revision : d377d6417452ac337bc502f28b2fde907d6b340e
2006-06-29Update the readme to point people to m5.eecs.umich.eduAli Saidi
start a new release section in RELEASE_NOTES add AUTHORS file that still needs work README: Update the readme to point people to m5.eecs.umich.edu RELEASE_NOTES: start a new release section --HG-- extra : convert_revision : 4c51e4255aecb67b10f18337428e5af114759d2e
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