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2016-03-30scons: Automatically install the git style hookAndreas Sandberg
Add a check in the main SConscript that installs the git pre-commit hook in util/ if git is used. Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> [andreas.sandberg@arm.com: Cleanups suggested by Steve] Reviewed-by: Steve Reinhardt <steve.reinhardt@amd.com> --HG-- extra : rebase_source : 4b805cdd74bc5442a65abf8a62e3e341f352c04e
2016-03-30scons, style: Rename style.py to hgstyle.pyAndreas Sandberg
The Mercurial style checker extensions are currently stored in style.py. This is not ideal since they won't work with other version control systems. This changeset renames style.py to hgstyle.py and adds upgrade code to scons that automatically updates the hooks in hgrc. Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Nathanael Premillieu <nathananel.premillieu@arm.com> Reviewed-by: Steve Reinhardt <steve.reinhardt@amd.com> --HG-- rename : util/style.py => util/hgstyle.py extra : rebase_source : ee8107ef245901371b368b7c2046ecdd89e3ff4c
2016-02-17scons: Enable building with the gcc/clang Address SanitizerAndreas Hansson
Allow the user to easily build gem5 with the Address Sanitizer, part of both gcc and clang these days.
2016-01-19gpu-compute: AMD's baseline GPU modelTony Gutierrez
2016-01-11scons: Enable -Wextra by defaultAndreas Hansson
Make best use of the compiler, and enable -Wextra as well as -Wall. There are a few issues that had to be resolved, but they are all trivial.
2016-01-11ext: Replace gzstream with iostream3 from zlib to avoid LGPLAndreas Hansson
This patch replaces the gzstream zlib wrapper with the iostream3 wrapper provided as part of zlib contributions. The main reason for the switch is to avoid including LGPL in the default gem5 build. iostream3 is provided under a more permissive license: The code is provided "as is", with the permission to use, copy, modify, distribute and sell it for any purpose without fee.
2015-12-04sim: Add support for generating back traces on errorsAndreas Sandberg
Add functionality to generate a back trace if gem5 crashes (SIGABRT or SIGSEGV). The current implementation uses glibc's stack traversal support if available and stubs out the call to print_backtrace() otherwise.
2015-11-15sim: support for distcc pump server settingsJoe Gross
2015-07-07ext: Add the NoMali GPU no-simulation libraryAndreas Sandberg
Add revision 9adf9d6e2d889a483a92136c96eb8a434d360561 of NoMali-model from https://github.com/ARM-software/nomali-model. This library implements the register interface of the Mali T6xx/T7xx series GPUs, but doesn't do any rendering. It can be used to hide the effects of software rendering.
2015-07-03scons: remove dead leading underscore checkCurtis Dunham
e56c3d8 (2008) added it but 8e37348 (2010) removed its only use.
2015-07-03scons: Bump compiler requirement to gcc >= 4.7 and clang >= 3.1Andreas Hansson
This patch updates the compiler minimum requirement to gcc 4.7 and clang 3.1, thus allowing: 1. Explicit virtual overrides (no need for M5_ATTR_OVERRIDE) 2. Non-static data member initializers 3. Template aliases 4. Delegating constructors This patch also enables a transition from --std=c++0x to --std=c++11.
2015-06-09scons: Allow GNU assembler version strings with hyphenAndreas Hansson
Make scons a bit more forgiving when determining the GNU assembler version.
2015-06-01kvm, arm: Add support for aarch64Andreas Sandberg
This changeset adds support for aarch64 in kvm. The CPU module supports both checkpointing and online CPU model switching as long as no devices are simulated by the host kernel. It currently has the following limitations: * The system register based generic timer can only be simulated by the host kernel. Workaround: Use a memory mapped timer instead to simulate the timer in gem5. * Simulating devices (e.g., the generic timer) in the host kernel requires that the host kernel also simulates the GIC. * ID registers in the host and in gem5 must match for switching between simulated CPUs and KVM. This is particularly important for ID registers describing memory system capabilities (e.g., ASID size, physical address size). * Switching between a virtualized CPU and a simulated CPU is currently not supported if in-kernel device emulation is used. This could be worked around by adding support for switching to the gem5 (e.g., the KvmGic) side of the device models. A simpler workaround is to avoid in-kernel device models altogether.
2015-05-23build: Don't test for KVM xsave support on ARMAndreas Sandberg
The current build tests for KVM unconditionally check for xsave support. This obviously never works on ARM since xsave is x86-specific. This changeset refactors the build tests probing for KVM support and moves the xsave test to an x86-specific section of is_isa_kvm_compatible().
2015-03-02tests: Run regression timeout as foregroundAndreas Hansson
Allow the user to send signals such as Ctrl C to the gem5 runs. Note that this assumes coreutils >= 8.13, which aligns with Ubuntu 12.04 and RHE6.
2015-02-03scons: Avoid implicit command dependenciesAndreas Hansson
Work around a bug in scons that causes the param wrappers being compiled twice. The easiest way for us to do so is to tell scons to ignore implicit command dependencies.
2014-12-22scons: Make the USE_KVM variable available in C++.Gabe Black
We need it to determine whether we should expect KVM related parameters exist in the cirrus graphics device.
2014-12-02scons: Ensure dictionary iteration is sorted by keyAndreas Hansson
This patch adds sorting based on the SimObject name or parameter name for all situations where we iterate over dictionaries. This should ensure a deterministic and consistent order across the host systems and hopefully avoid regression results differing across python versions.
2014-10-16config: Add the ability to read a config file using C++ and PythonAndreas Hansson
This patch adds the ability to load in config.ini files generated from gem5 into another instance of gem5 built without Python configuration support. The intended use case is for configuring gem5 when it is a library embedded in another simulation system. A parallel config file reader is also provided purely in Python to demonstrate the approach taken and to provided similar functionality for as-yet-unknown use models. The Python configuration file reader can read both .ini and .json files. C++ configuration file reading: A command line option has been added for scons to enable C++ configuration file reading: --with-cxx-config There is an example in util/cxx_config that shows C++ configuration in action. util/cxx_config/README explains how to build the example. Configuration is achieved by the object CxxConfigManager. It handles reading object descriptions from a CxxConfigFileBase object which wraps a config file reader. The wrapper class CxxIniFile is provided which wraps an IniFile for reading .ini files. Reading .json files from C++ would be possible with a similar wrapper and a JSON parser. After reading object descriptions, CxxConfigManager creates SimObjectParam-derived objects from the classes in the (generated with this patch) directory build/ARCH/cxx_config CxxConfigManager can then build SimObjects from those SimObjectParams (in an order dictated by the SimObject-value parameters on other objects) and bind ports of the produced SimObjects. A minimal set of instantiate-replacing member functions are provided by CxxConfigManager and few of the member functions of SimObject (such as drain) are extended onto CxxConfigManager. Python configuration file reading (configs/example/read_config.py): A Python version of the reader is also supplied with a similar interface to CxxConfigFileBase (In Python: ConfigFile) to config file readers. The Python config file reading will handle both .ini and .json files. The object construction strategy is slightly different in Python from the C++ reader as you need to avoid objects prematurely becoming the children of other objects when setting parameters. Port binding also needs to be strictly in the same port-index order as the original instantiation.
2014-10-16scons: Add Undefined Behavior Sanitizer (UBSan) optionAndreas Hansson
This patch adds the Undefined Behavior Sanitizer (UBSan) for clang and gcc >= 4.9. Due to the performance impact, the usage is guarded by a command-line option.
2014-09-22scons: Add --without-tcmalloc build optionCurtis Dunham
Disabling tcmalloc is required for valgrind's memcheck to work properly; this option makes it easier to create such a build.
2014-10-16config: Add a --without-python option to build processAndrew Bardsley
Add the ability to build libgem5 without embedded Python or the ability to configure with Python. This is a prelude to a patch to allow config.ini files to be loaded into libgem5 using only C++ which would make embedding gem5 within other simulation systems easier. This adds a few registration interfaces to things which cross between Python and C++. Namely: stats dumping and SimObject resolving
2014-10-09ext: Add DRAMPower to enable on-line DRAM power modellingAndreas Hansson
This patch adds the open-source (BSD 3-clause) tool DRAMPower, commit 8d3cf4bbb10aa202d850ef5e5e3e4f53aa668fa6, to be built as a part of the simulator. We have chosen this specific version of DRAMPower as it provides the necessary functionality, and future updates will be coordinated with the DRAMPower development team. The files added only include the bits needed to build the library, thus excluding all memory specifications, traces, and the stand-alone DRAMPower command-line tool. A future patch includes the DRAMPower functionality in the DRAM controller, to enable on-line DRAM power modelling, and avoid using post-processing of traces.
2014-10-09scons: Warn for known gcc and swig incompatibilitiesAndreas Hansson
2014-09-27scons: Address issues related to gcc 4.9.1Andreas Hansson
Fix a number few minor issues to please gcc 4.9.1. Removing the '-fuse-linker-plugin' flag means no libraries are part of the LTO process, but hopefully this is an acceptable loss, as the flag causes issues on a lot of systems (only certain combinations of gcc, ld and ar work).
2014-08-25tests: automatically kill regressions that take too longCurtis Dunham
When GNU coreutils 'timeout' is available, limit each regression simulation to 4 hours.
2014-09-03arch, cpu: Factor out the ExecContext into a proper base classAndreas Sandberg
We currently generate and compile one version of the ISA code per CPU model. This is obviously wasting a lot of resources at compile time. This changeset factors out the interface into a separate ExecContext class, which also serves as documentation for the interface between CPUs and the ISA code. While doing so, this changeset also fixes up interface inconsistencies between the different CPU models. The main argument for using one set of ISA code per CPU model has always been performance as this avoid indirect branches in the generated code. However, this argument does not hold water. Booting Linux on a simulated ARM system running in atomic mode (opt/10.linux-boot/realview-simple-atomic) is actually 2% faster (compiled using clang 3.4) after applying this patch. Additionally, compilation time is decreased by 35%.
2014-08-13scons: Silence clang 3.4 warnings on Ubuntu 12.04Andreas Sandberg
This changeset fixes three types of warnings that occur in clang 3.4 on Ubuntu 12.04: * Certain versions of libstdc++ (primarily 4.8) use struct and class interchangeably. This triggers a warning in clang. * Swig has a tendency to generate code with the register class which was deprecated in C++11. This triggers a deprecation warning in clang. * Swig sometimes generates Python wrapper code which returns uninitialized values. It's unclear if this is actually a problem (the cases might be limited to failure paths). We'll silence these warnings for now since there is little we can do about the generated code.
2014-08-10scons: Warn for incompatible gcc and binutilsAndreas Hansson
It seems gcc >4.8 does not get along well with binutils <= 2.22, and to help users this patch adds a warning with an indication for how to fix the issue. It might even be worth adding a Exit(-1) and stop the build.
2014-06-10scons: Bump the compiler version to gcc 4.6 and clang 3.0Andreas Hansson
This patch bumps the supported version of gcc from 4.4 to 4.6, and clang from 2.9 to 3.0. This enables, amongst other things, range-based for loops, lambda expressions, etc. The STL implementation shipping with 4.6 also has a full functional implementation of unique_ptr and shared_ptr.
2014-05-09arch: teach ISA parser how to split code across filesCurtis Dunham
This patch encompasses several interrelated and interdependent changes to the ISA generation step. The end goal is to reduce the size of the generated compilation units for instruction execution and decoding so that batch compilation can proceed with all CPUs active without exhausting physical memory. The ISA parser (src/arch/isa_parser.py) has been improved so that it can accept 'split [output_type];' directives at the top level of the grammar and 'split(output_type)' python calls within 'exec {{ ... }}' blocks. This has the effect of "splitting" the files into smaller compilation units. I use air-quotes around "splitting" because the files themselves are not split, but preprocessing directives are inserted to have the same effect. Architecturally, the ISA parser has had some changes in how it works. In general, it emits code sooner. It doesn't generate per-CPU files, and instead defers to the C preprocessor to create the duplicate copies for each CPU type. Likewise there are more files emitted and the C preprocessor does more substitution that used to be done by the ISA parser. Finally, the build system (SCons) needs to be able to cope with a dynamic list of source files coming out of the ISA parser. The changes to the SCons{cript,truct} files support this. In broad strokes, the targets requested on the command line are hidden from SCons until all the build dependencies are determined, otherwise it would try, realize it can't reach the goal, and terminate in failure. Since build steps (i.e. running the ISA parser) must be taken to determine the file list, several new build stages have been inserted at the very start of the build. First, the build dependencies from the ISA parser will be emitted to arch/$ISA/generated/inc.d, which is then read by a new SCons builder to finalize the dependencies. (Once inc.d exists, the ISA parser will not need to be run to complete this step.) Once the dependencies are known, the 'Environments' are made by the makeEnv() function. This function used to be called before the build began but now happens during the build. It is easy to see that this step is quite slow; this is a known issue and it's important to realize that it was already slow, but there was no obvious cause to attribute it to since nothing was displayed to the terminal. Since new steps that used to be performed serially are now in a potentially-parallel build phase, the pathname handling in the SCons scripts has been tightened up to deal with chdir() race conditions. In general, pathnames are computed earlier and more likely to be stored, passed around, and processed as absolute paths rather than relative paths. In the end, some of these issues had to be fixed by inserting serializing dependencies in the build. Minor note: For the null ISA, we just provide a dummy inc.d so SCons is never compelled to try to generate it. While it seems slightly wrong to have anything in src/arch/*/generated (i.e. a non-generated 'generated' file), it's by far the simplest solution.
2014-05-09scons: Require SWIG >= 2.0.4 and remove vector typemapsCurtis Dunham
SWIG commit fd666c1 (*) made it unnecessary for gem5 to have these typemaps to handle Vector types. * https://github.com/swig/swig/commit/fd666c1440628a847793bbe1333c27dfa2f757f0
2014-04-13scons: Fix python-config parsing by adding strip()Andreas Hansson
This patch fixes an issue with the way the python-config path is parsed, as it caused issues on systems where a newline ended up being included in the path.
2014-04-10scons: compile on systems where python2 and python3 co-existStian Hvatum
Compile gem5 on systems where python2 and python3 co-exists without any changes in path. python2-config is chosen over python-config if it exists. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-03-23scons: Shush sconsCurtis Dunham
make 'scons -s' actually silent.
2014-03-07scons: Fix clang version identification for OSXMitch Hayenga
The version string may have additional trailing information
2014-02-18scons: Add PROTOC from the environmentAndreas Hansson
This patch adds PROTOC to the build environment.
2014-02-18mem: Add a wrapped DRAMSim2 memory controllerAndreas Hansson
This patch adds DRAMSim2 as a memory controller by wrapping the external library and creating a sublass of AbstractMemory that bridges between the semantics of gem5 and the DRAMSim2 interface. The DRAMSim2 wrapper extracts the clock period from the config file. There is no way of extracting this information from DRAMSim2 itself, so we simply read the same config file and get it from there. To properly model the response queue, the wrapper keeps track of how many transactions are in the actual controller, and how many are stacking up waiting to be sent back as responses (in the wrapper). The latter requires us to move away from the queued port and manage the packets ourselves. This is due to DRAMSim2 not having any flow control on the response path. DRAMSim2 assumes that the transactions it is given are matching the burst size of the choosen memory. The wrapper checks to ensure the cache line size of the system matches the burst size of DRAMSim2 as there are currently no provisions to split the system requests. In theory we could allow a cache line size smaller than the burst size, but that would lead to inefficient use of the DRAM, so for not we fatal also in this case.
2013-10-15kvm: Set the perf exclude_host attribute if availableAndreas Sandberg
The performance counting framework in Linux 3.2 and onwards supports an attribute to exclude events generated by the host when running KVM. Setting this attribute allows us to get more reliable measurements of the guest machine. For example, on a highly loaded system, the instruction counts from the guest can be severely distorted by the host kernel (e.g., by page fault handlers). This changeset introduces a check for the attribute and enables it in the KVM CPU if present.
2013-10-17build: Enable color diagnostics in clang by preserving TERM.Stan Czerniawski
2013-10-02kvm: Only include KVM support for supported kernelsAndreas Hansson
This patch adds a check to ensure that the KVM API provided by the running kernel is what we are expecting.
2013-10-01scons, kvm: Check for the presence of POSIX timersAndreas Sandberg
The kvm-based CPU module requires support for POSIX timers. This changeset adds a check for POSIX timers and ensures that gem5 is linked with librt if necessary. KVM support is disabled if POSIX timers are not supported by the host. This fixes a compilation issue for some glibc versions where clock_nanosleep and timer_create are in different libraries.
2013-09-30ext: Include libfputilsAndreas Sandberg
This changeset includes libfputils from revision bbf0d61d75. This library can be used to convert to and from 80-bit floats and query the type of an 80-bit float, which is needed to support the x87 FPU.
2013-09-25kvm: Initial x86 supportAndreas Sandberg
This changeset adds support for KVM on x86. Full support is split across a number of commits since some features are relatively complex. This changeset includes support for: * Integer state synchronization (including segment regs) * CPUID (gem5's CPUID values are inserted into KVM) * x86 legacy IO (remapped and handled by gem5's memory system) * Memory mapped IO * PCI * MSRs * State dumping Most of the functionality is fairly straight forward. There are some quirks to support PCI enumerations since this is done in the TLB(!) in the simulated CPUs. We currently replicate some of that code. Unlike the ARM implementation, the x86 implementation of the virtual CPU does not use the cycles hardware counter. KVM on x86 simulates the time stamp counter (TSC) in the kernel. If we just measure host cycles using perfevent, we might end up measuring a slightly different number of cycles. If we don't get the cycle accounting right, we might end up rewinding the TSC, with all kinds of chaos as a result. An additional feature of the KVM CPU on x86 is extended state dumping. This enables Python scripts controlling the simulator to request dumping of a subset of the processor state. The following methods are currenlty supported: * dumpFpuRegs * dumpIntRegs * dumpSpecRegs * dumpDebugRegs * dumpXCRs * dumpXSave * dumpVCpuEvents * dumpMSRs Known limitations: * M5 ops are currently not supported. * FPU synchronization is not supported (only affects CPU switching). Both of the limitations will be addressed in separate commits.
2013-09-18swig: Warn on use of incompatible swig/gcc combinationsAndreas Hansson
This patch removes the fixed swig warning concerning 2.0.9/2.0.10 and adds a warning message for incompatible combinations of swig and gcc.
2013-09-04scons: Enable build on OSXAndreas Hansson
This patch changes the SConscript to build gem5 with libc++ on OSX as the conventional libstdc++ does not have the C++11 constructs that the current code base makes use of (e.g. std::forward). Since this was the last use of the transitional TR1, the unordered map and set header can now be simplified as well.
2013-07-18scons: Use python-config instead of distutilsAndreas Hansson
This patch changes how we determine the Python-related compiler and linker flags. The previous approach used the internal LINKFORSHARED which is not intended as part of the external API (http://bugs.python.org/issue3588) and causes failures on recent OSX installations. Instead of using distutils we now rely on python-config and scons ParseConfig. For backwards compatibility we also parse out the includes and libs although this could safely be dropped. The drawback of this patch is that Python 2.5 is now required, but hopefully that is an acceptable compromise as any system with gcc 4.4 most likely will have Python >= 2.5.
2013-06-04scons: ammend swig warning error to version 2.0.10 as wellAli Saidi
2013-04-22kvm: Add basic support for ARMAndreas Sandberg
Architecture specific limitations: * LPAE is currently not supported by gem5. We therefore panic if LPAE is enabled when returning to gem5. * The co-processor based interface to the architected timer is unsupported. We can't support this due to limitations in the KVM API on ARM. * M5 ops are currently not supported. This requires either a kernel hack or a memory mapped device that handles the guest<->m5 interface.
2013-04-22kvm: Basic support for hardware virtualized CPUsAndreas Sandberg
This changeset introduces the architecture independent parts required to support KVM-accelerated CPUs. It introduces two new simulation objects: KvmVM -- The KVM VM is a component shared between all CPUs in a shared memory domain. It is typically instantiated as a child of the system object in the simulation hierarchy. It provides access to KVM VM specific interfaces. BaseKvmCPU -- Abstract base class for all KVM-based CPUs. Architecture dependent CPU implementations inherit from this class and implement the following methods: * updateKvmState() -- Update the architecture-dependent KVM state from the gem5 thread context associated with the CPU. * updateThreadContext() -- Update the thread context from the architecture-dependent KVM state. * dump() -- Dump the KVM state using (optional). In order to deliver interrupts to the guest, CPU implementations typically override the tick() method and check for, and deliver, interrupts prior to entering KVM. Hardware-virutalized CPU currently have the following limitations: * SE mode is not supported. * PC events are not supported. * Timing statistics are currently very limited. The current approach simply scales the host cycles with a user-configurable factor. * The simulated system must not contain any caches. * Since cycle counts are approximate, there is no way to request an exact number of cycles (or instructions) to be executed by the CPU. * Hardware virtualized CPUs and gem5 CPUs must not execute at the same time in the same simulator instance. * Only single-CPU systems can be simulated. * Remote GDB connections to the guest system are not supported. Additionally, m5ops requires an architecture specific interface and might not be supported.