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2004-11-13Macros are nasty, so let's get rid of them. Convert allNathan Binkert
all macros in ev5.hh to inline functions or constant typed variables and make them follow our style while we're at it. All of the stuff in this file actually belongs in the ISA traits code, but this is a first step at getting things done in the right manner. arch/alpha/alpha_memory.cc: arch/alpha/alpha_memory.hh: arch/alpha/ev5.cc: arch/alpha/isa_desc: dev/ns_gige.cc: kern/tru64/tru64_events.cc: deal with changes in ev5.hh arch/alpha/ev5.hh: Macros are nasty, so let's get rid of them. Convert all all macros to inline functions or constant typed variables. Make them follow our style while we're at it. All of the stuff in this file actually belongs in the ISA traits code, but this is a first step at getting things done in the right manner. arch/alpha/isa_traits.hh: move some of the ev5 specific code into the isa arch/alpha/vtophys.cc: base/remote_gdb.cc: deal with isa addition cpu/exec_context.hh: be less isa specific and use the isa traits to figure out what we can. dev/alpha_console.cc: dev/pciconfigall.cc: dev/tsunami_cchip.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: dev/uart.cc: deal with changes in ev5.hh I don't believe this masking is actually necessary. We should look at removing it later. dev/ide_ctrl.cc: sort #includes deal with changes in ev5.hh --HG-- extra : convert_revision : c8a3adf0a4b1d198aefe38fc38b295abf289b08a
2004-11-13defining SYSTEM_EV5 isn't all that necessaryNathan Binkert
--HG-- extra : convert_revision : 2ed4866db9483820d550bad00fdbc8dd027f95ba
2004-11-13defining SYSTEM_EV5 isn't all that necessaryNathan Binkert
--HG-- extra : convert_revision : 7d39dd9f814434cb95ec769204d7f2426b0290fd
2004-11-10Use the inPalMode function instead of the PC_PAL macroNathan Binkert
--HG-- extra : convert_revision : 58e0a19ba98777e5d2e2572ed02dee1914378ff7
2004-11-10Don't use the global check_interrupts variable. Add a per-cpuNathan Binkert
checkInterrupts variable and use that to determine whether an interrupt can occur on a given cycle. arch/alpha/ev5.cc: XC -> CPU (and xc -> CPU) since we're really talking about a CPU here Don't use the global check_interrupts variable. Add a per-cpu checkInterrupts variable and use that to determine whether an interrupt can occur on a given cycle. --HG-- extra : convert_revision : be4c0247e5834005c60a45796a222cffd327b64e
2004-10-25Don't use magic numbers.Nathan Binkert
arch/alpha/isa_traits.hh: Move defines to non full system code section so they can be used elsewhere cpu/simple_cpu/simple_cpu.cc: Don't use magic numbers cpu/simple_cpu/simple_cpu.hh: simple format nit --HG-- extra : convert_revision : b8d492218340d41ab9420c6ad1e81a197db1c132
2004-10-23get rid of pmap.h and make things variables and inlineNathan Binkert
functions instead of preprocessor macros. arch/alpha/vtophys.cc: use new constants, functions and structs to clean up the vtophys code. arch/alpha/vtophys.hh: Clean up a little bit and make the protypes match new changes. base/remote_gdb.cc: dev/ide_disk.cc: kern/tru64/tru64_events.cc: use new constants from isa_traits.hh instead of ones from old pmap.h --HG-- extra : convert_revision : 5dce34e3b0c84ba72cefca34e5999b99898edcef
2004-10-23in the arch/alpha directory we should use arch/alpha, notNathan Binkert
targetarch. arch/alpha/alpha_memory.cc: arch/alpha/arguments.cc: arch/alpha/arguments.hh: arch/alpha/faults.cc: arch/alpha/isa_traits.hh: arch/alpha/osfpal.cc: arch/alpha/vtophys.cc: arch/alpha/vtophys.hh: in the arch/alpha directory we should use arch/alpha, not targetarch. sort includes while we're here. --HG-- extra : convert_revision : 99a71540e2997173db5c1072cef910a26acc75b2
2004-10-22Make targetarch directory in build tree and copy arch/alpha files to itSteve Reinhardt
instead of using symlink. The symlink broke scons's built-in include dependency tacking. Interestingly once it was fixed scons discovered two circular dependency problems which are also fixed now. SConscript: Make targetarch directory in build tree and copy arch/alpha files to it instead of using symlink. The symlink broke scons's built-in include dependency tacking. arch/alpha/ev5.hh: Get rid of circular #include dependence. kern/kernel_stats.cc: Add needed header file. kern/linux/linux_syscalls.hh: kern/tru64/tru64_syscalls.hh: Replace targetarch/syscalls.hh with single template class declaration. --HG-- extra : convert_revision : b8551623c1d441c6eb8d0651387e97e373128814
2004-10-16Fixes for bigendian platformsAli Saidi
arch/alpha/vtophys.cc: PGOFSET -> ALPHA_PGOFSET to avoid include file problems base/callback.hh: Added a class to create a callback from a function base/intmath.hh: make FloorLog2 inlined dev/pcidev.cc: more work in getting pciconfig space happy with different endiannesses dev/uart.cc: used an incorrect size for write uint64_t instead of uint8_t sim/system.cc: when writing things into system data structures we need to pay attention to endianness --HG-- extra : convert_revision : 52f441b5789c45db30ef2f6fd4975cbc7323a381
2004-09-22Merge zizzer:/bk/m5 into zeep.eecs.umich.edu:/z/saidi/work/m5-smpAli Saidi
--HG-- extra : convert_revision : 19dc01e1c0d2c0ba6b4d804b902429fb0a6a5552
2004-09-22fix unaligned memory offset and some small fixes to interrupt binningAli Saidi
code arch/alpha/alpha_memory.cc: Fixed unaligned trap faults arch/alpha/ev5.cc: little more verbose faulting information kern/linux/linux_system.cc: more descriptive errors, and the correct offsets from symbols sim/system.cc: load local pal symbols --HG-- extra : convert_revision : 0c81badf77321d5e1a060dcae2d42204e5a1fc84
2004-09-20Update copies to work around alignment faults.Erik Hallnor
arch/alpha/isa_desc: whitespace fix. cpu/simple_cpu/simple_cpu.cc: Add support to make sure we don't get alignment faults in copies. Warn if we go over an 8k page boundary. --HG-- extra : convert_revision : 98b38da86a66215d80ea9eb6e6f1f68ee573cb57
2004-09-03added system option to bin interrupt code seperately.Ali Saidi
arch/alpha/ev5.cc: set the mode explictly rather than having a bool user/notuser cpu/simple_cpu/simple_cpu.hh: there is no class Kernel kern/kernel_stats.cc: use cpu_mode_num kern/kernel_stats.hh: add interrupt mode and use cpu_mode_num rather than constant kern/linux/linux_system.cc: kern/linux/linux_system.hh: kern/system_events.cc: kern/system_events.hh: add events to change the mode to/from interrupt sim/system.cc: sim/system.hh: add a pal symbol table --HG-- extra : convert_revision : 9d30e826b72122062a5ea12d094f94760e75c66a
2004-08-20- Clean up and factor out all of the binning code into aNathan Binkert
single place so it's easier to work with. - Add support for binning kernel/user/idle time separately from lisa's binning stuff, but make the two compatible. - KernelStats used to directly implement the pImpl idiom, but it makes more sense to just remove the level of indirection and make the exec context have a pointer to the stats. - Factor common code out of LinuxSystem and Tru64System and put it into the System base class. While doing that, make all constructors take a pointer to a parameter struct instead of naming the parameters individually to make it much easier to add parameters to these classes. SConscript: Move the function tracking and binning stuff around. arch/alpha/ev5.cc: kernelStats is now a pointer arch/alpha/pseudo_inst.cc: kernelStats is now a pointer the parameters to the system have been moved into their own struct base/trace.hh: provide a little functor class for wrapping a string that can allow you to define name() in any scope very simply for use with DPRINTF cpu/base_cpu.cc: New order of arguments for consistency. cpu/exec_context.cc: kernelStats no longer has the level of indirection in it, execContext has the indirection now. so, kernelStats is a pointer. We also need a pointer to the kernelBinning stuff from the system and we need to figure out if we want to do binning or not. Move a whole bunch of code into kern_binning.cc so it's all in the same place. cpu/exec_context.hh: We want pointers to the kernel binning/stats stuff and we'll have the exec_context and system have the level of indirection instead of having the extra layer in the kernel stats class. cpu/simple_cpu/simple_cpu.cc: call through the exec context to do the special binning stuff. kern/kernel_stats.cc: kern/kernel_stats.hh: Re-organize the stats stuff and remove the level of indirection (that was there to simplify building) and move the binning stuff into its own class/file. kern/linux/linux_system.cc: kern/linux/linux_system.hh: kern/tru64/tru64_system.cc: kern/tru64/tru64_system.hh: sim/system.cc: sim/system.hh: move lots of common system code into the base system class so that it can be shared between linux, tru64, and whatever else we decide to support in the future. Make the constructor take a pointer to a parameter struct so that it is easier to pass parameters to the parent. kern/system_events.cc: move the majority of the binning code into the Kernel::Binning class in the kern_binning file kern/system_events.hh: FnEvents only need to know the bin create the Idle start event to find the PCBB of the idle process when it starts. kern/tru64/tru64_events.cc: memCtrl -> memctrl sim/process.cc: sim/process.hh: re-order args for consistency --HG-- extra : convert_revision : 86cb39738c41fcd680f2aad125c9dde000227b2b
2004-08-02merged full_cpu.ini, system.ini and devtime.cAli Saidi
util/ccdrv/devtime.c: coding style --HG-- extra : convert_revision : 972941e100ba13a2ece0986454c4a3485841d9cb
2004-08-02added m5 debug and m5 switch cpu instruction (doesn't work yet) andAli Saidi
a p4 memory/cpu config arch/alpha/alpha_memory.cc: Added code to fault on an unaligned access arch/alpha/isa_desc: arch/alpha/pseudo_inst.cc: arch/alpha/pseudo_inst.hh: Added m5debug break and m5switchcpu (the latter doesn't work) --HG-- extra : convert_revision : 409e73adb151600a4fea49f35bf6f503f66fa916
2004-07-30Added debug printk supportAli Saidi
arch/alpha/ev5.hh: Added max address PAL code can be at arch/alpha/vtophys.cc: Check max address pal can be at so we don't do the wrong conversion if gdb asks for an unaligned access. --HG-- extra : convert_revision : b44f6a8fcd8582337a7d4033f28137c7e718a6a8
2004-07-08fixed a bad merge from linux<->tru64Ali Saidi
--HG-- extra : convert_revision : d7a5acd89a2bdc013c8a2bd022cc7048a3920f01
2004-07-02Need to #include <unistd.h> to build with preadNathan Binkert
--HG-- extra : convert_revision : 1e5b3e5f1eaba3853d7d3da5546387c16932ab6a
2004-07-01implement the readfile pseudo instruction that will readNathan Binkert
a realworld file. arch/alpha/isa_desc: arch/alpha/pseudo_inst.hh: implement the readfile pseudo instruction that will read a chunk of a realworld file. arch/alpha/pseudo_inst.cc: implement the readfile pseudo instruction that will read a chunk of a realworld file. The filename is a per system parameter and comes from the system itself. kern/linux/linux_system.cc: sim/system.hh: Create a per-system readfile parameter for use by the readfile pseudo instruction. That way each system can get its own file. --HG-- extra : convert_revision : 941b3a3e20702a6252b219ca66a6d90da2944c50
2004-07-01rename CopyData to CopyOut and implement CopyIn to copy dataNathan Binkert
from the simulator into the simulatee kern/tru64/dump_mbuf.cc: rename CopyData -> CopyOut --HG-- extra : convert_revision : e3ef27a5762dfc495dcb84a372470464c27557d2
2004-06-30add asn when tracing tlb stuffNathan Binkert
--HG-- extra : convert_revision : abc774179b3d4c979efd98e32d1d071b142e7b48
2004-06-28fix up the recordEvent stuff to support ignoring eventsNathan Binkert
arch/alpha/ev5.cc: cpu/simple_cpu/simple_cpu.cc: update for new event interface base/stats/events.cc: implement the ignore event function which matches sim objects from which to ignore events. Make insert event like insert data and make it able to insert many events in a single transaction with the database. base/stats/events.hh: Make it possible to ignore events sim/sim_object.cc: make recordEvent a member function of SimObject to implement the ignore function easily sim/sim_object.hh: implement the ignore event stuff in the sim object. This is a bit of a hack, but an easy place to put it. --HG-- extra : convert_revision : ba3f25a14ad03662c53fb35514860d69be8cd4f0
2004-06-22ifdefed ev5 vs. ev6 differences so Tlaser can work in the linux treeAli Saidi
arch/alpha/alpha_memory.cc: arch/alpha/ev5.hh: Ifdefed TLASER code arch/alpha/vtophys.cc: added back some code andrew removed and couldn't remember why. --HG-- extra : convert_revision : f00d255f7a8a7bdb6e74f061dd014188e3b39e73
2004-06-22pull from head before pushing linux treeAli Saidi
--HG-- extra : convert_revision : 345f91c5c16c69db22035dc716e82fd77041380f
2004-06-15Get software prefetching to work in full-system mode.Steve Reinhardt
Mostly a matter of keeping prefetches to invalid addrs from messing up VM IPRs. Also discovered that wh64s were not being treated as prefetches, when they really should be (for the most part, anyway). arch/alpha/alpha_memory.cc: arch/alpha/alpha_memory.hh: - Get rid of intrlock flag for locking VM fault regs (a la EV5); instead, just don't update regs on VPTE loads (a la EV6). - Add NO_FAULT MemReq flag to indicate references that should not cause page faults (i.e., prefetches). arch/alpha/ev5.cc: - Get rid of intrlock flag for locking VM fault regs (a la EV5); instead, just don't update regs on VPTE loads (a la EV6). - Add Fault trace flag. arch/alpha/isa_desc: - Add NO_FAULT MemReq flag to indicate references that should not cause page faults (i.e., prefetches). - Mark wh64 as a "data prefetch" instruction so it gets controlled properly by the FullCPU data prefetch control switch. - Align wh64 EA in decoder so issue stage doesn't need to worry about it. arch/alpha/isa_traits.hh: - Get rid of intrlock flag for locking VM fault regs (a la EV5); instead, just don't update regs on VPTE loads (a la EV6). base/traceflags.py: - Add Fault trace flag. cpu/simple_cpu/simple_cpu.hh: - Pass MemReq flags to writeHint() operation. cpu/static_inst.hh: Update comment re: prefetches. --HG-- extra : convert_revision : 62e466b0f4c0ff9961796270fa2e371ec24bcbb6
2004-06-10Fixes for detailed boot, made cttz and ctlz instructions more compact,Ali Saidi
and started cleaning up config files. arch/alpha/isa_desc: Made implementation of cttz and ctlz more compact base/remote_gdb.cc: Added comment about PALcode debugger accesses dev/baddev.cc: dev/baddev.hh: dev/ide_ctrl.cc: dev/ide_ctrl.hh: dev/pciconfigall.cc: dev/pciconfigall.hh: dev/tsunami_cchip.cc: dev/tsunami_cchip.hh: dev/tsunami_io.cc: dev/tsunami_io.hh: dev/tsunami_pchip.cc: dev/tsunami_pchip.hh: dev/tsunami_uart.cc: dev/tsunami_uart.hh: Cleaned up includes and changed device from FunctionalMemory to PioDevice for detailed boot dev/ns_gige.cc: The ethernet dev uses two BARs, and the first bars size was being set incorrectly. dev/tsunamireg.h: I don't know why we were using the superpage as the PCI memory addr. Changed and works correctly with detailed boot. --HG-- extra : convert_revision : b535e76612cb90b544305dc1aa8c5e0e774564bd
2004-06-08Updated Copyright with information in bitkeeper changelogsAli Saidi
arch/alpha/alpha_linux_process.cc: arch/alpha/alpha_linux_process.hh: arch/alpha/alpha_memory.cc: arch/alpha/alpha_memory.hh: arch/alpha/alpha_tru64_process.cc: arch/alpha/alpha_tru64_process.hh: arch/alpha/aout_machdep.h: arch/alpha/arguments.cc: arch/alpha/arguments.hh: arch/alpha/faults.cc: arch/alpha/faults.hh: arch/alpha/isa_traits.hh: arch/alpha/osfpal.cc: arch/alpha/osfpal.hh: arch/alpha/pseudo_inst.cc: arch/alpha/pseudo_inst.hh: arch/alpha/vptr.hh: arch/alpha/vtophys.cc: arch/alpha/vtophys.hh: base/bitfield.hh: base/callback.hh: base/circlebuf.cc: base/circlebuf.hh: base/compression/lzss_compression.cc: base/compression/lzss_compression.hh: base/compression/null_compression.hh: base/cprintf.cc: base/cprintf.hh: base/cprintf_formats.hh: base/date.cc: base/dbl_list.hh: base/endian.hh: base/fast_alloc.cc: base/fast_alloc.hh: base/fifo_buffer.cc: base/fifo_buffer.hh: base/hashmap.hh: base/hostinfo.cc: base/hostinfo.hh: base/hybrid_pred.cc: base/hybrid_pred.hh: base/inet.cc: base/inet.hh: base/inifile.cc: base/inifile.hh: base/intmath.cc: base/intmath.hh: base/loader/aout_object.cc: base/loader/aout_object.hh: base/loader/ecoff_object.cc: base/loader/ecoff_object.hh: base/loader/elf_object.cc: base/loader/elf_object.hh: base/loader/object_file.cc: base/loader/object_file.hh: base/loader/symtab.cc: base/loader/symtab.hh: base/misc.cc: base/misc.hh: base/mod_num.hh: base/mysql.cc: base/mysql.hh: base/pollevent.cc: base/pollevent.hh: base/predictor.hh: base/random.cc: base/random.hh: base/range.cc: base/range.hh: base/refcnt.hh: base/remote_gdb.cc: base/remote_gdb.hh: base/res_list.hh: base/sat_counter.cc: base/sat_counter.hh: base/sched_list.hh: base/socket.cc: base/socket.hh: base/statistics.cc: base/statistics.hh: base/stats/events.cc: base/stats/events.hh: base/stats/flags.hh: base/stats/mysql.cc: base/stats/mysql.hh: base/stats/mysql_run.hh: base/stats/output.hh: base/stats/statdb.cc: base/stats/statdb.hh: base/stats/text.cc: base/stats/text.hh: base/stats/types.hh: base/stats/visit.cc: base/stats/visit.hh: base/str.cc: base/str.hh: base/time.cc: base/time.hh: base/trace.cc: base/trace.hh: base/userinfo.cc: base/userinfo.hh: cpu/base_cpu.cc: cpu/base_cpu.hh: cpu/exec_context.cc: cpu/exec_context.hh: cpu/exetrace.cc: cpu/exetrace.hh: cpu/full_cpu/op_class.hh: cpu/full_cpu/smt.hh: cpu/inst_seq.hh: cpu/intr_control.cc: cpu/intr_control.hh: cpu/memtest/memtest.cc: cpu/memtest/memtest.hh: cpu/pc_event.cc: cpu/pc_event.hh: cpu/simple_cpu/simple_cpu.cc: cpu/simple_cpu/simple_cpu.hh: cpu/static_inst.cc: cpu/static_inst.hh: dev/alpha_console.cc: dev/alpha_console.hh: dev/baddev.cc: dev/baddev.hh: dev/disk_image.cc: dev/disk_image.hh: dev/etherbus.cc: dev/etherbus.hh: dev/etherdump.cc: dev/etherdump.hh: dev/etherint.cc: dev/etherint.hh: dev/etherlink.cc: dev/etherlink.hh: dev/etherpkt.cc: dev/etherpkt.hh: dev/ethertap.cc: dev/ethertap.hh: dev/ide_ctrl.cc: dev/ide_ctrl.hh: dev/ide_disk.cc: dev/ide_disk.hh: dev/io_device.cc: dev/io_device.hh: dev/ns_gige.cc: dev/ns_gige.hh: dev/ns_gige_reg.h: dev/pciconfigall.cc: dev/pciconfigall.hh: dev/pcidev.cc: dev/pcidev.hh: dev/pcireg.h: dev/platform.cc: dev/platform.hh: dev/simple_disk.cc: dev/simple_disk.hh: dev/tsunami.cc: dev/tsunami.hh: dev/tsunami_cchip.cc: dev/tsunami_cchip.hh: dev/tsunami_io.cc: dev/tsunami_io.hh: dev/tsunami_pchip.cc: dev/tsunami_pchip.hh: dev/tsunami_uart.hh: dev/tsunamireg.h: docs/stl.hh: kern/linux/linux.hh: kern/linux/linux_syscalls.cc: kern/linux/linux_syscalls.hh: kern/linux/linux_system.cc: kern/linux/linux_system.hh: kern/system_events.cc: kern/system_events.hh: kern/tru64/dump_mbuf.cc: kern/tru64/dump_mbuf.hh: kern/tru64/mbuf.hh: kern/tru64/printf.cc: kern/tru64/printf.hh: kern/tru64/tru64.hh: kern/tru64/tru64_events.cc: kern/tru64/tru64_events.hh: kern/tru64/tru64_syscalls.cc: kern/tru64/tru64_syscalls.hh: kern/tru64/tru64_system.cc: kern/tru64/tru64_system.hh: sim/async.hh: sim/builder.cc: sim/builder.hh: sim/debug.cc: sim/debug.hh: sim/eventq.cc: sim/eventq.hh: sim/host.hh: sim/main.cc: sim/param.cc: sim/param.hh: sim/process.cc: sim/process.hh: sim/serialize.cc: sim/serialize.hh: sim/sim_events.cc: sim/sim_events.hh: sim/sim_exit.hh: sim/sim_object.cc: sim/sim_object.hh: sim/stat_control.cc: sim/stat_control.hh: sim/stats.hh: sim/syscall_emul.cc: sim/syscall_emul.hh: sim/system.cc: sim/system.hh: sim/universe.cc: test/bitvectest.cc: test/circletest.cc: test/cprintftest.cc: test/initest.cc: test/lru_test.cc: test/nmtest.cc: test/offtest.cc: test/paramtest.cc: test/rangetest.cc: test/sized_test.cc: test/stattest.cc: test/strnumtest.cc: test/symtest.cc: test/tokentest.cc: test/tracetest.cc: util/m5/m5.c: util/m5/m5op.h: util/tap/tap.cc: Updated Copyright dev/console.cc: dev/console.hh: This code isn't ours, and shouldn't have our copyright --HG-- extra : convert_revision : 598f2e5eab5d5d3de2c1e862b389086e3212f7c4
2004-06-04Added ctlz and cttz instructions to isa_desc for use in the PAL code.Ali Saidi
--HG-- extra : convert_revision : 74dec35113b795e792b7fc03947a05349a4ff669
2004-06-01Merge saidi@zizzer:/z/m5/Bitkeeper/m5/Ali Saidi
into zeep.eecs.umich.edu:/z/saidi/work/m5 --HG-- extra : convert_revision : 89e0bdd427b23a8f52b8ba53b18451df7be22f14
2004-05-31Renamed OpClass enum members: they all end in 'Op' now.Steve Reinhardt
Got rid of two inconsistent sets of strings that corresponded to this enum, and replaced with a single set that clearly matches the enum names. arch/alpha/isa_desc: arch/isa_parser.py: cpu/full_cpu/op_class.hh: Renamed OpClass enum members. --HG-- extra : convert_revision : bf596f7568a20b2e77c07ac349f253135141aef4
2004-05-31Merged head into linux treeAli Saidi
base/stats/mysql.hh: Rename of Statsistics namespace to stats... merge from head --HG-- extra : convert_revision : a5a7f6268b35e75fba1b1800a74fcd6dbd09d974
2004-05-28Updated FastCPU model with all the recent changes.Kevin Lim
arch/alpha/ev5.cc: Updated to support new forms of setIntReg and setFloatRegDouble. Will need to be cleaned up in the future. arch/isa_parser.py: Added in FastCPU model. --HG-- extra : convert_revision : 384a27efcb50729ea6c3cc11653f395c300e48db
2004-05-28Merged in new FastCPU stuff with existing code.Kevin Lim
arch/alpha/ev5.cc: Added templatized processInterrupts() function that can be used by all of the CPU models. arch/alpha/isa_desc: Merged in changes to remove CPU dependence. arch/isa_parser.py: Merged in changes. cpu/static_inst.hh: Includes FastCPU execute methods. --HG-- extra : convert_revision : fcaa1dca35a9b316c73982bec8680df564f50bd8
2004-05-27FastCPU model added. It's very similar to the SimpleCPU, just without a lot ↵Kevin Lim
of the stats tracking. Also various changes to make the CPU model less ISA dependent, which includes moving the code that checks for interrupts up to the ISA level, moving code that zeroes the zero registers up to the ISA level, and removing opcode and ra from the regfile. arch/alpha/alpha_memory.cc: The regfile has been changed so it no longer has the opcode and ra. Instead the xc holds the actual instruction, and from there the opcode and ra can be obtained with OPCODE() and RA(). arch/alpha/ev5.cc: Moved code that once existed within simpleCPU to ev5, and templatized it. This way the CPU models can call processInterrupts and the ISA specific interrupt handling is left to the ISA's code. Also moved ISA specific zero registers from simpleCPU to here. arch/alpha/ev5.hh: Added macros for obtaining the opcode and ra from the instruction itself, as there is no longer opcode or ra in the regfile. arch/alpha/isa_desc: Added in declarations for the FastCPU model. arch/alpha/isa_traits.hh: Removed opcode and ra from the regfile. The xc now holds the actual instruction, and the opcode and ra can be obtained through it. Also added the declaration for the templated zeroRegisters() function, which will set the zero registers to 0. arch/isa_parser.py: Added in FastCPUExecContext so it will generate code for the FastCPU model as well. cpu/exec_context.cc: Added in a more generic trap function so "ev5_trap" doesn't need to be called. It currently still calls the old method, with plans for making this ISA dependent in the future. cpu/exec_context.hh: Exec context now has the instruction within it. Also added methods for exec context to read an instruction from memory, return the current instruction, and set the instruction if needed. Also has declaration for more generic trap() function. cpu/simple_cpu/simple_cpu.cc: Removed references to opcode and ra, and instead sets the xc's instruction with the fetched instruction. cpu/static_inst.hh: Added declaration for execute() using FastCPUExecContext. --HG-- extra : convert_revision : 0441ea3700ac50b733e485395d4dd4ac83666f92
2004-05-21add a few statistics eventsNathan Binkert
arch/alpha/ev5.cc: Add an event for faults cpu/simple_cpu/simple_cpu.cc: add events for uncached reads/writes --HG-- extra : convert_revision : 747bdf12761e2de6ebbf54fecc9e0b71915b3a02
2004-05-21rename namespace Statistics to StatsNathan Binkert
--HG-- extra : convert_revision : 28f1703f8d7d8cf33fb952ae450f66bdba860fb7
2004-05-21Change the namespace Statistics to StatsNathan Binkert
--HG-- extra : convert_revision : 3084b292bbe2e8a392af8e99a31763ca0b0a9467
2004-05-19Remove the uncacheable bit 39 check (needs to be merged in with head treeAndrew Schultz
if Tru64 is to continue to be supported on Turbolaser) and fixed translation of physical addresses by clearing PA<42:35> when the real uncachable bit (43) is set arch/alpha/ev5.hh: Change to support 256 ASNs and seperate VA_SPACE checks for EV5 and EV6 also add support proper translation of uncacheable physical addresses dev/ide_ctrl.cc: Fix to work with real address translation --HG-- extra : convert_revision : aa3d1c284b8271d4763a8da2509c91bbcf83189a
2004-05-18Replace explicit xc->misspeculating() tests in execute() methodsSteve Reinhardt
with an IsNonSpeculative flag. No effect on results of non-full-system or SimpleCPU. Very small impact on full-system FullCPU runs since old wrong-path call_pal insts used to change the PC, where now they're treated as no-ops. arch/alpha/isa_desc: Get rid of xc->misspeculating() checks, use IsNonSpeculative flag instead. cpu/static_inst.hh: Add IsNonSpeculative flag and isNonSpeculative() method to test it. --HG-- extra : convert_revision : 7ec536bfc28b905c429c09eb920ed73ef2beeeba
2004-05-18merge m5 with linux for the event and binning liftingLisa Hsu
--HG-- extra : convert_revision : 09d3678746c2e9a93a9982dc75d5e1ac309cb2fa
2004-05-17Significant changes to ISA description to completely factorSteve Reinhardt
out CPU model. ISA description now generates multiple output source files to (in theory) reduce compilation time. arch/alpha/isa_desc: Update for parser changes. Move most constructors out of class declarations (which are now in decoder.hh) and into decoder.cc. Move all execute() methods into exec output. arch/isa_parser.py: Significant changes to make ISA description completely independent of CPU model, and isolate model-dependent parts of parser into one little class (CpuModel). Also split up code output into multiple files (a header, a main source file, and per-cpu execute() method files). Noticeable changes to language as a result. See updated Doxygen documentation. cpu/simple_cpu/simple_cpu.hh: SimpleCPUExecContext typedef no longer needed. Add forward declaration of Process. cpu/static_inst.hh: SimpleCPUExecContext and FullCPUExecContext typedefs no longer needed. Make eaCompInst() and memAccInst() return const refs. --HG-- extra : convert_revision : 71471f267804fafd0a881bac7445677e76334daf
2004-05-13Add VPtr class that makes it possible to esentially createNathan Binkert
a pointer to an object that lives inside simulated memory. Useful for doing a bit of analysis of what's going on in the running kernel. --HG-- extra : convert_revision : d78089cce5ec4334483a710ba512eaf18d9b0319
2004-05-13remove the annotation junkNathan Binkert
arch/alpha/isa_desc: remove the annotation junk Move some code to AlphaPseudo where it belongs arch/alpha/pseudo_inst.cc: arch/alpha/pseudo_inst.hh: remove the annotation junk add pseudo instruction code that was previously misplaced --HG-- extra : convert_revision : 97db8402aa34e0bdf044b138c52331fc9e714986
2004-05-13pass the address of both the old an new pcbb on contextNathan Binkert
switches. (Makes other uncommitted code easier to merge.) arch/alpha/ev5.cc: pass the address of both the old an new pcbb on context switches --HG-- extra : convert_revision : bff8c8d1b532ad5f9af6270169bbfb1b5c05256a
2004-05-11successful merge, linux still builds and runs as far it used to, network ↵Lisa Hsu
device still transmit ARP packet. arch/alpha/alpha_memory.cc: change to the main m5 tree convention for naming base/traceflags.py: add ide and pciconfigall traceflags kern/linux/linux_system.cc: kern/linux/linux_system.hh: kill some old binning styled stuff --HG-- extra : convert_revision : 0558878906817975a714b1c7c08f9ee405468535
2004-05-11first pass at merging m5 with linuxLisa Hsu
--HG-- extra : convert_revision : dfe23349b80ae3b34d3cb95c5734e01ef62f700e
2004-05-10Do a better job of factoring out CPU model in ISA description.Steve Reinhardt
(Still not perfect though.) arch/alpha/isa_desc: Do a better job of factoring out CPU model. (Still not perfect though.) Pull execute() methods out of class declarations into separate section of file, allowing (1) easier replication for different CPU models and (2) a path to putting them all in a separate file. Force all instruction execution context into a single model-dependent class (SimpleCPU itself for SimpleCPU, DynInst for FullCPU). arch/isa_parser.py: Do a better job of factoring out CPU model. (Still not perfect though.) Pull execute() methods out of class declarations into separate section of file, allowing (1) easier replication for different CPU models and (2) a path to putting them all in a separate file. Also restructure top level to allow parser to run under interactive interpreter session for easier debugging. cpu/exec_context.hh: Add a few new methods to clean up isa_desc. cpu/simple_cpu/simple_cpu.cc: cpu/static_inst.hh: StaticInst::execute no longer takes a CPU and an ExecContext, just a unified FooCPUExecContext. cpu/simple_cpu/simple_cpu.hh: Add methods to redirect calls to ExecContext so SimpleCPU can act as sole instruction execution context for itself. Typedef SimpleCPU to SimpleCPUExecContext. --HG-- extra : convert_revision : ecc445503bc585585da5663fe61796580e744da6
2004-05-09Added ULL for 64bit intsAli Saidi
Added function to skip determine_cpu_caches(). We may have to update this in the future: see note below. arch/alpha/alpha_memory.cc: dev/ide_ctrl.cc: dev/tsunamireg.h: Added ULL for 64bit ints kern/linux/linux_system.cc: Added a function to skip determine_cpu_caches, right now it is only used for printing in proc, however in the future we may either want to implement the SC_CTL IPR register or manually set alpha_l1i_cacheshape, alpha_l1d_cacheshape, alpha_l2_cacheshape, alpha_l3_cacheshape to ((size << 10) | (linesize>>1)<<4 | way) kern/linux/linux_system.hh: added event to skip determine_cpu_caches() --HG-- extra : convert_revision : 1065f2091bbe6832b730af490f5b4672c2afedce