| Age | Commit message (Collapse) | Author |
|---|
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- simulator source now in 'src' subdirectory
- imported files from 'ext' repository
- support building in arbitrary places, including
outside of the source tree. See comment at top
of SConstruct file for more details.
Regression tests are temporarily disabled; that
syetem needs more extensive revisions.
SConstruct:
Update for new directory structure.
Modify to support build trees that are not subdirectories
of the source tree. See comment at top of file for
more details.
Regression tests are temporarily disabled.
src/arch/SConscript:
src/arch/isa_parser.py:
src/python/SConscript:
Update for new directory structure.
--HG--
rename : build/SConstruct => SConstruct
rename : build/default_options/ALPHA_FS => build_opts/ALPHA_FS
rename : build/default_options/ALPHA_FS_TL => build_opts/ALPHA_FS_TL
rename : build/default_options/ALPHA_SE => build_opts/ALPHA_SE
rename : build/default_options/MIPS_SE => build_opts/MIPS_SE
rename : build/default_options/SPARC_SE => build_opts/SPARC_SE
rename : Doxyfile => src/Doxyfile
rename : SConscript => src/SConscript
rename : arch/SConscript => src/arch/SConscript
rename : arch/alpha/SConscript => src/arch/alpha/SConscript
rename : arch/alpha/aout_machdep.h => src/arch/alpha/aout_machdep.h
rename : arch/alpha/arguments.cc => src/arch/alpha/arguments.cc
rename : arch/alpha/arguments.hh => src/arch/alpha/arguments.hh
rename : arch/alpha/ecoff_machdep.h => src/arch/alpha/ecoff_machdep.h
rename : arch/alpha/ev5.cc => src/arch/alpha/ev5.cc
rename : arch/alpha/ev5.hh => src/arch/alpha/ev5.hh
rename : arch/alpha/faults.cc => src/arch/alpha/faults.cc
rename : arch/alpha/faults.hh => src/arch/alpha/faults.hh
rename : arch/alpha/freebsd/system.cc => src/arch/alpha/freebsd/system.cc
rename : arch/alpha/freebsd/system.hh => src/arch/alpha/freebsd/system.hh
rename : arch/alpha/isa/branch.isa => src/arch/alpha/isa/branch.isa
rename : arch/alpha/isa/decoder.isa => src/arch/alpha/isa/decoder.isa
rename : arch/alpha/isa/fp.isa => src/arch/alpha/isa/fp.isa
rename : arch/alpha/isa/int.isa => src/arch/alpha/isa/int.isa
rename : arch/alpha/isa/main.isa => src/arch/alpha/isa/main.isa
rename : arch/alpha/isa/mem.isa => src/arch/alpha/isa/mem.isa
rename : arch/alpha/isa/opcdec.isa => src/arch/alpha/isa/opcdec.isa
rename : arch/alpha/isa/pal.isa => src/arch/alpha/isa/pal.isa
rename : arch/alpha/isa/unimp.isa => src/arch/alpha/isa/unimp.isa
rename : arch/alpha/isa/unknown.isa => src/arch/alpha/isa/unknown.isa
rename : arch/alpha/isa/util.isa => src/arch/alpha/isa/util.isa
rename : arch/alpha/isa_traits.hh => src/arch/alpha/isa_traits.hh
rename : arch/alpha/linux/aligned.hh => src/arch/alpha/linux/aligned.hh
rename : arch/alpha/linux/hwrpb.hh => src/arch/alpha/linux/hwrpb.hh
rename : arch/alpha/linux/linux.cc => src/arch/alpha/linux/linux.cc
rename : arch/alpha/linux/linux.hh => src/arch/alpha/linux/linux.hh
rename : arch/alpha/linux/process.cc => src/arch/alpha/linux/process.cc
rename : arch/alpha/linux/process.hh => src/arch/alpha/linux/process.hh
rename : arch/alpha/linux/system.cc => src/arch/alpha/linux/system.cc
rename : arch/alpha/linux/system.hh => src/arch/alpha/linux/system.hh
rename : arch/alpha/linux/thread_info.hh => src/arch/alpha/linux/thread_info.hh
rename : arch/alpha/linux/threadinfo.hh => src/arch/alpha/linux/threadinfo.hh
rename : arch/alpha/osfpal.cc => src/arch/alpha/osfpal.cc
rename : arch/alpha/osfpal.hh => src/arch/alpha/osfpal.hh
rename : arch/alpha/process.cc => src/arch/alpha/process.cc
rename : arch/alpha/process.hh => src/arch/alpha/process.hh
rename : arch/alpha/regfile.hh => src/arch/alpha/regfile.hh
rename : arch/alpha/stacktrace.cc => src/arch/alpha/stacktrace.cc
rename : arch/alpha/stacktrace.hh => src/arch/alpha/stacktrace.hh
rename : arch/alpha/system.cc => src/arch/alpha/system.cc
rename : arch/alpha/system.hh => src/arch/alpha/system.hh
rename : arch/alpha/tlb.cc => src/arch/alpha/tlb.cc
rename : arch/alpha/tlb.hh => src/arch/alpha/tlb.hh
rename : arch/alpha/tru64/process.cc => src/arch/alpha/tru64/process.cc
rename : arch/alpha/tru64/process.hh => src/arch/alpha/tru64/process.hh
rename : arch/alpha/tru64/system.cc => src/arch/alpha/tru64/system.cc
rename : arch/alpha/tru64/system.hh => src/arch/alpha/tru64/system.hh
rename : arch/alpha/tru64/tru64.cc => src/arch/alpha/tru64/tru64.cc
rename : arch/alpha/tru64/tru64.hh => src/arch/alpha/tru64/tru64.hh
rename : arch/alpha/types.hh => src/arch/alpha/types.hh
rename : arch/alpha/utility.hh => src/arch/alpha/utility.hh
rename : arch/alpha/vtophys.cc => src/arch/alpha/vtophys.cc
rename : arch/alpha/vtophys.hh => src/arch/alpha/vtophys.hh
rename : arch/isa_parser.py => src/arch/isa_parser.py
rename : arch/isa_specific.hh => src/arch/isa_specific.hh
rename : arch/mips/SConscript => src/arch/mips/SConscript
rename : arch/mips/faults.cc => src/arch/mips/faults.cc
rename : arch/mips/faults.hh => src/arch/mips/faults.hh
rename : arch/mips/isa/base.isa => src/arch/mips/isa/base.isa
rename : arch/mips/isa/bitfields.isa => src/arch/mips/isa/bitfields.isa
rename : arch/mips/isa/decoder.isa => src/arch/mips/isa/decoder.isa
rename : arch/mips/isa/formats/basic.isa => src/arch/mips/isa/formats/basic.isa
rename : arch/mips/isa/formats/branch.isa => src/arch/mips/isa/formats/branch.isa
rename : arch/mips/isa/formats/formats.isa => src/arch/mips/isa/formats/formats.isa
rename : arch/mips/isa/formats/fp.isa => src/arch/mips/isa/formats/fp.isa
rename : arch/mips/isa/formats/int.isa => src/arch/mips/isa/formats/int.isa
rename : arch/mips/isa/formats/mem.isa => src/arch/mips/isa/formats/mem.isa
rename : arch/mips/isa/formats/noop.isa => src/arch/mips/isa/formats/noop.isa
rename : arch/mips/isa/formats/tlbop.isa => src/arch/mips/isa/formats/tlbop.isa
rename : arch/mips/isa/formats/trap.isa => src/arch/mips/isa/formats/trap.isa
rename : arch/mips/isa/formats/unimp.isa => src/arch/mips/isa/formats/unimp.isa
rename : arch/mips/isa/formats/unknown.isa => src/arch/mips/isa/formats/unknown.isa
rename : arch/mips/isa/formats/util.isa => src/arch/mips/isa/formats/util.isa
rename : arch/mips/isa/includes.isa => src/arch/mips/isa/includes.isa
rename : arch/mips/isa/main.isa => src/arch/mips/isa/main.isa
rename : arch/mips/isa/operands.isa => src/arch/mips/isa/operands.isa
rename : arch/mips/isa_traits.cc => src/arch/mips/isa_traits.cc
rename : arch/mips/isa_traits.hh => src/arch/mips/isa_traits.hh
rename : arch/mips/linux/linux.cc => src/arch/mips/linux/linux.cc
rename : arch/mips/linux/linux.hh => src/arch/mips/linux/linux.hh
rename : arch/mips/linux/process.cc => src/arch/mips/linux/process.cc
rename : arch/mips/linux/process.hh => src/arch/mips/linux/process.hh
rename : arch/mips/process.cc => src/arch/mips/process.cc
rename : arch/mips/process.hh => src/arch/mips/process.hh
rename : arch/mips/regfile/float_regfile.hh => src/arch/mips/regfile/float_regfile.hh
rename : arch/mips/regfile/int_regfile.hh => src/arch/mips/regfile/int_regfile.hh
rename : arch/mips/regfile/misc_regfile.hh => src/arch/mips/regfile/misc_regfile.hh
rename : arch/mips/regfile/regfile.hh => src/arch/mips/regfile/regfile.hh
rename : arch/mips/stacktrace.hh => src/arch/mips/stacktrace.hh
rename : arch/mips/types.hh => src/arch/mips/types.hh
rename : arch/mips/utility.hh => src/arch/mips/utility.hh
rename : arch/sparc/SConscript => src/arch/sparc/SConscript
rename : arch/sparc/faults.cc => src/arch/sparc/faults.cc
rename : arch/sparc/faults.hh => src/arch/sparc/faults.hh
rename : arch/sparc/isa/base.isa => src/arch/sparc/isa/base.isa
rename : arch/sparc/isa/bitfields.isa => src/arch/sparc/isa/bitfields.isa
rename : arch/sparc/isa/decoder.isa => src/arch/sparc/isa/decoder.isa
rename : arch/sparc/isa/formats.isa => src/arch/sparc/isa/formats.isa
rename : arch/sparc/isa/formats/basic.isa => src/arch/sparc/isa/formats/basic.isa
rename : arch/sparc/isa/formats/branch.isa => src/arch/sparc/isa/formats/branch.isa
rename : arch/sparc/isa/formats/integerop.isa => src/arch/sparc/isa/formats/integerop.isa
rename : arch/sparc/isa/formats/mem.isa => src/arch/sparc/isa/formats/mem.isa
rename : arch/sparc/isa/formats/nop.isa => src/arch/sparc/isa/formats/nop.isa
rename : arch/sparc/isa/formats/priv.isa => src/arch/sparc/isa/formats/priv.isa
rename : arch/sparc/isa/formats/trap.isa => src/arch/sparc/isa/formats/trap.isa
rename : arch/sparc/isa/formats/unknown.isa => src/arch/sparc/isa/formats/unknown.isa
rename : arch/sparc/isa/includes.isa => src/arch/sparc/isa/includes.isa
rename : arch/sparc/isa/main.isa => src/arch/sparc/isa/main.isa
rename : arch/sparc/isa/operands.isa => src/arch/sparc/isa/operands.isa
rename : arch/sparc/isa_traits.hh => src/arch/sparc/isa_traits.hh
rename : arch/sparc/linux/linux.cc => src/arch/sparc/linux/linux.cc
rename : arch/sparc/linux/linux.hh => src/arch/sparc/linux/linux.hh
rename : arch/sparc/linux/process.cc => src/arch/sparc/linux/process.cc
rename : arch/sparc/linux/process.hh => src/arch/sparc/linux/process.hh
rename : arch/sparc/process.cc => src/arch/sparc/process.cc
rename : arch/sparc/process.hh => src/arch/sparc/process.hh
rename : arch/sparc/regfile.hh => src/arch/sparc/regfile.hh
rename : arch/sparc/solaris/process.cc => src/arch/sparc/solaris/process.cc
rename : arch/sparc/solaris/process.hh => src/arch/sparc/solaris/process.hh
rename : arch/sparc/solaris/solaris.cc => src/arch/sparc/solaris/solaris.cc
rename : arch/sparc/solaris/solaris.hh => src/arch/sparc/solaris/solaris.hh
rename : arch/sparc/stacktrace.hh => src/arch/sparc/stacktrace.hh
rename : arch/sparc/system.cc => src/arch/sparc/system.cc
rename : arch/sparc/system.hh => src/arch/sparc/system.hh
rename : arch/sparc/utility.hh => src/arch/sparc/utility.hh
rename : base/bitfield.hh => src/base/bitfield.hh
rename : base/callback.hh => src/base/callback.hh
rename : base/chunk_generator.hh => src/base/chunk_generator.hh
rename : base/circlebuf.cc => src/base/circlebuf.cc
rename : base/circlebuf.hh => src/base/circlebuf.hh
rename : base/compression/lzss_compression.cc => src/base/compression/lzss_compression.cc
rename : base/compression/lzss_compression.hh => src/base/compression/lzss_compression.hh
rename : base/compression/null_compression.hh => src/base/compression/null_compression.hh
rename : base/cprintf.cc => src/base/cprintf.cc
rename : base/cprintf.hh => src/base/cprintf.hh
rename : base/cprintf_formats.hh => src/base/cprintf_formats.hh
rename : base/crc.cc => src/base/crc.cc
rename : base/crc.hh => src/base/crc.hh
rename : base/date.cc => src/base/date.cc
rename : base/dbl_list.hh => src/base/dbl_list.hh
rename : base/endian.hh => src/base/endian.hh
rename : base/fast_alloc.cc => src/base/fast_alloc.cc
rename : base/fast_alloc.hh => src/base/fast_alloc.hh
rename : base/fenv.hh => src/base/fenv.hh
rename : base/fifo_buffer.cc => src/base/fifo_buffer.cc
rename : base/fifo_buffer.hh => src/base/fifo_buffer.hh
rename : base/hashmap.hh => src/base/hashmap.hh
rename : base/hostinfo.cc => src/base/hostinfo.cc
rename : base/hostinfo.hh => src/base/hostinfo.hh
rename : base/hybrid_pred.cc => src/base/hybrid_pred.cc
rename : base/hybrid_pred.hh => src/base/hybrid_pred.hh
rename : base/inet.cc => src/base/inet.cc
rename : base/inet.hh => src/base/inet.hh
rename : base/inifile.cc => src/base/inifile.cc
rename : base/inifile.hh => src/base/inifile.hh
rename : base/intmath.cc => src/base/intmath.cc
rename : base/intmath.hh => src/base/intmath.hh
rename : base/kgdb.h => src/base/kgdb.h
rename : base/loader/aout_object.cc => src/base/loader/aout_object.cc
rename : base/loader/aout_object.hh => src/base/loader/aout_object.hh
rename : base/loader/coff_sym.h => src/base/loader/coff_sym.h
rename : base/loader/coff_symconst.h => src/base/loader/coff_symconst.h
rename : base/loader/ecoff_object.cc => src/base/loader/ecoff_object.cc
rename : base/loader/ecoff_object.hh => src/base/loader/ecoff_object.hh
rename : base/loader/elf_object.cc => src/base/loader/elf_object.cc
rename : base/loader/elf_object.hh => src/base/loader/elf_object.hh
rename : base/loader/exec_aout.h => src/base/loader/exec_aout.h
rename : base/loader/exec_ecoff.h => src/base/loader/exec_ecoff.h
rename : base/loader/object_file.cc => src/base/loader/object_file.cc
rename : base/loader/object_file.hh => src/base/loader/object_file.hh
rename : base/loader/symtab.cc => src/base/loader/symtab.cc
rename : base/loader/symtab.hh => src/base/loader/symtab.hh
rename : base/match.cc => src/base/match.cc
rename : base/match.hh => src/base/match.hh
rename : base/misc.cc => src/base/misc.cc
rename : base/misc.hh => src/base/misc.hh
rename : base/mod_num.hh => src/base/mod_num.hh
rename : base/mysql.cc => src/base/mysql.cc
rename : base/mysql.hh => src/base/mysql.hh
rename : base/output.cc => src/base/output.cc
rename : base/output.hh => src/base/output.hh
rename : base/pollevent.cc => src/base/pollevent.cc
rename : base/pollevent.hh => src/base/pollevent.hh
rename : base/predictor.hh => src/base/predictor.hh
rename : base/random.cc => src/base/random.cc
rename : base/random.hh => src/base/random.hh
rename : base/range.cc => src/base/range.cc
rename : base/range.hh => src/base/range.hh
rename : base/refcnt.hh => src/base/refcnt.hh
rename : base/remote_gdb.cc => src/base/remote_gdb.cc
rename : base/remote_gdb.hh => src/base/remote_gdb.hh
rename : base/res_list.hh => src/base/res_list.hh
rename : base/sat_counter.cc => src/base/sat_counter.cc
rename : base/sat_counter.hh => src/base/sat_counter.hh
rename : base/sched_list.hh => src/base/sched_list.hh
rename : base/socket.cc => src/base/socket.cc
rename : base/socket.hh => src/base/socket.hh
rename : base/statistics.cc => src/base/statistics.cc
rename : base/statistics.hh => src/base/statistics.hh
rename : base/stats/events.cc => src/base/stats/events.cc
rename : base/stats/events.hh => src/base/stats/events.hh
rename : base/stats/flags.hh => src/base/stats/flags.hh
rename : base/stats/mysql.cc => src/base/stats/mysql.cc
rename : base/stats/mysql.hh => src/base/stats/mysql.hh
rename : base/stats/mysql_run.hh => src/base/stats/mysql_run.hh
rename : base/stats/output.hh => src/base/stats/output.hh
rename : base/stats/statdb.cc => src/base/stats/statdb.cc
rename : base/stats/statdb.hh => src/base/stats/statdb.hh
rename : base/stats/text.cc => src/base/stats/text.cc
rename : base/stats/text.hh => src/base/stats/text.hh
rename : base/stats/types.hh => src/base/stats/types.hh
rename : base/stats/visit.cc => src/base/stats/visit.cc
rename : base/stats/visit.hh => src/base/stats/visit.hh
rename : base/str.cc => src/base/str.cc
rename : base/str.hh => src/base/str.hh
rename : base/time.cc => src/base/time.cc
rename : base/time.hh => src/base/time.hh
rename : base/timebuf.hh => src/base/timebuf.hh
rename : base/trace.cc => src/base/trace.cc
rename : base/trace.hh => src/base/trace.hh
rename : base/traceflags.py => src/base/traceflags.py
rename : base/userinfo.cc => src/base/userinfo.cc
rename : base/userinfo.hh => src/base/userinfo.hh
rename : cpu/SConscript => src/cpu/SConscript
rename : cpu/base.cc => src/cpu/base.cc
rename : cpu/base.hh => src/cpu/base.hh
rename : cpu/base_dyn_inst.cc => src/cpu/base_dyn_inst.cc
rename : cpu/base_dyn_inst.hh => src/cpu/base_dyn_inst.hh
rename : cpu/cpu_exec_context.cc => src/cpu/cpu_exec_context.cc
rename : cpu/cpu_exec_context.hh => src/cpu/cpu_exec_context.hh
rename : cpu/cpu_models.py => src/cpu/cpu_models.py
rename : cpu/exec_context.hh => src/cpu/exec_context.hh
rename : cpu/exetrace.cc => src/cpu/exetrace.cc
rename : cpu/exetrace.hh => src/cpu/exetrace.hh
rename : cpu/inst_seq.hh => src/cpu/inst_seq.hh
rename : cpu/intr_control.cc => src/cpu/intr_control.cc
rename : cpu/intr_control.hh => src/cpu/intr_control.hh
rename : cpu/memtest/memtest.cc => src/cpu/memtest/memtest.cc
rename : cpu/memtest/memtest.hh => src/cpu/memtest/memtest.hh
rename : cpu/o3/2bit_local_pred.cc => src/cpu/o3/2bit_local_pred.cc
rename : cpu/o3/2bit_local_pred.hh => src/cpu/o3/2bit_local_pred.hh
rename : cpu/o3/alpha_cpu.cc => src/cpu/o3/alpha_cpu.cc
rename : cpu/o3/alpha_cpu.hh => src/cpu/o3/alpha_cpu.hh
rename : cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha_cpu_builder.cc
rename : cpu/o3/alpha_cpu_impl.hh => src/cpu/o3/alpha_cpu_impl.hh
rename : cpu/o3/alpha_dyn_inst.cc => src/cpu/o3/alpha_dyn_inst.cc
rename : cpu/o3/alpha_dyn_inst.hh => src/cpu/o3/alpha_dyn_inst.hh
rename : cpu/o3/alpha_dyn_inst_impl.hh => src/cpu/o3/alpha_dyn_inst_impl.hh
rename : cpu/o3/alpha_impl.hh => src/cpu/o3/alpha_impl.hh
rename : cpu/o3/alpha_params.hh => src/cpu/o3/alpha_params.hh
rename : cpu/o3/bpred_unit.cc => src/cpu/o3/bpred_unit.cc
rename : cpu/o3/bpred_unit.hh => src/cpu/o3/bpred_unit.hh
rename : cpu/o3/bpred_unit_impl.hh => src/cpu/o3/bpred_unit_impl.hh
rename : cpu/o3/btb.cc => src/cpu/o3/btb.cc
rename : cpu/o3/btb.hh => src/cpu/o3/btb.hh
rename : cpu/o3/comm.hh => src/cpu/o3/comm.hh
rename : cpu/o3/commit.cc => src/cpu/o3/commit.cc
rename : cpu/o3/commit.hh => src/cpu/o3/commit.hh
rename : cpu/o3/commit_impl.hh => src/cpu/o3/commit_impl.hh
rename : cpu/o3/cpu.cc => src/cpu/o3/cpu.cc
rename : cpu/o3/cpu.hh => src/cpu/o3/cpu.hh
rename : cpu/o3/cpu_policy.hh => src/cpu/o3/cpu_policy.hh
rename : cpu/o3/decode.cc => src/cpu/o3/decode.cc
rename : cpu/o3/decode.hh => src/cpu/o3/decode.hh
rename : cpu/o3/decode_impl.hh => src/cpu/o3/decode_impl.hh
rename : cpu/o3/fetch.cc => src/cpu/o3/fetch.cc
rename : cpu/o3/fetch.hh => src/cpu/o3/fetch.hh
rename : cpu/o3/fetch_impl.hh => src/cpu/o3/fetch_impl.hh
rename : cpu/o3/free_list.cc => src/cpu/o3/free_list.cc
rename : cpu/o3/free_list.hh => src/cpu/o3/free_list.hh
rename : cpu/o3/iew.cc => src/cpu/o3/iew.cc
rename : cpu/o3/iew.hh => src/cpu/o3/iew.hh
rename : cpu/o3/iew_impl.hh => src/cpu/o3/iew_impl.hh
rename : cpu/o3/inst_queue.cc => src/cpu/o3/inst_queue.cc
rename : cpu/o3/inst_queue.hh => src/cpu/o3/inst_queue.hh
rename : cpu/o3/inst_queue_impl.hh => src/cpu/o3/inst_queue_impl.hh
rename : cpu/o3/mem_dep_unit.cc => src/cpu/o3/mem_dep_unit.cc
rename : cpu/o3/mem_dep_unit.hh => src/cpu/o3/mem_dep_unit.hh
rename : cpu/o3/mem_dep_unit_impl.hh => src/cpu/o3/mem_dep_unit_impl.hh
rename : cpu/o3/ras.cc => src/cpu/o3/ras.cc
rename : cpu/o3/ras.hh => src/cpu/o3/ras.hh
rename : cpu/o3/regfile.hh => src/cpu/o3/regfile.hh
rename : cpu/o3/rename.cc => src/cpu/o3/rename.cc
rename : cpu/o3/rename.hh => src/cpu/o3/rename.hh
rename : cpu/o3/rename_impl.hh => src/cpu/o3/rename_impl.hh
rename : cpu/o3/rename_map.cc => src/cpu/o3/rename_map.cc
rename : cpu/o3/rename_map.hh => src/cpu/o3/rename_map.hh
rename : cpu/o3/rob.cc => src/cpu/o3/rob.cc
rename : cpu/o3/rob.hh => src/cpu/o3/rob.hh
rename : cpu/o3/rob_impl.hh => src/cpu/o3/rob_impl.hh
rename : cpu/o3/sat_counter.cc => src/cpu/o3/sat_counter.cc
rename : cpu/o3/sat_counter.hh => src/cpu/o3/sat_counter.hh
rename : cpu/o3/store_set.cc => src/cpu/o3/store_set.cc
rename : cpu/o3/store_set.hh => src/cpu/o3/store_set.hh
rename : cpu/o3/tournament_pred.cc => src/cpu/o3/tournament_pred.cc
rename : cpu/o3/tournament_pred.hh => src/cpu/o3/tournament_pred.hh
rename : cpu/op_class.cc => src/cpu/op_class.cc
rename : cpu/op_class.hh => src/cpu/op_class.hh
rename : cpu/ozone/cpu.cc => src/cpu/ozone/cpu.cc
rename : cpu/ozone/cpu.hh => src/cpu/ozone/cpu.hh
rename : cpu/ozone/cpu_impl.hh => src/cpu/ozone/cpu_impl.hh
rename : cpu/ozone/ea_list.cc => src/cpu/ozone/ea_list.cc
rename : cpu/ozone/ea_list.hh => src/cpu/ozone/ea_list.hh
rename : cpu/pc_event.cc => src/cpu/pc_event.cc
rename : cpu/pc_event.hh => src/cpu/pc_event.hh
rename : cpu/profile.cc => src/cpu/profile.cc
rename : cpu/profile.hh => src/cpu/profile.hh
rename : cpu/simple/atomic.cc => src/cpu/simple/atomic.cc
rename : cpu/simple/atomic.hh => src/cpu/simple/atomic.hh
rename : cpu/simple/base.cc => src/cpu/simple/base.cc
rename : cpu/simple/base.hh => src/cpu/simple/base.hh
rename : cpu/simple/timing.cc => src/cpu/simple/timing.cc
rename : cpu/simple/timing.hh => src/cpu/simple/timing.hh
rename : cpu/smt.hh => src/cpu/smt.hh
rename : cpu/static_inst.cc => src/cpu/static_inst.cc
rename : cpu/static_inst.hh => src/cpu/static_inst.hh
rename : cpu/trace/opt_cpu.cc => src/cpu/trace/opt_cpu.cc
rename : cpu/trace/opt_cpu.hh => src/cpu/trace/opt_cpu.hh
rename : cpu/trace/reader/ibm_reader.cc => src/cpu/trace/reader/ibm_reader.cc
rename : cpu/trace/reader/ibm_reader.hh => src/cpu/trace/reader/ibm_reader.hh
rename : cpu/trace/reader/itx_reader.cc => src/cpu/trace/reader/itx_reader.cc
rename : cpu/trace/reader/itx_reader.hh => src/cpu/trace/reader/itx_reader.hh
rename : cpu/trace/reader/m5_reader.cc => src/cpu/trace/reader/m5_reader.cc
rename : cpu/trace/reader/m5_reader.hh => src/cpu/trace/reader/m5_reader.hh
rename : cpu/trace/reader/mem_trace_reader.cc => src/cpu/trace/reader/mem_trace_reader.cc
rename : cpu/trace/reader/mem_trace_reader.hh => src/cpu/trace/reader/mem_trace_reader.hh
rename : cpu/trace/trace_cpu.cc => src/cpu/trace/trace_cpu.cc
rename : cpu/trace/trace_cpu.hh => src/cpu/trace/trace_cpu.hh
rename : dev/alpha_access.h => src/dev/alpha_access.h
rename : dev/alpha_console.cc => src/dev/alpha_console.cc
rename : dev/alpha_console.hh => src/dev/alpha_console.hh
rename : dev/baddev.cc => src/dev/baddev.cc
rename : dev/baddev.hh => src/dev/baddev.hh
rename : dev/disk_image.cc => src/dev/disk_image.cc
rename : dev/disk_image.hh => src/dev/disk_image.hh
rename : dev/etherbus.cc => src/dev/etherbus.cc
rename : dev/etherbus.hh => src/dev/etherbus.hh
rename : dev/etherdump.cc => src/dev/etherdump.cc
rename : dev/etherdump.hh => src/dev/etherdump.hh
rename : dev/etherint.cc => src/dev/etherint.cc
rename : dev/etherint.hh => src/dev/etherint.hh
rename : dev/etherlink.cc => src/dev/etherlink.cc
rename : dev/etherlink.hh => src/dev/etherlink.hh
rename : dev/etherpkt.cc => src/dev/etherpkt.cc
rename : dev/etherpkt.hh => src/dev/etherpkt.hh
rename : dev/ethertap.cc => src/dev/ethertap.cc
rename : dev/ethertap.hh => src/dev/ethertap.hh
rename : dev/ide_atareg.h => src/dev/ide_atareg.h
rename : dev/ide_ctrl.cc => src/dev/ide_ctrl.cc
rename : dev/ide_ctrl.hh => src/dev/ide_ctrl.hh
rename : dev/ide_disk.cc => src/dev/ide_disk.cc
rename : dev/ide_disk.hh => src/dev/ide_disk.hh
rename : dev/ide_wdcreg.h => src/dev/ide_wdcreg.h
rename : dev/io_device.cc => src/dev/io_device.cc
rename : dev/io_device.hh => src/dev/io_device.hh
rename : dev/isa_fake.cc => src/dev/isa_fake.cc
rename : dev/isa_fake.hh => src/dev/isa_fake.hh
rename : dev/ns_gige.cc => src/dev/ns_gige.cc
rename : dev/ns_gige.hh => src/dev/ns_gige.hh
rename : dev/ns_gige_reg.h => src/dev/ns_gige_reg.h
rename : dev/pciconfigall.cc => src/dev/pciconfigall.cc
rename : dev/pciconfigall.hh => src/dev/pciconfigall.hh
rename : dev/pcidev.cc => src/dev/pcidev.cc
rename : dev/pcidev.hh => src/dev/pcidev.hh
rename : dev/pcireg.h => src/dev/pcireg.h
rename : dev/pitreg.h => src/dev/pitreg.h
rename : dev/pktfifo.cc => src/dev/pktfifo.cc
rename : dev/pktfifo.hh => src/dev/pktfifo.hh
rename : dev/platform.cc => src/dev/platform.cc
rename : dev/platform.hh => src/dev/platform.hh
rename : dev/rtcreg.h => src/dev/rtcreg.h
rename : dev/simconsole.cc => src/dev/simconsole.cc
rename : dev/simconsole.hh => src/dev/simconsole.hh
rename : dev/simple_disk.cc => src/dev/simple_disk.cc
rename : dev/simple_disk.hh => src/dev/simple_disk.hh
rename : dev/sinic.cc => src/dev/sinic.cc
rename : dev/sinic.hh => src/dev/sinic.hh
rename : dev/sinicreg.hh => src/dev/sinicreg.hh
rename : dev/tsunami.cc => src/dev/tsunami.cc
rename : dev/tsunami.hh => src/dev/tsunami.hh
rename : dev/tsunami_cchip.cc => src/dev/tsunami_cchip.cc
rename : dev/tsunami_cchip.hh => src/dev/tsunami_cchip.hh
rename : dev/tsunami_io.cc => src/dev/tsunami_io.cc
rename : dev/tsunami_io.hh => src/dev/tsunami_io.hh
rename : dev/tsunami_pchip.cc => src/dev/tsunami_pchip.cc
rename : dev/tsunami_pchip.hh => src/dev/tsunami_pchip.hh
rename : dev/tsunamireg.h => src/dev/tsunamireg.h
rename : dev/uart.cc => src/dev/uart.cc
rename : dev/uart.hh => src/dev/uart.hh
rename : dev/uart8250.cc => src/dev/uart8250.cc
rename : dev/uart8250.hh => src/dev/uart8250.hh
rename : kern/kernel_stats.cc => src/kern/kernel_stats.cc
rename : kern/kernel_stats.hh => src/kern/kernel_stats.hh
rename : kern/linux/events.cc => src/kern/linux/events.cc
rename : kern/linux/events.hh => src/kern/linux/events.hh
rename : kern/linux/linux.hh => src/kern/linux/linux.hh
rename : kern/linux/linux_syscalls.cc => src/kern/linux/linux_syscalls.cc
rename : kern/linux/linux_syscalls.hh => src/kern/linux/linux_syscalls.hh
rename : kern/linux/printk.cc => src/kern/linux/printk.cc
rename : kern/linux/printk.hh => src/kern/linux/printk.hh
rename : kern/linux/sched.hh => src/kern/linux/sched.hh
rename : kern/solaris/solaris.hh => src/kern/solaris/solaris.hh
rename : kern/system_events.cc => src/kern/system_events.cc
rename : kern/system_events.hh => src/kern/system_events.hh
rename : kern/tru64/dump_mbuf.cc => src/kern/tru64/dump_mbuf.cc
rename : kern/tru64/dump_mbuf.hh => src/kern/tru64/dump_mbuf.hh
rename : kern/tru64/mbuf.hh => src/kern/tru64/mbuf.hh
rename : kern/tru64/printf.cc => src/kern/tru64/printf.cc
rename : kern/tru64/printf.hh => src/kern/tru64/printf.hh
rename : kern/tru64/tru64.hh => src/kern/tru64/tru64.hh
rename : kern/tru64/tru64_events.cc => src/kern/tru64/tru64_events.cc
rename : kern/tru64/tru64_events.hh => src/kern/tru64/tru64_events.hh
rename : kern/tru64/tru64_syscalls.cc => src/kern/tru64/tru64_syscalls.cc
rename : kern/tru64/tru64_syscalls.hh => src/kern/tru64/tru64_syscalls.hh
rename : mem/bridge.cc => src/mem/bridge.cc
rename : mem/bridge.hh => src/mem/bridge.hh
rename : mem/bus.cc => src/mem/bus.cc
rename : mem/bus.hh => src/mem/bus.hh
rename : mem/cache/prefetch/tagged_prefetcher_impl.hh => src/mem/cache/prefetch/tagged_prefetcher_impl.hh
rename : mem/config/prefetch.hh => src/mem/config/prefetch.hh
rename : mem/mem_object.cc => src/mem/mem_object.cc
rename : mem/mem_object.hh => src/mem/mem_object.hh
rename : mem/packet.cc => src/mem/packet.cc
rename : mem/packet.hh => src/mem/packet.hh
rename : mem/page_table.cc => src/mem/page_table.cc
rename : mem/page_table.hh => src/mem/page_table.hh
rename : mem/physical.cc => src/mem/physical.cc
rename : mem/physical.hh => src/mem/physical.hh
rename : mem/port.cc => src/mem/port.cc
rename : mem/port.hh => src/mem/port.hh
rename : mem/request.hh => src/mem/request.hh
rename : mem/translating_port.cc => src/mem/translating_port.cc
rename : mem/translating_port.hh => src/mem/translating_port.hh
rename : mem/vport.cc => src/mem/vport.cc
rename : mem/vport.hh => src/mem/vport.hh
rename : python/SConscript => src/python/SConscript
rename : python/m5/__init__.py => src/python/m5/__init__.py
rename : python/m5/config.py => src/python/m5/config.py
rename : python/m5/convert.py => src/python/m5/convert.py
rename : python/m5/multidict.py => src/python/m5/multidict.py
rename : python/m5/objects/AlphaConsole.py => src/python/m5/objects/AlphaConsole.py
rename : python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/AlphaFullCPU.py
rename : python/m5/objects/AlphaTLB.py => src/python/m5/objects/AlphaTLB.py
rename : python/m5/objects/BadDevice.py => src/python/m5/objects/BadDevice.py
rename : python/m5/objects/BaseCPU.py => src/python/m5/objects/BaseCPU.py
rename : python/m5/objects/BaseCache.py => src/python/m5/objects/BaseCache.py
rename : python/m5/objects/Bridge.py => src/python/m5/objects/Bridge.py
rename : python/m5/objects/Bus.py => src/python/m5/objects/Bus.py
rename : python/m5/objects/CoherenceProtocol.py => src/python/m5/objects/CoherenceProtocol.py
rename : python/m5/objects/Device.py => src/python/m5/objects/Device.py
rename : python/m5/objects/DiskImage.py => src/python/m5/objects/DiskImage.py
rename : python/m5/objects/Ethernet.py => src/python/m5/objects/Ethernet.py
rename : python/m5/objects/Ide.py => src/python/m5/objects/Ide.py
rename : python/m5/objects/IntrControl.py => src/python/m5/objects/IntrControl.py
rename : python/m5/objects/MemObject.py => src/python/m5/objects/MemObject.py
rename : python/m5/objects/MemTest.py => src/python/m5/objects/MemTest.py
rename : python/m5/objects/Pci.py => src/python/m5/objects/Pci.py
rename : python/m5/objects/PhysicalMemory.py => src/python/m5/objects/PhysicalMemory.py
rename : python/m5/objects/Platform.py => src/python/m5/objects/Platform.py
rename : python/m5/objects/Process.py => src/python/m5/objects/Process.py
rename : python/m5/objects/Repl.py => src/python/m5/objects/Repl.py
rename : python/m5/objects/Root.py => src/python/m5/objects/Root.py
rename : python/m5/objects/SimConsole.py => src/python/m5/objects/SimConsole.py
rename : python/m5/objects/SimpleDisk.py => src/python/m5/objects/SimpleDisk.py
rename : python/m5/objects/System.py => src/python/m5/objects/System.py
rename : python/m5/objects/Tsunami.py => src/python/m5/objects/Tsunami.py
rename : python/m5/objects/Uart.py => src/python/m5/objects/Uart.py
rename : python/m5/smartdict.py => src/python/m5/smartdict.py
rename : sim/async.hh => src/sim/async.hh
rename : sim/builder.cc => src/sim/builder.cc
rename : sim/builder.hh => src/sim/builder.hh
rename : sim/byteswap.hh => src/sim/byteswap.hh
rename : sim/debug.cc => src/sim/debug.cc
rename : sim/debug.hh => src/sim/debug.hh
rename : sim/eventq.cc => src/sim/eventq.cc
rename : sim/eventq.hh => src/sim/eventq.hh
rename : sim/faults.cc => src/sim/faults.cc
rename : sim/faults.hh => src/sim/faults.hh
rename : sim/host.hh => src/sim/host.hh
rename : sim/main.cc => src/sim/main.cc
rename : sim/param.cc => src/sim/param.cc
rename : sim/param.hh => src/sim/param.hh
rename : sim/process.cc => src/sim/process.cc
rename : sim/process.hh => src/sim/process.hh
rename : sim/pseudo_inst.cc => src/sim/pseudo_inst.cc
rename : sim/pseudo_inst.hh => src/sim/pseudo_inst.hh
rename : sim/root.cc => src/sim/root.cc
rename : sim/serialize.cc => src/sim/serialize.cc
rename : sim/serialize.hh => src/sim/serialize.hh
rename : sim/sim_events.cc => src/sim/sim_events.cc
rename : sim/sim_events.hh => src/sim/sim_events.hh
rename : sim/sim_exit.hh => src/sim/sim_exit.hh
rename : sim/sim_object.cc => src/sim/sim_object.cc
rename : sim/sim_object.hh => src/sim/sim_object.hh
rename : sim/startup.cc => src/sim/startup.cc
rename : sim/startup.hh => src/sim/startup.hh
rename : sim/stat_control.cc => src/sim/stat_control.cc
rename : sim/stat_control.hh => src/sim/stat_control.hh
rename : sim/stats.hh => src/sim/stats.hh
rename : sim/syscall_emul.cc => src/sim/syscall_emul.cc
rename : sim/syscall_emul.hh => src/sim/syscall_emul.hh
rename : sim/system.cc => src/sim/system.cc
rename : sim/system.hh => src/sim/system.hh
rename : sim/vptr.hh => src/sim/vptr.hh
rename : test/Makefile => src/unittest/Makefile
rename : test/bitvectest.cc => src/unittest/bitvectest.cc
rename : test/circletest.cc => src/unittest/circletest.cc
rename : test/cprintftest.cc => src/unittest/cprintftest.cc
rename : test/foo.ini => src/unittest/foo.ini
rename : test/genini.py => src/unittest/genini.py
rename : test/initest.cc => src/unittest/initest.cc
rename : test/initest.ini => src/unittest/initest.ini
rename : test/lru_test.cc => src/unittest/lru_test.cc
rename : test/nmtest.cc => src/unittest/nmtest.cc
rename : test/offtest.cc => src/unittest/offtest.cc
rename : test/paramtest.cc => src/unittest/paramtest.cc
rename : test/rangetest.cc => src/unittest/rangetest.cc
rename : test/sized_test.cc => src/unittest/sized_test.cc
rename : test/stattest.cc => src/unittest/stattest.cc
rename : test/strnumtest.cc => src/unittest/strnumtest.cc
rename : test/symtest.cc => src/unittest/symtest.cc
rename : test/tokentest.cc => src/unittest/tokentest.cc
rename : test/tracetest.cc => src/unittest/tracetest.cc
extra : convert_revision : cab6a5271ca1b368193cd948e5d3dcc47ab1bd48
|
|
arch/mips/isa_traits.hh:
debug statements to be taken out real soon like...
--HG--
extra : convert_revision : 4e9abcb99c991db93328d01d7606a2bb942b29ee
|
|
Edit the convert_and_round function which access FloatRegFile
arch/isa_parser.py:
recognize when we are writing a 'uint64_t' FloatReg and set the width appropriately
arch/mips/isa/decoder.isa:
Send a 'float' to the convert function instead of a unsigned word. Do this so we dont have to worry about the
bit manipulation ourselves. We can just concern ourselves with values.
Use unsigned double to get movd...
arch/mips/isa/formats/fp.isa:
float debug statement
arch/mips/isa_traits.cc:
add different versions of convert_and_round functions
arch/mips/isa_traits.hh:
Use an array of uint32_t unsigned integers to represent the Floating Point Regfile
configs/test/hello_mips:
basic FP program
cpu/simple/cpu.hh:
spacing
--HG--
extra : convert_revision : a6fca91ad6365c83025f1131d71fa1b8ee76d7bc
|
|
arch/mips/isa/decoder.isa:
remove useless cout statements
arch/mips/isa_traits.hh:
space
--HG--
extra : convert_revision : 8b8cf5df6fc3eb92598360343eb887c35cda202d
|
|
in the InstObjParams constructor.
arch/isa_parser.py:
Expanded the capability of the InstObjParams constructor to allow adding in extra keys for use in templates. These are added as key, value tuples as optional arguements.
arch/sparc/isa/base.isa:
arch/sparc/isa/formats/mem.isa:
arch/sparc/isa/formats/priv.isa:
The genCompositeIop function is no longer needed, as this functionality is now in the InstObjParams constructor.
arch/sparc/isa/decoder.isa:
Fixed up alot of instructions, and fixed indentation.
arch/sparc/isa/formats/integerop.isa:
The genCompositeIop function is no longer needed, as this functionality is now in the InstObjParams constructor. Also changed the immediate values to be signed.
base/traceflags.py:
Added SPARC traceflag
configs/test/hello_sparc:
Recompiled without -mflat
cpu/cpu_exec_context.cc:
Used the regfile clear function rather than memsetting to 0.
--HG--
extra : convert_revision : b9da6f264f3ebc4ce1815008dfff7f476b247ee9
|
|
Makes .isa files cleaner and simplifies scanner too.
Simplified scanner to work under both old and new versions of scons.
arch/SConscript:
Simplify .isa scanner... seems to work with both scons 0.96.1 and 0.96.91 now.
Assumes .isa ##include paths are relative to including file.
arch/alpha/isa/main.isa:
arch/mips/isa/formats/formats.isa:
arch/mips/isa/main.isa:
arch/sparc/isa/formats.isa:
arch/sparc/isa/main.isa:
Make ##include paths relative to including file.
arch/isa_parser.py:
Make ##include file paths relative to including file.
Makes .isa files cleaner and simplifies scanner too.
Partial rewrite of include-handling code to use cool re.sub() feature
where you can specify a function to provide the replacement string.
Minor cleanup of error-handling code.
Also got rid of '#!' at top to make caller choose which python interpreter
is used (since SPARC now requires 2.4 to build, we may need to do that via
scons in the future).
--HG--
rename : arch/mips/isa/formats.isa => arch/mips/isa/formats/formats.isa
extra : convert_revision : 15a3920fa3aaf80cd94083eda853aa4e49425045
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|
accessor functions. The width of the floating point register to access can be specified, and if not, it will be accessed at its "natural" width. That is, the width of each individual register. Also, the functions which access the bit representation of floating point registers can use the blahblahBits functions now instead of blahblahInt.
arch/alpha/arguments.cc:
Renamed readFloatRegInt to readFloatRegBits
arch/alpha/ev5.cc:
Removed the Double from setFloatRegDouble
arch/alpha/registerfile.hh:
Changed the floating point register file from a union of arrays to a class with appropriate accessor functions. The interface is necessary for SPARC.
arch/alpha/types.hh:
Changed the FloatReg type from a union of uint64_t and double to a double, and defined a new type FloatRegBits which is a uint64_t and is used to return the bits which compose a floating point register rather than the value of the register.
arch/isa_parser.py:
Adjusted the makeRead and makeWrite functions to generate the new versions of readFloatReg and setFloatReg.
base/remote_gdb.cc:
kern/tru64/tru64.hh:
Replaced setFloatRegInt with setFloatRegBits
cpu/cpu_exec_context.cc:
Removed the duplicated code for setting the floating point registers, and renamed the function to setFloatRegBits and readFloatRegBits.
cpu/cpu_exec_context.hh:
cpu/exec_context.hh:
cpu/o3/alpha_cpu_impl.hh:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
cpu/o3/regfile.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.hh:
Implemented the new versions of the floating point read and set functions.
cpu/simple/cpu.cc:
Replaced setFloatRegDouble with setFloatReg
--HG--
extra : convert_revision : 3dad06224723137f6033c335fb8f6395636767f2
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|
time. This requires using an ExtMachInst (uint64_t) instead of the normal MachInst; the ExtMachInst is packed with extra decode context information. In the case of Alpha, the PAL mode is included.
The shadow registers are folded into the normal integer registers to ease renaming indexing.
Include the removed Opcdec class of instructions for faulting when a pal mode only instruction is decoded in non-pal mode.
arch/alpha/ev5.cc:
Changes to automatically map the shadow registers if the instruction is in PAL mode.
arch/alpha/isa/branch.isa:
arch/alpha/isa/decoder.isa:
arch/alpha/isa/fp.isa:
arch/alpha/isa/int.isa:
arch/alpha/isa/mem.isa:
arch/alpha/isa/pal.isa:
arch/alpha/isa/unimp.isa:
Changes for automatically using the shadow registers. Now instructions must decode based on an ExtMachInst, which is a MachInst with any decode context information concatenated onto the higher order bits.
arch/alpha/isa/main.isa:
Changes for automatically using the shadow registers. Now instructions must decode based on an ExtMachInst, which is a MachInst with any decode context information concatenated onto the higher order bits.
The decoder (for Alpha) uses the 32nd bit in order to determine if the machine is in PAL mode. If it is, then it refers to the reg_redir table to determine the true index of the register it is using.
Also include the opcdec instruction definition.
arch/alpha/isa_traits.hh:
Define ExtMachInst type that is used by the static inst in order to decode the instruction, given the context of being in pal mode or not.
Redefine the number of Int registers, splitting it into NumIntArchRegs (32) and NumIntRegs (32 + 8 shadow registers).
Change the dependence tags to reflect the integer registers include the 8 shadow registers.
Define function to make an ExtMachInst. Currently it is somewhat specific to Alpha; in the future it must be decided to make this more generic and possibly slower, or leave it specific to each architecture and ifdef it within the CPU.
arch/isa_parser.py:
Have static insts decode on the ExtMachInst.
base/remote_gdb.cc:
Support the automatic remapping of shadow registers. Remote GDB must now look at the PC being read in order to tell if it should use the normal register indices or the shadow register indices.
cpu/o3/regfile.hh:
Comment out the pal registers; they are now a part of the integer registers.
cpu/simple/cpu.cc:
Create an ExtMachInst to decode on, based on the normal MachInst and the PC of the instructoin.
cpu/static_inst.hh:
Change from MachInst to ExtMachInst to support shadow register renaming.
--HG--
extra : convert_revision : 1d23eabf735e297068e1917445a6348e9f8c88d5
|
|
the FPCR, Uniq, lock flag, lock addr, and IPRs.
They are now accessed by calling readMiscReg()/setMiscReg() on the XC. Old IPR accesses are supported by using readMiscRegWithEffect() and setMiscRegWithEffect() (names may change in the future).
arch/alpha/alpha_memory.cc:
Change accesses to IPR to go through the XC.
arch/alpha/ev5.cc:
Change accesses for IPRs to go through the misc regs.
arch/alpha/isa/decoder.isa:
Change accesses to IPRs to go through the misc regs. readIpr() and setIpr() are now changed to calls to readMiscRegWithEffect() and setMiscRegWithEffect().
arch/alpha/isa/fp.isa:
Change accesses to IPRs and Fpcr to go through the misc regs.
arch/alpha/isa/main.isa:
Add support for all misc regs being accessed through readMiscReg() and setMiscReg(). Instead of readUniq and readFpcr, they are replaced by calls with Uniq_DepTag and Fpcr_DepTag passed in as the register index.
arch/alpha/isa_traits.hh:
Change the MiscRegFile to a class that handles all accesses to MiscRegs, which in Alpha include the FPCR, Uniq, Lock Addr, Lock Flag, and IPRs.
Two flavors of accesses are supported: normal register reads/writes, and reads/writes with effect. The latter are basically the original read/write IPR functions, while the former are normal reads/writes.
The lock flag and lock addr registers are added to the dependence tags in order to support being accessed through the misc regs.
arch/alpha/stacktrace.cc:
cpu/simple/cpu.cc:
dev/sinic.cc:
Change accesses to the IPRs to go through the XC.
arch/alpha/vtophys.cc:
Change access to the IPR to go through the XC.
arch/isa_parser.py:
Change generation of code for control registers to use the readMiscReg and setMiscReg functions.
base/remote_gdb.cc:
Change accesses to the IPR to go through the XC.
cpu/exec_context.hh:
Use the miscRegs to access the lock addr, lock flag, and other misc registers.
cpu/o3/alpha_cpu.hh:
cpu/simple/cpu.hh:
Support interface for reading and writing misc registers, which replaces readUniq, readFpcr, readIpr, and their set functions.
cpu/o3/alpha_cpu_impl.hh:
Change accesses to the IPRs to go through the miscRegs.
For now comment out some of the accesses to the misc regs until the proxy exec context is completed.
cpu/o3/alpha_dyn_inst.hh:
Change accesses to misc regs to use readMiscReg and setMiscReg.
cpu/o3/alpha_dyn_inst_impl.hh:
Remove old misc reg accessors.
cpu/o3/cpu.cc:
Comment out old misc reg accesses until the proxy exec context is completed.
cpu/o3/cpu.hh:
Change accesses to the misc regs.
cpu/o3/regfile.hh:
Remove old access methods for the misc regs, replace them with readMiscReg and setMiscReg. They are dummy functions for now until the proxy exec context is completed.
kern/kernel_stats.cc:
kern/system_events.cc:
Have accesses to the IPRs go through the XC.
kern/tru64/tru64.hh:
Have accesses to the misc regs use the new access methods.
--HG--
extra : convert_revision : e32e0a3fe99522e17294bbe106ff5591cb1a9d76
|
|
CPU_MODELS parameter. For example:
scons CPU_MODELS="SimpleCPU,FullCPU" ALPHA_SE/m5.debug
Unfortunately the option is not sticky due to a scons
bug with saving & restoring ListOption parameters.
SConscript:
Separate out cpu-model-specific files so they can be conditionally
included based on value of new CPU_MODELS parameter.
Most of these are now handled in cpu/SConscript, except for FullCPU
which is still in this file.
arch/SConscript:
The set of CPU-model-specific execute files must now be
determined from the CPU_MODELS parameter, via the new
cpu_models.py file.
Also pass the list of configured CPU models to isa_parser.py.
arch/isa_parser.py:
Move CpuModel definition and objects out to a
separate file so they can be shared with scons.
Global list of CPU models to generate code for is now
controlled by command-line parameters (so we can do
only a subset of the available ones).
build/SConstruct:
Define new CPU_MODELS ListOption.
cpu/static_inst.hh:
Rename static_inst_impl.hh to static_inst_exec_sigs.hh.
--HG--
extra : convert_revision : 163df32a76d4c05900490b2bce4c7962a5e3f614
|
|
Start using SCons File objects to avoid fixed paths in
subordinate SConscripts.
SConscript:
Push isa_parser stuff (including .isa scanner) down into
arch/SConscript.
arch/SConscript:
Create a Builder object for .isa files, including existing scanner.
Return file objects generated by isa-specific SConscript
back up to parent.
arch/alpha/SConscript:
arch/mips/SConscript:
arch/sparc/SConscript:
Convert sources to scons File objects, so file names can be specified
relative to the current directory.
Invoke new builder for isa description, and get generated sources from
there (instead of listing them explicitly).
arch/isa_parser.py:
Get rid of third argument ("include_path").
It was a pain to generate this from scons, and it turned out
it's not needed anyway, since the only included file
(decoder.hh) will be in the same directory as the sources.
--HG--
extra : convert_revision : 36861bcef36763f229704d8cb7a642b4486a3581
|
|
into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch
arch/alpha/faults.hh:
ur
Using cleaned up fault class deiffinitions
--HG--
extra : convert_revision : a600950d539be2be73358f072aa5426456bf3d2d
|
|
into ewok.(none):/home/gblack/m5/multiarch
--HG--
extra : convert_revision : 090b30a7f70294e1aeb13ba0bc15da4061bdf348
|
|
namespace instead of a class, an improvement to the architecture specific header file selection system, and fixed up a few include paths.
arch/alpha/alpha_linux_process.cc:
Added using directive for AlphaISA namespace
arch/alpha/alpha_memory.hh:
arch/alpha/isa/branch.isa:
cpu/pc_event.hh:
Added typedefs for Addr
arch/alpha/alpha_tru64_process.cc:
arch/alpha/arguments.cc:
Added using directive for AlphaISA
arch/alpha/ev5.hh:
Added an include of arch/alpha/isa_traits.hh, and a using directive for the AlphaISA namespace.
arch/alpha/faults.hh:
Added a typedef for the Addr type, and changed the formatting of the faults slightly.
arch/alpha/isa/main.isa:
Untemplatized StaticInst, added a using for namespace AlphaISA to show up in decoder.cc and the exec.ccs, relocated makeNop to decoder.hh
arch/alpha/isa/mem.isa:
Untemplatized StaticInst and StaticInstPtr
arch/alpha/isa/pal.isa:
cpu/base_dyn_inst.cc:
Untemplatized StaticInstPtr
arch/alpha/isa_traits.hh:
Changed variables to be externs instead of static since they are part of a namespace and not a class.
arch/alpha/stacktrace.cc:
Untemplatized StaticInstPtr, and added a using directive for AlphaISA.
arch/alpha/stacktrace.hh:
Added some typedefs for Addr and MachInst, and untemplatized StaticInstPtr
arch/alpha/vtophys.cc:
Added a using directive for AlphaISA
arch/alpha/vtophys.hh:
Added the AlphaISA namespace specifier where needed
arch/isa_parser.py:
Changed the placement of the definition of the decodeInst function to be outside the namespaceInst namespace.
base/loader/object_file.hh:
cpu/o3/bpred_unit.hh:
Added a typedef for Addr
base/loader/symtab.hh:
Added a typedef for Addr, and added a TheISA to Addr in another typedef
base/remote_gdb.cc:
Added a using namespace TheISA, and untemplatized StaticInstPtr
base/remote_gdb.hh:
Added typedefs for Addr and MachInst
cpu/base.cc:
Added TheISA specifier to some variables exported from the isa.
cpu/base.hh:
Added a typedef for Addr, and TheISA to some variables from the ISA
cpu/base_dyn_inst.hh:
Untemplatized StaticInstPtr, and added TheISA specifier to some variables from the ISA.
cpu/exec_context.hh:
Added some typedefs for types from the isa, and added TheISA specifier to some variables from the isa
cpu/exetrace.hh:
Added typedefs for some types from the ISA, and untemplatized StaticInstPtr
cpu/memtest/memtest.cc:
cpu/o3/btb.cc:
dev/baddev.cc:
dev/ide_ctrl.cc:
dev/ide_disk.cc:
dev/isa_fake.cc:
dev/ns_gige.cc:
dev/pciconfigall.cc:
dev/platform.cc:
dev/sinic.cc:
dev/uart8250.cc:
kern/freebsd/freebsd_system.cc:
kern/linux/linux_system.cc:
kern/system_events.cc:
kern/tru64/dump_mbuf.cc:
kern/tru64/tru64_events.cc:
sim/process.cc:
sim/pseudo_inst.cc:
sim/system.cc:
Added using namespace TheISA
cpu/memtest/memtest.hh:
cpu/trace/opt_cpu.hh:
cpu/trace/reader/itx_reader.hh:
dev/ide_disk.hh:
dev/pcidev.hh:
dev/platform.hh:
dev/tsunami.hh:
sim/system.hh:
sim/vptr.hh:
Added typedef for Addr
cpu/o3/2bit_local_pred.hh:
Changed the include to use arch/isa_traits.hh instead of arch/alpha/isa_traits.hh. Added typedef for Addr
cpu/o3/alpha_cpu.hh:
Added typedefs for Addr and IntReg
cpu/o3/alpha_cpu_impl.hh:
Added this-> to setNextPC to fix a problem since it didn't depend on template parameters any more. Removed "typename" where it was no longer needed.
cpu/o3/alpha_dyn_inst.hh:
Cleaned up some typedefs, and untemplatized StaticInst
cpu/o3/alpha_dyn_inst_impl.hh:
untemplatized StaticInstPtr
cpu/o3/alpha_impl.hh:
Fixed up a typedef of MachInst
cpu/o3/bpred_unit_impl.hh:
Added a using TheISA::MachInst to a function
cpu/o3/btb.hh:
Changed an include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr
cpu/o3/commit.hh:
Removed a typedef of Impl::ISA as ISA, since TheISA takes care of this now.
cpu/o3/cpu.cc:
Cleaned up namespace issues
cpu/o3/cpu.hh:
Cleaned up namespace usage
cpu/o3/decode.hh:
Removed typedef of ISA, and changed it to TheISA
cpu/o3/fetch.hh:
Fized up typedefs, and changed ISA to TheISA
cpu/o3/free_list.hh:
Changed include of arch/alpha/isa_traits.hh to arch/isa_traits.hh
cpu/o3/iew.hh:
Removed typedef of ISA
cpu/o3/iew_impl.hh:
Added TheISA namespace specifier to MachInst
cpu/o3/ras.hh:
Changed include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr.
cpu/o3/regfile.hh:
Changed ISA to TheISA, and added some typedefs for Addr, IntReg, FloatReg, and MiscRegFile
cpu/o3/rename.hh:
Changed ISA to TheISA, and added a typedef for RegIndex
cpu/o3/rename_map.hh:
Added an include for arch/isa_traits.hh, and a typedef for RegIndex
cpu/o3/rob.hh:
Added a typedef for RegIndex
cpu/o3/store_set.hh:
cpu/o3/tournament_pred.hh:
Changed an include of arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef of Addr
cpu/ozone/cpu.hh:
Changed ISA into TheISA, and untemplatized StaticInst
cpu/pc_event.cc:
Added namespace specifier TheISA to Addr types
cpu/profile.hh:
kern/kernel_stats.hh:
Added typedef for Addr, and untemplatized StaticInstPtr
cpu/simple/cpu.cc:
Changed using directive from LittleEndianGuest to AlphaISA, which will contain both namespaces. Added TheISA where needed, and untemplatized StaticInst
cpu/simple/cpu.hh:
Added a typedef for MachInst, and untemplatized StaticInst
cpu/static_inst.cc:
Untemplatized StaticInst
cpu/static_inst.hh:
Untemplatized StaticInst by using the TheISA namespace
dev/alpha_console.cc:
Added using namespace AlphaISA
dev/simple_disk.hh:
Added typedef for Addr and fixed up some formatting
dev/sinicreg.hh:
Added TheISA namespace specifier where needed
dev/tsunami.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
Added using namespace TheISA. It might be better for it to be AlphaISA
dev/tsunami_cchip.cc:
Added typedef for TheISA. It might be better for it to be AlphaISA
kern/linux/aligned.hh:
sim/pseudo_inst.hh:
Added TheISA namespace specifier to Addr
kern/linux/linux_threadinfo.hh:
Added typedef for Addr, and TheISA namespace specifier to StackPointerReg
kern/tru64/mbuf.hh:
Added TheISA to Addr type in structs
sim/process.hh:
Added typedefs of Addr, RegFile, and MachInst
sim/syscall_emul.cc:
Added using namespace TheISA, and a cast of VMPageSize to the int type
sim/syscall_emul.hh:
Added typecast for Addr, and TheISA namespace specifier for where needed
--HG--
extra : convert_revision : 91d4f6ca33a73b21c1f1771d74bfdea3b80eff45
|
|
Edits to the CPU model may still need to be made to handle branch likely insts...
arch/isa_parser.py:
add a NNPC operand ...
arch/mips/isa/base.isa:
change SPARC to MIPS
arch/mips/isa/decoder.isa:
typo < to >=
arch/mips/isa/formats/basic.isa:
spacing
arch/mips/isa/formats/branch.isa:
add code for branch instructions (still need adjustments for the branch likely)
arch/mips/isa/operands.isa:
support for NNPC and R31
arch/mips/isa_traits.hh:
NNPC Addr variable
--HG--
extra : convert_revision : df03d2a71c36dbc00270c2e3d7882b4f09ed97ad
|
|
little more cleanly.
arch/alpha/isa/mem.isa:
Avoid explicitly declaring the Mem variable. Instead break up the code blocks used to generate the initiate and complete functions. The templates reflect which operands need to be declared for each function (src, dest, or both).
Loads use both the EA code and mem acc code for the initiate, and memacc code and postacc code for the complete.
Stores use both the EA code and mem acc code for the initiate, and only post acc code for the complete.
arch/isa_parser.py:
Remove hack for mem ops.
--HG--
extra : convert_revision : a367797a2cb698762bfc27be1da00bcbe9367150
|
|
will be helpful for the merged memory model.
arch/alpha/isa/mem.isa:
Include methods that allow a memory operation to be split between the part that initiates the access, and the part that completes the access. In these functions the Mem variable is explicitly declared; in the default execute functions, the Mem variable is still handled through %(op_decl)s.
arch/isa_parser.py:
Include recording the type of the memory access variable so that it can be used if it needs to be explicitly declared in a template.
Have memory operands consider themselves neither a source nor a destination to avoid including themselves on the op_src_decl list or the op_dest_decl list.
Record op_src_decl and op_dest_decl lists to allow for declaring only source or destination operands. This is needed for the split memory access methods.
--HG--
extra : convert_revision : f674f7a2f747ae40ba8c3a0933b0337c87ee0b6c
|
|
minor change to syntax of 'def operands' in ISA descriptions.
arch/alpha/isa/main.isa:
arch/mips/isa/operands.isa:
arch/sparc/isa/operands.isa:
Change 'def operands' statement to work with new
isa_parser changes.
arch/isa_parser.py:
Merge OperandTraits and OperandDescriptor objects into a
unified hierarchy of Operand objects.
Required a change in the syntax of the 'def operands'
statement in the ISA description.
--HG--
extra : convert_revision : cb43f1607311497ead88ba13953d410ab5bc6a37
|
|
arch/isa_parser.py:
Minor cleanup of operand type and traits code:
- build operand size map right away when types are defined
instead of waiting to do it lazily
- check that operand types have been defined before operands
- don't use 'type' as a variable name
- use isinstance() instead of checking for types directly
--HG--
extra : convert_revision : 099c1ee8d490f9c38316749bf87209388c55c971
|
|
instruction format functions in ISA description language.
Take advantage of these features to clean up memory
instruction definitions in Alpha.
arch/alpha/isa/decoder.isa:
arch/alpha/isa/mem.isa:
arch/alpha/isa/pal.isa:
Take advantage of new keyword parameters to disambiguate
instruction vs. memory-request flags, and to provide
a default EA calculation for memory ops (since 99% of them
are the same).
arch/isa_parser.py:
Add two new features to instruction format functions:
- Keyword parameters, a la Python.
- List-valued arguments.
Also export makeList() function to Python code blocks,
as this is handy for dealing with flags.
--HG--
extra : convert_revision : 99bbbaa2e765230aa96b6a06ed193793325f9fb0
|
|
Should enable implementation of split-phase timing loads
with new memory model.
May create slight timing differences under FullCPU, as I
believe we were not handling software prefetches correctly
before when the split MemAcc/Exec model was used. I haven't
looked into this in any detail though.
arch/alpha/isa/decoder.isa:
HwLoadStore format split into separate HwLoad and
HwStore formats.
Copy instructions now fall under MiscPrefetch format.
Mem_write_result is now just write_result in store
conditionals.
arch/alpha/isa/mem.isa:
Split MemAccExecute and LoadStoreExecute templates
into separate templates for loads and stores; now
that memory operands are handled differently from
registers, it's impossible to have a single template
serve both.
Also unified the handling of "regular" prefetches
(loads to r31) and "misc" prefetches (e.g., wh64)
under the new scheme. It looks like SW prefetches
were not handled correctly in FullCPU up til now,
since we generated an execute() method for the outer
instruction but didn't generate a proper method for
MemAcc::execute() (instead getting a default no-op
method for that).
arch/alpha/isa/pal.isa:
Split HwLoadStore into separate HwLoad and HwStore
formats to select proper template (see change to
mem.isa in this changeset).
arch/isa_parser.py:
Stop trying to treat memory operands like register
operands, since we never used them in a uniform way
anyway, and it made it impossible to do split-phase
loads as needed for the new CPU model. Now there's no
more 'op_mem_rd', 'op_nonmem_rd', etc.: 'op_rd' just does
register operands, and the template code is responsible
for formulating the call to the memory system. Right now
the only thing exported by InstObjParams is a new attribute
'mem_acc_size' which gives the memory access size in bits,
though more attributes can be added if needed.
Also moved code in findOperands() method to
OperandDescriptorList.__init__(), which is where it belongs.
--HG--
extra : convert_revision : 6d53d07e0c5e828455834ded4395fa40f9146a34
|
|
arch/isa_parser.py:
Clean up ##include code a bit.
arch/sparc/isa/formats.isa:
arch/sparc/isa/main.isa:
Fix include paths.
--HG--
extra : convert_revision : 0689963c2948e5f1088ecbf2cf6018d29bdaceff
|
|
into zizzer.eecs.umich.edu:/z/stever/bk/m5
--HG--
extra : convert_revision : 10146c85d2fa6f565568cc30a4564b3674e4768d
|
|
arch/isa_parser.py:
Get rid of "munged name" for operands in C++ code.
That is, "Ra.uq" will now be known in the C++ as "Ra"
rather than "Ra_uq". It wasn't legal to use different
type extensions for the same operand at the same time
anyway, and now it will be easier to refer to explicit
operands in template code if necessary.
--HG--
extra : convert_revision : 9ff41e0201aeefe761743084ecdb34f4b9c84fdb
|
|
repository was created.
SConscript:
There is a new SConscript in the arch/alpha directory which has the alpha specific files. To add files for an arch, a similar file should be created.
arch/isa_parser.py:
The isa parser now supports include directives. These are done with ##include
build/SConstruct:
The target directory is passed on so that the architecture specific SConscript can have it. Also, sparc was added as a valid architecture type.
arch/alpha/SConscript:
This SConscript adds the alpha specific source
arch/sparc/isa_desc/operands.h:
This sets up the operand types that the sparc isa uses
arch/sparc/isa_traits.cc:
Implementation of sparc specific things, like a register file with windows
build/build_options/default/SPARC_SE:
The default options for a sparc syscall emulation build.
--HG--
extra : convert_revision : 1afedae61dc8cae0d59d3bf1d41420d929be2efd
|
|
arch/isa_parser.py:
Derive Stack class directly from list.
--HG--
extra : convert_revision : 4f09db4baec0bb2144d71ffad5ce53651e8c3ac6
|
|
Seems to avoid the significant problems on platforms w/o fenv.h.
arch/alpha/isa_desc:
Explicitly handle rounding on FP-to-integer conversions.
Seems to avoid the significant problems on platforms w/o fenv.h.
Get rid of FP "Fast" vs "General" distinction... more headache than
it's worth.
arch/isa_parser.py:
Fix bug with "%s" in C++ templates (must escape properly to
pass through Python string interpolation).
--HG--
extra : convert_revision : de964d764e67e0934ac0ef535f53c974640731fb
|
|
that the script doesn't deal with.
Don't bother with copyright notices in generated files.
LICENSE:
Fix author list.
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
Fix inconsistently formatted copyright.
arch/isa_parser.py:
base/traceflags.py:
Fix copyright & author list.
Don't bother with copyrights in generated files.
dev/rtcreg.h:
Fix broken copyright.
--HG--
extra : convert_revision : d628e63c495960e2b129cef0aa8fddbdd4dabd45
|
|
Remove RCS Id string
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/alpha_tru64_process.cc:
arch/alpha/aout_machdep.h:
arch/alpha/arguments.cc:
arch/alpha/arguments.hh:
arch/alpha/ecoff_machdep.h:
arch/isa_parser.py:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/faults.cc:
arch/alpha/faults.hh:
arch/alpha/isa_traits.hh:
arch/alpha/osfpal.cc:
arch/alpha/osfpal.hh:
arch/alpha/pseudo_inst.cc:
arch/alpha/pseudo_inst.hh:
arch/alpha/vptr.hh:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
base/bitfield.hh:
base/callback.hh:
base/circlebuf.cc:
base/circlebuf.hh:
base/cprintf.cc:
base/cprintf.hh:
base/cprintf_formats.hh:
base/crc.cc:
base/crc.hh:
base/date.cc:
base/dbl_list.hh:
base/endian.hh:
base/fast_alloc.cc:
base/fast_alloc.hh:
base/fifo_buffer.cc:
base/fifo_buffer.hh:
base/hashmap.hh:
base/hostinfo.cc:
base/hostinfo.hh:
base/hybrid_pred.cc:
base/hybrid_pred.hh:
base/inet.cc:
base/inet.hh:
base/inifile.cc:
base/inifile.hh:
base/intmath.cc:
base/intmath.hh:
base/kgdb.h:
base/match.cc:
base/match.hh:
base/misc.cc:
base/misc.hh:
base/mod_num.hh:
base/mysql.cc:
base/mysql.hh:
base/output.cc:
base/output.hh:
base/pollevent.cc:
base/pollevent.hh:
base/predictor.hh:
base/random.cc:
base/random.hh:
base/range.cc:
base/range.hh:
base/refcnt.hh:
base/remote_gdb.cc:
base/remote_gdb.hh:
base/res_list.hh:
base/sat_counter.cc:
base/sat_counter.hh:
base/sched_list.hh:
base/socket.cc:
base/socket.hh:
base/statistics.cc:
base/statistics.hh:
base/compression/lzss_compression.cc:
base/compression/lzss_compression.hh:
base/compression/null_compression.hh:
base/loader/aout_object.cc:
base/loader/aout_object.hh:
base/loader/coff_sym.h:
base/loader/coff_symconst.h:
base/loader/ecoff_object.cc:
base/loader/ecoff_object.hh:
base/loader/elf_object.cc:
base/loader/elf_object.hh:
base/loader/exec_aout.h:
base/loader/exec_ecoff.h:
base/loader/symtab.cc:
base/loader/symtab.hh:
base/stats/events.cc:
base/stats/events.hh:
base/stats/flags.hh:
base/stats/mysql.cc:
base/stats/mysql.hh:
base/stats/mysql_run.hh:
base/stats/output.hh:
base/stats/statdb.cc:
base/stats/statdb.hh:
base/stats/text.cc:
base/stats/text.hh:
base/stats/types.hh:
base/stats/visit.cc:
base/stats/visit.hh:
base/str.cc:
base/str.hh:
base/time.cc:
base/time.hh:
base/timebuf.hh:
base/trace.cc:
base/trace.hh:
base/traceflags.py:
base/userinfo.cc:
base/userinfo.hh:
cpu/base.cc:
cpu/base.hh:
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/exetrace.cc:
cpu/exetrace.hh:
cpu/inst_seq.hh:
cpu/intr_control.cc:
cpu/intr_control.hh:
cpu/pc_event.cc:
cpu/pc_event.hh:
cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
cpu/o3/2bit_local_pred.cc:
cpu/o3/2bit_local_pred.hh:
cpu/o3/alpha_cpu.cc:
cpu/o3/alpha_cpu.hh:
cpu/o3/alpha_cpu_builder.cc:
cpu/o3/alpha_dyn_inst.cc:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_dyn_inst_impl.hh:
cpu/o3/alpha_impl.hh:
cpu/o3/alpha_params.hh:
cpu/o3/bpred_unit.cc:
cpu/o3/bpred_unit.hh:
cpu/o3/bpred_unit_impl.hh:
cpu/o3/btb.cc:
cpu/o3/btb.hh:
cpu/o3/comm.hh:
cpu/o3/commit.cc:
cpu/o3/commit.hh:
cpu/o3/commit_impl.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
cpu/o3/cpu_policy.hh:
cpu/o3/decode.cc:
cpu/o3/decode.hh:
cpu/o3/decode_impl.hh:
cpu/o3/fetch.cc:
cpu/o3/fetch.hh:
cpu/o3/fetch_impl.hh:
cpu/o3/free_list.cc:
cpu/o3/free_list.hh:
cpu/o3/iew.cc:
cpu/o3/iew.hh:
cpu/o3/iew_impl.hh:
cpu/o3/inst_queue.cc:
cpu/o3/inst_queue.hh:
cpu/o3/inst_queue_impl.hh:
cpu/o3/mem_dep_unit.cc:
cpu/o3/mem_dep_unit.hh:
cpu/o3/mem_dep_unit_impl.hh:
cpu/o3/ras.cc:
cpu/o3/ras.hh:
cpu/o3/regfile.hh:
cpu/o3/rename.cc:
cpu/o3/rename.hh:
cpu/o3/rename_impl.hh:
cpu/o3/rename_map.cc:
cpu/o3/rename_map.hh:
cpu/o3/rob.hh:
cpu/o3/rob_impl.hh:
cpu/o3/sat_counter.cc:
cpu/o3/sat_counter.hh:
cpu/o3/store_set.cc:
cpu/o3/store_set.hh:
cpu/o3/tournament_pred.cc:
cpu/o3/tournament_pred.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
cpu/smt.hh:
cpu/static_inst.cc:
cpu/static_inst.hh:
cpu/trace/opt_cpu.hh:
cpu/trace/reader/ibm_reader.cc:
cpu/trace/reader/ibm_reader.hh:
cpu/trace/reader/itx_reader.cc:
cpu/trace/reader/itx_reader.hh:
cpu/trace/reader/m5_reader.cc:
cpu/trace/reader/m5_reader.hh:
cpu/trace/reader/mem_trace_reader.cc:
cpu/trace/reader/mem_trace_reader.hh:
cpu/trace/trace_cpu.cc:
cpu/trace/trace_cpu.hh:
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/baddev.cc:
dev/baddev.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.cc:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.cc:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/ide_disk.cc:
dev/ide_disk.hh:
dev/io_device.cc:
dev/io_device.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/ns_gige_reg.h:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/pcidev.cc:
dev/pcidev.hh:
dev/pcireg.h:
dev/pktfifo.cc:
dev/pktfifo.hh:
dev/platform.cc:
dev/platform.hh:
dev/simconsole.cc:
dev/simconsole.hh:
dev/simple_disk.cc:
dev/simple_disk.hh:
dev/sinic.cc:
dev/sinic.hh:
dev/sinicreg.hh:
dev/tsunami.cc:
dev/tsunami.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/uart.cc:
dev/uart.hh:
dev/uart8250.cc:
dev/uart8250.hh:
docs/stl.hh:
encumbered/cpu/full/op_class.hh:
kern/kernel_stats.cc:
kern/kernel_stats.hh:
kern/linux/linux.hh:
kern/system_events.cc:
kern/system_events.hh:
kern/linux/linux_syscalls.cc:
kern/linux/linux_syscalls.hh:
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
kern/linux/printk.cc:
kern/linux/printk.hh:
kern/tru64/dump_mbuf.cc:
kern/tru64/dump_mbuf.hh:
kern/tru64/mbuf.hh:
kern/tru64/printf.cc:
kern/tru64/printf.hh:
kern/tru64/tru64.hh:
kern/tru64/tru64_events.cc:
kern/tru64/tru64_events.hh:
kern/tru64/tru64_syscalls.cc:
kern/tru64/tru64_syscalls.hh:
kern/tru64/tru64_system.cc:
kern/tru64/tru64_system.hh:
sim/async.hh:
sim/builder.cc:
sim/builder.hh:
sim/debug.cc:
sim/debug.hh:
sim/eventq.cc:
sim/eventq.hh:
sim/host.hh:
sim/main.cc:
sim/param.cc:
sim/param.hh:
sim/root.cc:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_events.cc:
sim/sim_events.hh:
sim/sim_exit.hh:
sim/sim_object.cc:
sim/sim_object.hh:
sim/startup.cc:
sim/startup.hh:
sim/stat_control.cc:
sim/stat_control.hh:
sim/stats.hh:
sim/syscall_emul.cc:
sim/syscall_emul.hh:
sim/system.cc:
sim/system.hh:
test/Makefile:
test/bitvectest.cc:
test/circletest.cc:
test/cprintftest.cc:
test/initest.cc:
test/lru_test.cc:
test/nmtest.cc:
test/offtest.cc:
test/paramtest.cc:
test/rangetest.cc:
test/sized_test.cc:
test/stattest.cc:
test/strnumtest.cc:
test/symtest.cc:
test/tokentest.cc:
test/tracetest.cc:
util/m5/m5.c:
util/m5/m5op.h:
util/m5/m5op.s:
util/tap/Makefile:
util/tap/tap.cc:
util/term/Makefile:
util/term/term.c:
Remove RCS Id string
--HG--
extra : convert_revision : fc5b0a6ee2a213785bd58c51ce82eb2f769d6b88
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|
--HG--
rename : cpu/base_cpu.cc => cpu/base.cc
rename : cpu/base_cpu.hh => cpu/base.hh
rename : cpu/beta_cpu/2bit_local_pred.cc => cpu/o3/2bit_local_pred.cc
rename : cpu/beta_cpu/2bit_local_pred.hh => cpu/o3/2bit_local_pred.hh
rename : cpu/beta_cpu/alpha_full_cpu.cc => cpu/o3/alpha_cpu.cc
rename : cpu/beta_cpu/alpha_full_cpu.hh => cpu/o3/alpha_cpu.hh
rename : cpu/beta_cpu/alpha_full_cpu_builder.cc => cpu/o3/alpha_cpu_builder.cc
rename : cpu/beta_cpu/alpha_full_cpu_impl.hh => cpu/o3/alpha_cpu_impl.hh
rename : cpu/beta_cpu/alpha_dyn_inst.cc => cpu/o3/alpha_dyn_inst.cc
rename : cpu/beta_cpu/alpha_dyn_inst.hh => cpu/o3/alpha_dyn_inst.hh
rename : cpu/beta_cpu/alpha_dyn_inst_impl.hh => cpu/o3/alpha_dyn_inst_impl.hh
rename : cpu/beta_cpu/alpha_impl.hh => cpu/o3/alpha_impl.hh
rename : cpu/beta_cpu/alpha_params.hh => cpu/o3/alpha_params.hh
rename : cpu/beta_cpu/bpred_unit.cc => cpu/o3/bpred_unit.cc
rename : cpu/beta_cpu/bpred_unit.hh => cpu/o3/bpred_unit.hh
rename : cpu/beta_cpu/bpred_unit_impl.hh => cpu/o3/bpred_unit_impl.hh
rename : cpu/beta_cpu/btb.cc => cpu/o3/btb.cc
rename : cpu/beta_cpu/btb.hh => cpu/o3/btb.hh
rename : cpu/beta_cpu/comm.hh => cpu/o3/comm.hh
rename : cpu/beta_cpu/commit.cc => cpu/o3/commit.cc
rename : cpu/beta_cpu/commit.hh => cpu/o3/commit.hh
rename : cpu/beta_cpu/commit_impl.hh => cpu/o3/commit_impl.hh
rename : cpu/beta_cpu/full_cpu.cc => cpu/o3/cpu.cc
rename : cpu/beta_cpu/full_cpu.hh => cpu/o3/cpu.hh
rename : cpu/beta_cpu/cpu_policy.hh => cpu/o3/cpu_policy.hh
rename : cpu/beta_cpu/decode.cc => cpu/o3/decode.cc
rename : cpu/beta_cpu/decode.hh => cpu/o3/decode.hh
rename : cpu/beta_cpu/decode_impl.hh => cpu/o3/decode_impl.hh
rename : cpu/beta_cpu/fetch.cc => cpu/o3/fetch.cc
rename : cpu/beta_cpu/fetch.hh => cpu/o3/fetch.hh
rename : cpu/beta_cpu/fetch_impl.hh => cpu/o3/fetch_impl.hh
rename : cpu/beta_cpu/free_list.cc => cpu/o3/free_list.cc
rename : cpu/beta_cpu/free_list.hh => cpu/o3/free_list.hh
rename : cpu/beta_cpu/iew.cc => cpu/o3/iew.cc
rename : cpu/beta_cpu/iew.hh => cpu/o3/iew.hh
rename : cpu/beta_cpu/iew_impl.hh => cpu/o3/iew_impl.hh
rename : cpu/beta_cpu/inst_queue.cc => cpu/o3/inst_queue.cc
rename : cpu/beta_cpu/inst_queue.hh => cpu/o3/inst_queue.hh
rename : cpu/beta_cpu/inst_queue_impl.hh => cpu/o3/inst_queue_impl.hh
rename : cpu/beta_cpu/mem_dep_unit.cc => cpu/o3/mem_dep_unit.cc
rename : cpu/beta_cpu/mem_dep_unit.hh => cpu/o3/mem_dep_unit.hh
rename : cpu/beta_cpu/mem_dep_unit_impl.hh => cpu/o3/mem_dep_unit_impl.hh
rename : cpu/beta_cpu/ras.cc => cpu/o3/ras.cc
rename : cpu/beta_cpu/ras.hh => cpu/o3/ras.hh
rename : cpu/beta_cpu/regfile.hh => cpu/o3/regfile.hh
rename : cpu/beta_cpu/rename.cc => cpu/o3/rename.cc
rename : cpu/beta_cpu/rename.hh => cpu/o3/rename.hh
rename : cpu/beta_cpu/rename_impl.hh => cpu/o3/rename_impl.hh
rename : cpu/beta_cpu/rename_map.cc => cpu/o3/rename_map.cc
rename : cpu/beta_cpu/rename_map.hh => cpu/o3/rename_map.hh
rename : cpu/beta_cpu/rob.cc => cpu/o3/rob.cc
rename : cpu/beta_cpu/rob.hh => cpu/o3/rob.hh
rename : cpu/beta_cpu/rob_impl.hh => cpu/o3/rob_impl.hh
rename : cpu/beta_cpu/sat_counter.cc => cpu/o3/sat_counter.cc
rename : cpu/beta_cpu/sat_counter.hh => cpu/o3/sat_counter.hh
rename : cpu/beta_cpu/store_set.cc => cpu/o3/store_set.cc
rename : cpu/beta_cpu/store_set.hh => cpu/o3/store_set.hh
rename : cpu/beta_cpu/tournament_pred.cc => cpu/o3/tournament_pred.cc
rename : cpu/beta_cpu/tournament_pred.hh => cpu/o3/tournament_pred.hh
rename : cpu/ooo_cpu/ooo_cpu.cc => cpu/ozone/cpu.cc
rename : cpu/ooo_cpu/ooo_cpu.hh => cpu/ozone/cpu.hh
rename : cpu/ooo_cpu/ooo_impl.hh => cpu/ozone/cpu_impl.hh
rename : cpu/ooo_cpu/ea_list.cc => cpu/ozone/ea_list.cc
rename : cpu/ooo_cpu/ea_list.hh => cpu/ozone/ea_list.hh
rename : cpu/simple_cpu/simple_cpu.cc => cpu/simple/cpu.cc
rename : cpu/simple_cpu/simple_cpu.hh => cpu/simple/cpu.hh
rename : cpu/full_cpu/smt.hh => cpu/smt.hh
rename : cpu/full_cpu/op_class.hh => encumbered/cpu/full/op_class.hh
extra : convert_revision : c4a891d8d6d3e0e9e5ea56be47d851da44d8c032
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|
--HG--
extra : convert_revision : 626aad449df9370383becb8e14f4cbf406b5b376
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inclusion of a full-fledged load/store queue. At the moment it still has some issues running, but most of the code is hopefully close to the final version.
SConscript:
arch/isa_parser.py:
cpu/base_dyn_inst.cc:
Remove OOO CPU stuff.
arch/alpha/faults.hh:
Add fake memory fault. This will be removed eventually.
arch/alpha/isa_desc:
Change EA comp and Mem accessor to be const StaticInstPtrs.
cpu/base_dyn_inst.hh:
Update read/write calls to use load queue and store queue indices.
cpu/beta_cpu/alpha_dyn_inst.hh:
Change to const StaticInst in the register accessors.
cpu/beta_cpu/alpha_dyn_inst_impl.hh:
Update syscall code with thread numbers.
cpu/beta_cpu/alpha_full_cpu.hh:
Alter some of the full system code so it will compile without errors.
cpu/beta_cpu/alpha_full_cpu_builder.cc:
Created a DerivAlphaFullCPU class so I can instantiate different CPUs that have different template parameters.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
Update some of the full system code so it compiles.
cpu/beta_cpu/alpha_params.hh:
cpu/beta_cpu/fetch_impl.hh:
Remove asid.
cpu/beta_cpu/comm.hh:
Remove global history field.
cpu/beta_cpu/commit.hh:
Comment out rename map.
cpu/beta_cpu/commit_impl.hh:
Update some of the full system code so it compiles. Also change it so that it handles memory instructions properly.
cpu/beta_cpu/cpu_policy.hh:
Removed IQ from the IEW template parameter to make it more uniform.
cpu/beta_cpu/decode.hh:
Add debug function.
cpu/beta_cpu/decode_impl.hh:
Slight updates for decode in the case where it causes a squash.
cpu/beta_cpu/fetch.hh:
cpu/beta_cpu/rob.hh:
Comment out unneccessary code.
cpu/beta_cpu/full_cpu.cc:
Changed some of the full system code so it compiles. Updated exec contexts and so forth to hopefully make multithreading easier.
cpu/beta_cpu/full_cpu.hh:
Updated some of the full system code to make it compile.
cpu/beta_cpu/iew.cc:
Removed IQ from template parameter to IEW.
cpu/beta_cpu/iew.hh:
Removed IQ from template parameter to IEW. Updated IEW to recognize the Load/Store queue.
cpu/beta_cpu/iew_impl.hh:
New handling of memory instructions through the Load/Store queue.
cpu/beta_cpu/inst_queue.hh:
Updated comment.
cpu/beta_cpu/inst_queue_impl.hh:
Slightly different handling of memory instructions due to Load/Store queue.
cpu/beta_cpu/regfile.hh:
Updated full system code so it compiles.
cpu/beta_cpu/rob_impl.hh:
Moved some code around; no major functional changes.
cpu/ooo_cpu/ooo_cpu.hh:
Slight updates to OOO CPU; still does not work.
cpu/static_inst.hh:
Remove OOO CPU stuff. Change ea comp and mem acc to return const StaticInst.
kern/kernel_stats.hh:
Extra forward declares added due to compile error.
--HG--
extra : convert_revision : 594a7cdbe57f6c2bda7d08856fcd864604a6238e
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|
SConscript:
Include new files.
arch/alpha/isa_desc:
Make the eaCompPtr and memAccPtr non-const so that execute() can be called on them.
arch/alpha/isa_traits.hh:
Add enum for total number of data registers.
arch/isa_parser.py:
base/traceflags.py:
Include new light-weight OoO CPU model.
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
Changes to abstract more away from the base dyn inst class.
cpu/beta_cpu/2bit_local_pred.cc:
cpu/beta_cpu/2bit_local_pred.hh:
cpu/beta_cpu/tournament_pred.cc:
cpu/beta_cpu/tournament_pred.hh:
Remove redundant SatCounter class.
cpu/beta_cpu/alpha_dyn_inst.cc:
cpu/beta_cpu/alpha_full_cpu.cc:
cpu/beta_cpu/alpha_full_cpu.hh:
cpu/beta_cpu/bpred_unit.cc:
cpu/beta_cpu/inst_queue.cc:
cpu/beta_cpu/mem_dep_unit.cc:
cpu/beta_cpu/ras.cc:
cpu/beta_cpu/rename_map.cc:
cpu/beta_cpu/rename_map.hh:
cpu/beta_cpu/rob.cc:
Fix for gcc-3.4
cpu/beta_cpu/alpha_dyn_inst.hh:
cpu/beta_cpu/alpha_dyn_inst_impl.hh:
Fixes for gcc-3.4.
Include more variables and functions that are specific to AlphaDynInst which were once in BaseDynInst.
cpu/beta_cpu/alpha_full_cpu_builder.cc:
Make params match the current params inherited from BaseCPU.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
Fixes for gcc-3.4
cpu/beta_cpu/full_cpu.cc:
Use new params pointer in BaseCPU.
Fix for gcc-3.4.
cpu/beta_cpu/full_cpu.hh:
Use new params class from BaseCPU.
cpu/beta_cpu/iew_impl.hh:
Remove unused function.
cpu/simple_cpu/simple_cpu.cc:
Remove unused global variable.
cpu/static_inst.hh:
Include OoODynInst for new lightweight OoO CPU
--HG--
extra : convert_revision : 34d9f2e64ca0313377391e0d059bf09c040286fa
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|
--HG--
extra : convert_revision : 86c7399b79c17558041a73056745227f70fe8b3b
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|
address calculation and memory access portions separately.
Not currently used by any CPU models, but Kevin says he needs this.
Also clean up handling of execution tracing for memory accesses
(move it all into isa_desc and out of CPU models).
Got rid of some ancient unused code too.
arch/alpha/isa_desc:
Add execute() methods to EAComp and MemAcc portions of memory
access instructions, to allow CPU models to execute the effective
address calculation and memory access portions separately.
Requires the execution context to remember the effective address
across the two invocations. Added setEA() and getEA() methods to
execution context to support this. A model that does not use the
split execution model can panic if these methods are called.
Also added hook to call traceData->setAddr() after EA computation
on any load or store operation.
arch/isa_parser.py:
Call traceData->setData() on memory writes (stores).
cpu/simple_cpu/simple_cpu.cc:
Get rid of unused code.
cpu/simple_cpu/simple_cpu.hh:
Add (non-functional) setEA() and getEA() methods for new
split memory access execution support.
--HG--
extra : convert_revision : bc2d2c758c4ca753812b9fa81f21038e55929ff0
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|
base/traceflags.py:
Merge extra new CPU flags
cpu/static_inst.hh:
Include all the execute functions in static_inst_impl.hh
--HG--
extra : convert_revision : 78eb753bf709d37400e7c2418bb35d842d7c3f63
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|
SConscript:
arch/isa_parser.py:
cpu/static_inst.hh:
Add inorderCPU
--HG--
extra : convert_revision : 141372808fac5f6d125f9051ee0be982d21683aa
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|
Also change to ref counted DynInst.
SConscript:
Add branch predictor, BTB, load store queue, and storesets.
arch/isa_parser.py:
Specify the template parameter for AlphaDynInst
base/traceflags.py:
Add load store queue, store set, and mem dependence unit to the
list of trace flags.
cpu/base_dyn_inst.cc:
Change formating, add in debug statement.
cpu/base_dyn_inst.hh:
Change DynInst to be RefCounted, add flag to clear whether or not this
instruction can commit. This is likely to be removed in the future.
cpu/beta_cpu/alpha_dyn_inst.cc:
AlphaDynInst has been changed to be templated, so now this CC file
is just used to force instantiations of AlphaDynInst.
cpu/beta_cpu/alpha_dyn_inst.hh:
Changed AlphaDynInst to be templated on Impl. Removed some unnecessary
functions.
cpu/beta_cpu/alpha_full_cpu.cc:
AlphaFullCPU has been changed to be templated, so this CC file is now
just used to force instantation of AlphaFullCPU.
cpu/beta_cpu/alpha_full_cpu.hh:
Change AlphaFullCPU to be templated on Impl.
cpu/beta_cpu/alpha_impl.hh:
Update it to reflect AlphaDynInst and AlphaFullCPU being templated
on Impl. Also removed time buffers from here, as they are really
a part of the CPU and are thus in the CPU policy now.
cpu/beta_cpu/alpha_params.hh:
Make AlphaSimpleParams inherit from the BaseFullCPU so that it doesn't
need to specifically declare any parameters that are already in the
BaseFullCPU.
cpu/beta_cpu/comm.hh:
Changed the structure of the time buffer communication structs. Now
they include the size of the packet of instructions it is sending.
Added some parameters to the backwards communication struct, mainly
for squashing.
cpu/beta_cpu/commit.hh:
Update typenames to reflect change in location of time buffer structs.
Update DynInst to DynInstPtr (it is refcounted now).
cpu/beta_cpu/commit_impl.hh:
Formatting changes mainly. Also sends back proper information
on branch mispredicts so that the bpred unit can update itself.
Updated behavior for non-speculative instructions (stores, any
other non-spec instructions): once they reach the head of the ROB,
the ROB signals back to the IQ that it can go ahead and issue the
non-speculative instruction. The instruction itself is updated so that
commit won't try to commit it again until it is done executing.
cpu/beta_cpu/cpu_policy.hh:
Added branch prediction unit, mem dependence prediction unit, load
store queue. Moved time buffer structs from AlphaSimpleImpl to here.
cpu/beta_cpu/decode.hh:
Changed typedefs to reflect change in location of time buffer structs
and also the change from DynInst to ref counted DynInstPtr.
cpu/beta_cpu/decode_impl.hh:
Continues to buffer instructions even while unblocking now. Changed
how it loops through groups of instructions so it can properly block
during the middle of a group of instructions.
cpu/beta_cpu/fetch.hh:
Changed typedefs to reflect change in location of time buffer structs
and the change to ref counted DynInsts. Also added in branch
brediction unit.
cpu/beta_cpu/fetch_impl.hh:
Add in branch prediction. Changed how fetch checks inputs and its
current state to make for easier logic.
cpu/beta_cpu/free_list.cc:
Changed int regs and float regs to logically use one flat namespace.
Future change will be moving them to a single scoreboard to conserve
space.
cpu/beta_cpu/free_list.hh:
Mostly debugging statements. Might be removed for performance in future.
cpu/beta_cpu/full_cpu.cc:
Added in some debugging statements. Updated BaseFullCPU to take
a params object.
cpu/beta_cpu/full_cpu.hh:
Added params class within BaseCPU that other param classes will be
able to inherit from. Updated typedefs to reflect change in location
of time buffer structs and ref counted DynInst.
cpu/beta_cpu/iew.hh:
Updated typedefs to reflect change in location of time buffer structs
and use of ref counted DynInsts.
cpu/beta_cpu/iew_impl.hh:
Added in load store queue, updated iew to be able to execute non-
speculative instructions, instead of having them execute in commit.
cpu/beta_cpu/inst_queue.hh:
Updated change to ref counted DynInsts. Changed inst queue to hold
non-speculative instructions as well, which are issued only when
commit signals backwards that a nonspeculative instruction is at
the head of the ROB.
cpu/beta_cpu/inst_queue_impl.hh:
Updated to allow for non-speculative instructions to be in the inst
queue. Also added some debug functions.
cpu/beta_cpu/regfile.hh:
Added debugging statements, changed formatting.
cpu/beta_cpu/rename.hh:
Updated typedefs, added some functions to clean up code.
cpu/beta_cpu/rename_impl.hh:
Moved some code into functions to make it easier to read.
cpu/beta_cpu/rename_map.cc:
Changed int and float reg behavior to use a single flat namespace. In
the future, the rename maps can be combined to a single rename map to
save space.
cpu/beta_cpu/rename_map.hh:
Added destructor.
cpu/beta_cpu/rob.hh:
Updated it with change from DynInst to ref counted DynInst.
cpu/beta_cpu/rob_impl.hh:
Formatting, updated to use ref counted DynInst.
cpu/static_inst.hh:
Updated forward declaration for AlphaDynInst now that it is templated.
--HG--
extra : convert_revision : 1045f240ee9b6a4bd368e1806aca029ebbdc6dd3
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caches.
SConscript:
Added new CPU files to build.
arch/alpha/isa_desc:
Changed rduniq and wruniq to be nonspeculative because the uniq register is not renamed.
arch/isa_parser.py:
Added new CPU exec method.
base/statistics.hh:
Minor change for namespace conflict. Probably can change back one the new CPU files are cleaned up.
base/traceflags.py:
Added new CPU trace flags.
cpu/static_inst.hh:
Changed static inst to use a file that defines the execute functions.
--HG--
extra : convert_revision : bd4ce34361308280168324817fc1258dd253e519
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|
Got rid of two inconsistent sets of strings that corresponded
to this enum, and replaced with a single set that clearly
matches the enum names.
arch/alpha/isa_desc:
arch/isa_parser.py:
cpu/full_cpu/op_class.hh:
Renamed OpClass enum members.
--HG--
extra : convert_revision : bf596f7568a20b2e77c07ac349f253135141aef4
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|
arch/alpha/ev5.cc:
Updated to support new forms of setIntReg and setFloatRegDouble. Will need to be cleaned up in the future.
arch/isa_parser.py:
Added in FastCPU model.
--HG--
extra : convert_revision : 384a27efcb50729ea6c3cc11653f395c300e48db
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|
instruction execute methods. Register i now means the instruction's
i'th src (or dest) operand, not architectural register i. Current
models that use the architectural reg index can look that up easily
in the instruction object. Future models that do register renaming
should find this much simpler to deal with.
arch/isa_parser.py:
Generate register accessors with an extra level of indirection.
cpu/simple_cpu/simple_cpu.hh:
Modify register accessors to use an extra level of indirection.
--HG--
extra : convert_revision : f4c7d6bfa92fb2ea6251f31ee368809c3643f08f
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|
out CPU model. ISA description now generates multiple
output source files to (in theory) reduce compilation time.
arch/alpha/isa_desc:
Update for parser changes. Move most constructors
out of class declarations (which are now in decoder.hh)
and into decoder.cc. Move all execute() methods into
exec output.
arch/isa_parser.py:
Significant changes to make ISA description completely
independent of CPU model, and isolate model-dependent parts
of parser into one little class (CpuModel). Also split up code
output into multiple files (a header, a main source file, and
per-cpu execute() method files).
Noticeable changes to language as a result. See updated Doxygen
documentation.
cpu/simple_cpu/simple_cpu.hh:
SimpleCPUExecContext typedef no longer needed.
Add forward declaration of Process.
cpu/static_inst.hh:
SimpleCPUExecContext and FullCPUExecContext typedefs no longer needed.
Make eaCompInst() and memAccInst() return const refs.
--HG--
extra : convert_revision : 71471f267804fafd0a881bac7445677e76334daf
|
|
(Still not perfect though.)
arch/alpha/isa_desc:
Do a better job of factoring out CPU model. (Still not perfect though.)
Pull execute() methods out of class declarations into separate section
of file, allowing (1) easier replication for different CPU models and
(2) a path to putting them all in a separate file. Force all instruction
execution context into a single model-dependent class (SimpleCPU itself
for SimpleCPU, DynInst for FullCPU).
arch/isa_parser.py:
Do a better job of factoring out CPU model. (Still not perfect though.)
Pull execute() methods out of class declarations into separate section
of file, allowing (1) easier replication for different CPU models and
(2) a path to putting them all in a separate file.
Also restructure top level to allow parser to run under interactive
interpreter session for easier debugging.
cpu/exec_context.hh:
Add a few new methods to clean up isa_desc.
cpu/simple_cpu/simple_cpu.cc:
cpu/static_inst.hh:
StaticInst::execute no longer takes a CPU and an ExecContext,
just a unified FooCPUExecContext.
cpu/simple_cpu/simple_cpu.hh:
Add methods to redirect calls to ExecContext so SimpleCPU
can act as sole instruction execution context for itself.
Typedef SimpleCPU to SimpleCPUExecContext.
--HG--
extra : convert_revision : ecc445503bc585585da5663fe61796580e744da6
|
|
arch/isa_parser.py:
Fix include path (bitfield.hh -> base/bitfield.hh).
--HG--
extra : convert_revision : 2ce02d0a5986694a6a6ebcab1e5e0a306d6e5a49
|
|
arch/isa_parser.py:
Add attribution to license generated into decoder.cc
--HG--
extra : convert_revision : dc309fc0035e5a1f2d7216d3feda8e3c1225f917
|
|
Change mode to -rwxrwxr-x
--HG--
extra : convert_revision : da836f2f901c9f80563f9022a057315836d50482
|
|
Doxyfile:
LICENSE:
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/arguments.cc:
arch/alpha/arguments.hh:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/fake_syscall.cc:
arch/alpha/faults.cc:
arch/alpha/faults.hh:
arch/alpha/isa_desc:
arch/alpha/isa_traits.hh:
arch/alpha/osfpal.cc:
arch/alpha/osfpal.hh:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
arch/isa_parser.py:
base/bitfield.hh:
base/callback.hh:
base/circlebuf.cc:
base/circlebuf.hh:
base/cprintf.cc:
base/cprintf.hh:
base/cprintf_formats.hh:
base/date.cc:
base/dbl_list.hh:
base/endian.hh:
base/fast_alloc.cc:
base/fast_alloc.hh:
base/fifo_buffer.cc:
base/fifo_buffer.hh:
base/hashmap.hh:
base/inet.cc:
base/inet.hh:
base/inifile.cc:
base/inifile.hh:
base/intmath.cc:
base/intmath.h:
base/kgdb.h:
base/misc.cc:
base/misc.hh:
base/mod_num.hh:
base/object_file.cc:
base/object_file.hh:
base/pollevent.cc:
base/pollevent.hh:
base/random.cc:
base/random.hh:
base/range.hh:
base/refcnt.hh:
base/remote_gdb.cc:
base/remote_gdb.hh:
base/res_list.hh:
base/sched_list.hh:
base/socket.cc:
base/socket.hh:
base/statistics.cc:
base/statistics.hh:
base/str.cc:
base/str.hh:
base/symtab.cc:
base/symtab.hh:
base/trace.cc:
base/trace.hh:
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/console.cc:
dev/console.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.cc:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/pcireg.h:
dev/simple_disk.cc:
dev/simple_disk.hh:
kern/tru64/tru64.hh:
kern/tru64/tru64_syscalls.cc:
kern/tru64/tru64_syscalls.hh:
sim/async.hh:
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/cache/lzss_compression.cc:
sim/cache/lzss_compression.hh:
sim/cache/null_compression.hh:
sim/debug.cc:
sim/debug.hh:
sim/eventq.cc:
sim/eventq.hh:
sim/exec_context.cc:
sim/exec_context.hh:
sim/exetrace.cc:
sim/exetrace.hh:
sim/host.hh:
sim/hybrid_pred.cc:
sim/hybrid_pred.hh:
sim/intr_control.cc:
sim/intr_control.hh:
sim/main.cc:
sim/memtest.cc:
sim/memtest.hh:
sim/op_class.hh:
sim/param.cc:
sim/param.hh:
sim/pc_event.cc:
sim/pc_event.hh:
sim/predictor.hh:
sim/prog.cc:
sim/prog.hh:
sim/sat_counter.cc:
sim/sat_counter.hh:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_events.cc:
sim/sim_events.hh:
sim/sim_exit.hh:
sim/sim_object.cc:
sim/sim_object.hh:
sim/sim_time.cc:
sim/sim_time.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
sim/smt.hh:
sim/static_inst.cc:
sim/static_inst.hh:
sim/std_types.hh:
sim/system.cc:
sim/system.hh:
sim/universe.cc:
test/Makefile:
test/bitvectest.cc:
test/circletest.cc:
test/cprintftest.cc:
test/foo.ini:
test/initest.cc:
test/initest.ini:
test/lru_test.cc:
test/nmtest.cc:
test/offtest.cc:
test/paramtest.cc:
test/rangetest.cc:
test/sized_test.cc:
test/stattest.cc:
test/strnumtest.cc:
test/symtest.cc:
test/tokentest.cc:
test/tracetest.cc:
util/rundiff:
util/tap/Makefile:
util/tap/tap.cc:
util/term/Makefile:
util/term/term.c:
RCS to BitKeeper
sim/main.cc:
Initial revision
sim/main.cc:
Added base SMT support to SS3 distribution
sim/main.cc:
Corrected statistics in sim-smt
Added "cnt_*" statistics to sim-smt and sim-outorder
Added execution tracing to sim-outorder
sim/main.cc:
Numerous minor fixes.
Implemented Ideal and Random fetch policies.
Numerous new statistics.
sim/main.cc:
A few minor bug fixes to collapsing RUU & "ideal" fetch policy.
sim/main.cc:
Snapshot of MICRO99 work in progress. Lots of SMT stuff, EIO fixes, etc.
sim/main.cc:
-> New fetch stage:
- Fetch a block at a time
- Execute in fetch
-> Removed execute from ruu_dispatch()
-> Cleaned up
sim/main.cc:
Added build time-stamp to top of simulation log
sim/main.cc:
Corrected error in priority rotation routine
Added -max:mult option
Modified makefile to use egcs compiler
Added the -t option bkdwn.pl
sim/main.cc:
Added memory usage display
Fixed #define for number of RS_LINKs
sim/main.cc:
Should be able to build other simulators (sim-fast, sim-eio, etc.) using
"make -f Makefile.orig" (for Alpha at least, not quite for PISA).
sim/main.cc:
More SMT vs. non-SMT cleanup: 'make sim-X' now works for most X.
sim/main.cc:
Changed function of Fetch/Decode/Dispatch pipe:
a) Fetch only if room in fetch queue
b) Decode only if pipe advanced as a result of dispatching a packet
c) Dispatch a packet only if:
1) Room for all insns in RUU
2) Room for all insns in LSQ
3) Room for all insns in INT Register File
4) Room for all insns in FP Register File
Added ROB structure
a) Instruction is placed in RUU & ROB at dispatch
b) Instruction is removed from RUU at writeback (except stores)
c) Instruction is removed from ROB at commit
Added support for counting physical register usage (INT and FP)
a) subtract from "free" count at dispatch
b) add back when instruction is removed from ROB
Added "my_index" field to RUU_station (simplifies reverse-lookups)
Removed all remaining ptrace stuff
RUU & LSQ now dump squashed instructions instead of marking them squashed
- No cost!
Reworked commit stage to use ROB instea
sim/main.cc:
- Added sc_dist1 stat type as a user-transparent special case of distribution
with unit-size buckets: saves an unnecessary divide on every sample
- Minor changes to compile as C++ code
base/fast_alloc.cc:
base/fast_alloc.hh:
Major reorganization. Split sim-smt.c into multiple files, compile with C++,
split ROB & RUU structures, numerous small formatting and performance changes.
sim/eventq.cc:
sim/eventq.hh:
- Replaced SimpleScalar event queue code with smt_eventq.{cc,hh}
- Eliminated unused cache:flush option
- Initialize bpred history regs and BTB and RAS entries to provide
repeatable results
- Added reset_spec_state() function: cleans up interface to spec_state.c
sim/eventq.cc:
sim/eventq.hh:
Major reorganization of memory-system code and interface.
base/fast_alloc.cc:
sim/eventq.cc:
sim/eventq.hh:
Moved C++ files to .cc/.hh, compile C files with C compiler.
base/dbl_list.hh:
Initial check-in: doubly-linked list template class.
sim/eventq.hh:
Added when_created and when_scheduled time-tags for debugging
base/fast_alloc.hh:
Plug memory leak
sim/eventq.cc:
Runahead_Prefetch memory-system support, including miss notification
events in cache.
sim/eventq.cc:
sim/eventq.hh:
Merged branch "mt-frontend" into trunk of CVS tree
Changes include:
Multi-threaded Fetch & Decode
Correct functionality of branch misprediction fixup (MT only)
Improved stats
base/intmath.cc:
base/intmath.h:
Integer math functions.
base/fast_alloc.cc:
base/fast_alloc.hh:
Remove carriage returns.
base/intmath.h:
Add Min/Max template functions
sim/prog.cc:
sim/prog.hh:
Adding smt-safe and smt-fast. These are functional simulators based on
sim-safe and sim-fast. Despite their names, they do not actually don't
handle multithreaded programs yet. The runfile functionality was
pulled out of sim-smt.cc into its own files. This allows all three
simulators to use runfiles.
NOTE: There is a lot of duplicated code in these three simulators that
should probably be separated out. The macro type definitions in engin.hh
are similar to the definitions in smt-safe.cc and smt-fast.cc
sim/prog.cc:
Add support for loading a kernel with simplescalar. Also add skeleton for
loading a disk image to boot from with simplescalar.
Hook for loading palcode is in place, but not implemented.
Initial parameters passed to kernel at boot time are not passed properly.
sim/prog.cc:
Only support loading kernel/disk image if we're running FULL_SYSTEM
sim/prog.cc:
Make loading PAL a separate operation. Also separate kernel loading and
disk loading so that it can only be done in FULL_SYSTEM. Finally, we need
to also load the console image file. I'm not sure what's in there, maybe
some stuff from SRM, but it's needed for proper execution.
dev/alpha_console.cc:
dev/alpha_console.hh:
Console device implementation from simos. This is a simple device that
supports the necessary console functions for booting.
sim/prog.cc:
sim/prog.hh:
Separate the kernel loader and the program loader for simplicity since they
don't share much code.
arch/alpha/alpha_memory.hh:
Add this somewhat gross hack to take care of the fact that alpha has the
this load locking and conditional store mechanism.
sim/prog.cc:
Enable asids again. This makes multithreaded programs work again.
I guess you could say that this was an accidental commit. Sorry
sim/main.cc:
Clean up Simplescalar copyright notice.
sim/prog.cc:
Allow '-' for stdout as well as stdin in run file.
dev/alpha_console.cc:
dev/alpha_console.hh:
sim/prog.cc:
arch/alpha/alpha_memory.hh:
Replace the interface to the memory system. Basically this change goes
away from the model of passing an address, and a number of bytes and
getting/setting data. This change rather creates a memory_request packet
(a simple struct) that bundles all of the necessary information together
to pass into the memory system when making a request. This makes the
function call syntax consistent even when you have virtual to physical
translation and when you have strange flags like locked, or physical that
you need to pass to your memory system. It has the added benefit of allowing
the layers to pass data to each other, possibly skipping layers in between.
This was necessary for the whacked out behavior that store conditional has
on alpha.
In addition, the entire memory system is now consistent in that it will return
an alignment fault due to an unaligned access. This is necessary to properly
model a full alpha system, but changes the behavior of bogus bad path loads
and stores that access unaligned data. Because
base/fast_alloc.cc:
base/fast_alloc.hh:
Major enhancement of FastAlloc debug code (uncomment #define in
fast_alloc.hh to enable). Can now dump summary of in-use objects
by type and address/type of oldest n objects (thank you RTTI!).
Should be easier to identify memory leaks now.
base/res_list.hh:
file res_list.hh was initially added on branch segmented_iq.
sim/sat_counter.hh:
file sat_counter.hh was initially added on branch segmented_iq.
sim/std_types.hh:
file std_types.hh was initially added on branch segmented_iq.
base/fast_alloc.hh:
base/res_list.hh:
sim/sat_counter.hh:
sim/eventq.cc:
sim/eventq.hh:
sim/prog.cc:
sim/std_types.hh:
Merged branch "segmented_iq"
-> Objectized the IQ and LSQ
-> Implemented Standard, Sezned, and Segmented IQ's
-> Major fixes to wrong-path execution (primarily involving data dependencies)
base/res_list.hh:
g++ is braindead, so I cannot pull template functions out into a .cc file.
Instead, pull large functions out of the class definition and inline them.
This leads to a much more readable class definition.
In addition, since these functions are inlined, youseems to be what is
intended anyway.
sim/prog.cc:
Move some variables to smt_prog so that targets other than sim-smt can use
them.
sim/main.cc:
remove the dlite debugger (for smt at least)
dev/alpha_console.cc:
sim/eventq.cc:
sim/main.cc:
I knew I had done this for a reason
Change 64 bit types back to long for alpha and replace all instances
of stuff like %lld to use FMT64d and the like.
The reason this is necessary is because TRU64 does not understand what
%lld is and will print out "ld" instead of actually printing the
number.
So, PLEASE use the FMTxxx stuff instead of sticking %lld, %llx, %016llx
and such into the code.
sim/main.cc:
Don't want FMT64d for things declared 'long': this doesn't work when
FMT64d evaluates to "%lld". Just use "%ld" instead.
dev/console.cc:
dev/console.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/pcireg.h:
dev/simple_disk.cc:
dev/simple_disk.hh:
Add several initial devices for full alpha system simulation.
Many of these devices are based on SimOS devices
dev/alpha_console.cc:
dev/alpha_console.hh:
Update the alpha_console to take advantage of the simple disk interface
sim/eventq.cc:
sim/eventq.hh:
Make it so you can service events that will happen in the future
base/trace.cc:
base/trace.hh:
This is a simple tracing facility.
The idea is that there is a bitvector where each bit represents something
that you may want to trace. The end result is that you can at runtime
turn on and off different tracing statements in the code so that you
only see messages for things that you care about.
This is only currently used in the devices framework, but I would like
to see it eventually replace the debug, warn, and info functions.
sim/intr_control.hh:
Initial abstraction for a processor and interrupt controller
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
Add full support for the SYSTEM_EV5 model in smt-safe. With this model, the
user should be able to boot Tru64 unix.
Several aspects of the memory subsystem were changed to accomidate this
ability:
- The C memory access functions no longer return an md_fault_type.
- The prot_* functions no longer take a memrequest, and no longer return
an md_fault type. They now take a single address and a size. This is
because the prot_* functions don't need translation abilities, etc.
- The prot_* functions will by default fail to work unless they are
specifically implemented for the class that you want to use them with.
- The unaligned parameter to the READ_* and WRITE_* function calls was added
back so that exceptions that occur on STQ_U, LDQ_U, etc get the proper
faulting address.
- The memory controller now supports adding an arbitrary number of objects
at arbitrary memory ranges so that a variety of devices can be accomidated.
- The physical_memory class now not only emulates a specific amount of memor
base/trace.cc:
Check for existence of environment variable
dev/console.cc:
Temporary fix to get this to compile under Linux.
sim/main.cc:
Flush stdout before dumping stats.
sim/exec_context.cc:
sim/exec_context.hh:
sim/exetrace.cc:
sim/exetrace.hh:
sim/main.cc:
sim/prog.cc:
sim/prog.hh:
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/fake_syscall.cc:
Pull per-cpu variables into cpu_t object as first step toward multiprocessor
support. Also encapsulated execution context into a single object.
Program loading code also significantly reorganized.
Syscall redirection to host machine temporarily broken (must use EIO
files for now).
arch/alpha/fake_syscall.cc:
sim/eventq.cc:
sim/exec_context.cc:
sim/exetrace.cc:
sim/main.cc:
sim/prog.cc:
Update source tree to deal with shuffling of files and renaming of files.
Maybe a tiny bit of style here and there for kicks too.
sim/prog.cc:
Fix more stuff for reorg.
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/fake_syscall.cc:
base/dbl_list.hh:
base/fast_alloc.cc:
base/fast_alloc.hh:
base/intmath.cc:
base/intmath.h:
base/res_list.hh:
base/trace.cc:
base/trace.hh:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/console.cc:
dev/console.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/pcireg.h:
dev/simple_disk.cc:
dev/simple_disk.hh:
sim/main.cc:
sim/eventq.cc:
sim/eventq.hh:
sim/exec_context.cc:
sim/exec_context.hh:
sim/exetrace.cc:
sim/exetrace.hh:
sim/intr_control.hh:
sim/prog.cc:
sim/prog.hh:
sim/sat_counter.hh:
sim/std_types.hh:
Some style changes
remove all of the $Log$ crap
add $Id$ strings to the top of all files.
arch/alpha/alpha_memory.cc:
Convert memory request objects to have a bitvector of flags.
sim/sat_counter.hh:
Minor bug-fixes to statistics & options
Saturating counter wasn't initializing properly
arch/alpha/fake_syscall.cc:
Compile on OpenBSD
base/fast_alloc.cc:
dev/console.cc:
dev/disk_image.cc:
sim/eventq.cc:
sim/eventq.hh:
sim/exec_context.hh:
sim/exetrace.cc:
sim/exetrace.hh:
sim/intr_control.hh:
sim/prog.cc:
sim/sat_counter.hh:
Move extern "C" statements out of C++ files and into the C headers with
#ifdef __cplusplus guarding the extern.
base/str.cc:
base/str.hh:
My lame old reference counting string class. It's really not too bad.
base/intmath.cc:
removed unused variable
sim/main.cc:
add option -inifile to load the config file
base/inifile.cc:
base/inifile.hh:
sim/main.cc:
rename configfile to inifile
base/intmath.h:
Functions to determine if a character is hex, dec, oct.
Convert hex to int
base/str.cc:
base/str.hh:
Add a tokenize function.
Fix a bug in the CopyRight function
Add a const iterator
Add a string to number function that will deal with hex, decimal, octal,
positive numbers and a few suffixes. Complete with bounds checking and
syntax checking
base/inifile.cc:
base/inifile.hh:
Cope with fix in CopyRight function from the String class.
Add a find default which whill check for a Default= parameter.
Add #include guards
dev/alpha_console.cc:
style. change assertion
sim/sat_counter.hh:
Added instruction-type identification methods to dyn_inst
Continued work on the segmented IQ:
- Stats
- Seg0 load mechanisms
- "short" dump function
- free_slots_last_cycle model improvement
Added stats to sat_counter
sim/main.cc:
Parse .ini file for options in main.cc.
sim/main.cc:
Reindent following style guide.
sim/sat_counter.hh:
Updates to the segmented IQ
sim/hybrid_pred.hh:
Initial check-in
sim/predictor.hh:
Initial check-in of predictor
Mods to predictor stats
sim/hybrid_pred.hh:
sim/predictor.hh:
sim/sat_counter.hh:
Class heirarchy fixes
sim/predictor.hh:
sim/sat_counter.hh:
Now the predictors actually work!
sim/sat_counter.hh:
Final fixes to the SaturatingCounterPred
Corrections to the LRP and HMP
sim/sat_counter.hh:
Bug fixes and predictor mods to segmented IQ during ISCA-2002 work
Dumping of queue contents is a little more flexible for debugging
arch/alpha/fake_syscall.cc:
sim/prog.cc:
Updated fake syscall support (for most common syscalls) so we can
once again run straight binaries (not just EIO files).
sim/sat_counter.hh:
Final updates (for now) to the Segmented IQ
Cleaning up the fetch stage
Speed improvements to the Saturating Counter Predictor Object
sim/prog.cc:
sim/prog.hh:
Fix parameter bug in process_t::dup_fd (causing stdio fd's not to get
remapped correctly).
base/str.hh:
Add forward decl of class ostream
base/inifile.cc:
base/inifile.hh:
Rename members to conform to common style.
base/inifile.cc:
Oops... looks like CPP_PIPE doesn't work.
sim/main.cc:
sim/sat_counter.hh:
sim/sim_object.cc:
sim/sim_object.hh:
New configuration scheme based on .ini files and hierarchical descriptions.
Currently in a transitional state: only sim_smt CPU, IQ, Cache, Bus, and
Mem objects are configured this way. Old mmodel.{hh,cc} completely gone.
base/inifile.cc:
Fix pipe directionality for Linux: CPP_PIPE works again.
sim/sim_object.cc:
Updates for INI-file parameters for Seznec and Segmented IQ models
Fixed naming of IQ classes
sim/sim_object.cc:
sim/sim_object.hh:
- Minor revisions to ParamContext, SimObjectBuilder, etc. to allow creation
of SimObjects outside of configuration hierarchy.
- Encapsulated magic boilerplate for object creation in macros to simplify
usage and make future changes like this simpler.
arch/alpha/fake_syscall.cc:
sim/exec_context.cc:
sim/exec_context.hh:
sim/prog.cc:
sim/prog.hh:
Rename process_t --> Process, eio_process_t -> EioProcess,
live_process_t -> LiveProcess
base/str.cc:
base/str.hh:
flesh out string class
base/str.cc:
This time commit the right file.
base/str.cc:
fix Tokenize for the case where the last string is only a single character
sim/sim_object.cc:
Instantiate Param<String>::showValue().
sim/sim_object.cc:
sim/sim_object.hh:
- Auto-register global parameter contexts for non-SimObject parameters
- added ParamContext::parseAllContexts()
- Finish and test enum params (SimpleEnumParam, MappedEnumParam)
- Add vector-valued parameters: VectorParam<T>, SimObjectVectorParam,
SimpleEnumVectorParam, MappedEnumVectorParam
- Factor parsing & displaying functions to share code between scalar
and vector parameter objects
- Fix bug where a SimObjectClass constructor could be called before
the static SimObjectClass::classMap constructor
- Add "help" functions to dump parameter descriptions
(ParamContext::describeAllContexts() and
SimObjectClass::describeAllClasses())
sim/main.cc:
Dump out config file parameters on '-h' cmd-line argument.
sim/sim_object.cc:
sim/sim_object.hh:
- Add showType() method to display parameter type as string for help
- Change EnumParam types to include specific enum type (avoids casting)
sim/sim_object.hh:
Minor updates for statistics, new compilers, etc.
Moved some options into new options model
base/inifile.cc:
base/inifile.hh:
sim/exetrace.cc:
sim/exetrace.hh:
sim/main.cc:
sim/param.cc:
sim/param.hh:
sim/prog.cc:
sim/prog.hh:
sim/sim_object.cc:
sim/sim_object.hh:
Eliminated old SimpleScalar options package from sim_smt, shifting
everything over to new parameter objects fed by .ini-style
configuration files. Parameters can be set on command line using
'--<sec>:<param>=<value>'. All other cmd-line options are assumed
to be config file names, except '-h' prints help msg.
Got rid of *_reg_options(), *_check_options(), *_uninit() calls.
Moved more initialization into constructors; remaining code is now
automagically executed by providing checkParams() and cleanup()
methods on ParamContext-derived objects. (See exetrace.cc, for
example.)
Runfile is gone; processes are initialized as simulation objects.
Split parameter code out of sim_object.{cc,hh} into param.{cc,hh}.
Moved a bunch of CPU object methods from sim_smt.cc to cpu.cc.
smt_reg_stats calls now need to know number of threads. Can be done
by explicit argument to global function, or (for backward
compatibility) calling CPU object method with same parameters as old
global function.
Renamed "SimControl" par
base/circlebuf.cc:
base/circlebuf.hh:
Add a circular buffer class that holds string data.
You can set the size of the buffer, and basically keep writing to it,
and later read the last size bytes from the buffer. kinda like tail -f
test/Makefile:
test/bitvectest.cc:
test/circletest.cc:
test/foo.ini:
test/initest.cc:
test/initest.ini:
test/strnumtest.cc:
test/tokentest.cc:
Add a little bit of test framework and a bunch of initial tests
test/paramtest.cc:
Move the param test thing to the new test framework, though it doesn't
compile right now since I couldn't figure it out
base/inifile.cc:
Disable pipes for cpp: hangs if cpp output is bigger than kernel pipe buffer.
sim/sim_object.cc:
Check for accidental redefinition of SimObject class names.
base/str.cc:
Support exponents in StringToNumber.
It should be noted, that while StringToNumber does bounds checking,
the bounds checking has not been mathmatically proven, so it could
have mistakes.
base/range.hh:
Simple range class that will parse a range and provides comparison
operators
base/trace.hh:
New tracing options
test/Makefile:
test/rangetest.cc:
add a new test for the Range class
sim/exetrace.cc:
sim/exetrace.hh:
sim/main.cc:
Create an ExecutionTrace class that encapsulates the old exe_trace stuff.
Convert the last of the old options stuff to the new params and get rid
of the old options files.
Get rid of the old range files.
arch/alpha/fake_syscall.cc:
Stupid linuxisms
sim/main.cc:
sim/sim_object.cc:
Output config info to cerr instead of cout.
sim/main.cc:
Load default.ini if the file exists
test/Makefile:
test/bitvectest.cc:
test/circletest.cc:
test/initest.cc:
test/paramtest.cc:
test/rangetest.cc:
test/strnumtest.cc:
test/tokentest.cc:
Add Id tags
sim/sim_object.cc:
Bug fix to allow use of "default=" in ini-files
sim/prog.cc:
Fix for wacky compiler bug
base/inifile.cc:
Modified some ROB statistic labels to make them more uniform
Re-implimented rob-caps
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
Add support for doing virtual to physical translation using the in-memory
page table
base/kgdb.h:
base/remote_gdb.cc:
base/remote_gdb.hh:
Basic support for remote debugging
base/pollevent.cc:
base/pollevent.hh:
A class abstraction for poll
base/socket.cc:
base/socket.hh:
Support for tcp server sockets
base/symtab.cc:
base/symtab.hh:
simple symbol table loaded from a preprocessed file
dev/alpha_access.h:
dev/alpha_console.hh:
split alpha access into a separate file so that building console code is
simpler
dev/disk_image.cc:
dev/disk_image.hh:
use a string for the disk image file name instead of a char *
arch/alpha/alpha_memory.cc:
Make the MCSR segment check more explicit
rearrange
base/trace.cc:
Make trace stuff use new parameter stuff
base/trace.hh:
Fix DPRINTF and DPRINTFN macros
Add a few new trace flags
sim/exetrace.cc:
sim/exetrace.hh:
Add more features to the exetrace stuff.
Make use of the symbol table support.
base/remote_gdb.cc:
fix DPRINTFs
dev/alpha_console.cc:
dev/console.cc:
dev/console.hh:
Change the console framework to use the new pollevent stuff.
This adds support for a console that can be attached and detached at runtime
via a tcp connection (telnet). There is also a circular buffer integrated
into the console so that upon connection, any missed console text is output
to the console.
In the future, this should easily allow for multiple system consoles to
be attached.
base/inifile.cc:
base/str.hh:
Move the string hash function
base/symtab.cc:
base/symtab.hh:
sim/exetrace.cc:
Add support to lookup symbols by name, and take advantage of that support
for looking up symbols for panic and badaddr
base/str.cc:
base/str.hh:
change to new formatting.
naming convention still dosn't match new style
dev/console.cc:
dev/console.hh:
Fix console code so that typed characters are properly handled.
When clearing interrupts, be explicit with regards to which ones.
arch/alpha/vtophys.cc:
a tad bit of error checking
sim/exetrace.cc:
sim/exetrace.hh:
EXE-Trace extensions
Disabled "good_mem" memory layer... this still needs to be properly removed
base/kgdb.h:
Add more kgdb commands
base/trace.hh:
Tracing for ISP
sim/exec_context.cc:
sim/exec_context.hh:
sim/exetrace.cc:
sim/exetrace.hh:
sim/prog.cc:
sim/prog.hh:
Update to BTB functionality
Fixed numerous statistics
Fixed path of store instructions so that they _all_ go through issue stage
Updates to exetrace functionality
sim/eventq.cc:
sim/eventq.hh:
Replaced every-cycle termination checks in sim_main() with events.
Added per-thread instruction-count-based event queues to handle
termination based on committed instruction count. These are now
specified via parameters to the FullCPU object (max_insts_any_thread
and max_insts_all_threads) rather than global parameters under the
[max] context.
Also replaced break_cycle check with DebugBreakEvent.
Some cleanup of eventq.{cc,hh}.
sim/prog.hh:
Don't die if included under FULL_SYSTEM: just skip contents.
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
Added SimpleCPU object to do sim_safe type simulation in sim_smt.
Created abstract base class BaseCPU as common parent of (detailed) CPU
and SimpleCPU.
sim/exec_context.cc:
sim/exec_context.hh:
sim/prog.cc:
sim/prog.hh:
Register Process object stats using SimObject reg_stats() method
rather than indirectly via Thread end exec_context objects.
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/main.cc:
sim/sim_object.cc:
sim/sim_object.hh:
Changes to eliminate the global 'the_cpu' pointer to allow for
mutliple CPUs/systems. Specifically:
- Add findMaxThreadsPerCPU() and tickAll() static methods to
BaseCPU class.
- Added generic printExtraOutput() method for all SimObjects,
to dump output at the end of simulation that is not covered by
stats. Use this hook on CPU object to call
dump_floss_reasons(). sim_aux_stats() is now obsolete.
- printExtraOutput() takes an ostream& rather than a FILE*, so
dump_floss_reasons() had to be converted to C++ I/O.
- Fixed a bug in floss_reasons.cc where an additional
mem_access_result_t item (MA_NOT_PREDICTED) did not have a
corresponding entry in mem_access_result_item_descr. This
resulted in "(null)" being printed with sprintf I/O (which no
one had noticed, apparently), but caused a segfault using
streams.
sim/exec_context.hh:
sim/main.cc:
sim/prog.cc:
sim/prog.hh:
sim/sat_counter.hh:
sim/simple_cpu.cc:
Rename many stats to include config hierarchy path, so results from
different CPUs/systems can be distinguished.
Move stats.c/h into C++... renamed to stats.cc/hh. Added overloads
of most stat registration functions to allow 'string' rather than
'char *' stat names & formulas... no more sprintf needed!
sim/base_cpu.cc:
sim/base_cpu.hh:
Add sim_num_insn stats as per-CPU and total number of simulated instructions
so we can continue to calculate sim_inst_rate.
sim/simple_cpu.cc:
Fix sim_num_insn stat for SimpleCPU.
sim/simple_cpu.cc:
sim/simple_cpu.hh:
Move global memory interface objects into SimpleCPU object.
Made read/write functions SimpleCPU members for easier access to same.
Can now do multiple systems in non-FULL_SYSTEM mode.
sim/param.hh:
sim/sim_object.cc:
sim/sim_object.hh:
SimObjects now look in the .ini database first using the object
instance name (e.g., sys.cpu0) *then* using the configuration class
name (e.g., DetailedCPU). This makes it easier to use a common
description but override a few simple things like the workload.
base/remote_gdb.cc:
dev/console.cc:
dev/disk_image.cc:
Make ConsoleListener & GDBListener explicitly print which ports
they're listening on.
arch/alpha/alpha_memory.cc:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/fake_syscall.cc:
arch/alpha/vtophys.hh:
base/remote_gdb.cc:
base/symtab.cc:
base/symtab.hh:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/console.cc:
sim/exec_context.cc:
sim/exec_context.hh:
sim/exetrace.cc:
sim/exetrace.hh:
sim/main.cc:
sim/prog.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
Cleanup of full-system global variables, primarily in simple_cpu.cc,
to allow multi-system simulations. (Multiple systems not yet yested
though.) Also changes to build sim_smt in full-system mode (though
with only SimpleCPU and not the full timing CPU for now).
Still to do: minimize changes in SimpleCPU code between full-system
and application modes... way too many ifdefs there. Much of the
full-system stuff moved into SimpleCPU should be put in a new System
object to allow multiprocessor simulations.
Converted last remaining modules from C to C++ (mostly in /old).
Renamed all .c files to .cc and a few .h files to .hh.
Renamed architecture-specific files in arch/$TARGET from
$TARGET.{cc,hh,def} to machine.{cc,hh,def} to get rid of pointless
intermediate files in object directory. Split exo-specific
definitions out of machine.hh into machine_exo.h.
Specifics:
In machine.def, null resource descriptors must be FUClamd_NA (and not
NA) to pass C++ type checking.
Enhanced error checking/reporting in bas
base/range.hh:
Use the templated type for intermediate storage.
Added "valid" flag and method to the user can determine if the range parse or assignment was successful.
sim/eventq.cc:
sim/eventq.hh:
Modifications to properly count commited instructions... [no impacts]
test/Makefile:
test/offtest.cc:
New test
test/foo.ini:
test/initest.cc:
add Another piece to the test
arch/alpha/ev5.hh:
Properly do alternate mode
arch/alpha/alpha_memory.cc:
arch/alpha/ev5.cc:
sim/simple_cpu.cc:
arch/alpha/ev5.cc:
arch/alpha/isa_traits.hh:
base/hashmap.hh:
formatting
arch/alpha/alpha_memory.cc:
C style comment -> C++ style
arch/alpha/alpha_memory.cc:
more formatting
arch/alpha/alpha_memory.cc:
Add ALT_MODE support to the tlb lookup and make mode handling more sane
test/Makefile:
test/symtest.cc:
Add a test for the symboltable
base/symtab.cc:
Avoid some temporary objects
base/trace.cc:
add a hexdump like dump function for dumping memory
base/trace.hh:
Add more trace flags
Add DUMP which does a hexdump with semantics like DPRINTF
flush standard out after a debugging print or dump
dev/simple_disk.cc:
Add some debugging dumps
sim/param.cc:
sim/param.hh:
sim/sim_object.cc:
Because of order of construction, call a function that will return a
ParamList that will construct it as soon as it is needed
dev/pcireg.h:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
Flesh out the pci configuration space support.
Add configuration file support for vendor ID and device ID.
Clean up debugging
sim/simple_cpu.cc:
sim/simple_cpu.hh:
Don't execute pmap_scavenge_boot.
rename console_panic_addr to panic_addr.
change some warn()s to DPRINTF()
base/pollevent.cc:
base/pollevent.hh:
Don't poll every cycle. Use SIGIO to kick a poll off.
Make it possible to disable events
sim/exetrace.cc:
sim/exetrace.hh:
sim/simple_cpu.cc:
Completely rework the exetrace stuff.
Make a clas that holds all of the trace data for a particular cycle.
Add a N entry trace log so that one can dump the last N cycles leading
up to some sort of crash.
When printing a branch instruction, print the target symbol if available
instead of the address
dev/console.cc:
dev/console.hh:
sim/simple_cpu.cc:
Make console code deal with not being polled every cycle
sim/simple_cpu.cc:
Don't interrupt while in PAL
base/remote_gdb.cc:
base/remote_gdb.hh:
constify some functions.
fix some buffer handling.
add some debugging help
sim/param.cc:
Initialize paramList to NULL
sim/exetrace.cc:
sim/exetrace.hh:
sim/simple_cpu.cc:
Rework the execution trace stuff again. Merge the cycle log and the exetrace
into one class.
Stick the TraceData in the dyn_inst_t class.
Put the read_foo and write_foo functions in the dyn_inst_t class.
This gets rid of the memaccess namespace.
sim/exetrace.cc:
sim/exetrace.hh:
sim/simple_cpu.cc:
Don't worry about which thread to trace right now. Fix that later.
Add better support for merged logging and tracing.
Make sure that there is a place to put data when there is no log.
Make tracing work for non-system.
sim/exetrace.hh:
tracing() method must not return true if not initialized
sim/base_cpu.cc:
sim/main.cc:
Many fixes to statistics (especially distributions)
Many renamed statistics (added CPU name to all except cache stuff)
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/console.cc:
dev/console.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/simple_disk.cc:
dev/simple_disk.hh:
sim/intr_control.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
style fixes:
Make class names follow the ClassName style
Indenting based on four spaces
sim/param.cc:
Added pipetracing
(The trace output _should_ be compatible with the original Simplescalar
output, making their visualization tools available to us and providing
us with a more detailed debugging tool than exetrace)
base/trace.hh:
Separate disk and disk data
add tlaser uart
arch/alpha/alpha_memory.cc:
arch/alpha/ev5.cc:
Make this use C++ instead of void * voodoo
base/symtab.cc:
base/symtab.hh:
sim/exetrace.cc:
sim/exetrace.hh:
constify
sim/param.hh:
SimObjects are always pointers. Make this clear, and add the -> operator
sim/prog.hh:
fix comment
dev/pcireg.h:
Don't depend on order of #includes
sim/exetrace.cc:
Make logging work without tracing
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/console.cc:
dev/console.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/simple_disk.cc:
dev/simple_disk.hh:
sim/intr_control.cc:
sim/intr_control.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
Turn all of the devices and system stuff into SimObjects.
Add many extra parameters to have config file flexibility
base/sched_list.hh:
file sched_list.hh was initially added on branch clustering.
dev/console.cc:
dev/disk_image.cc:
Don't assume variables are initiaized to be zero
sim/simple_cpu.cc:
don't forget to dump the trace data if we're tracing
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
sim/simple_cpu.cc:
remove md_done_hwrei which was a hack that helped me
make the trace output look like what I was able to get out of
SimOS. Since we're more advanced than them, it's not needed
sim/simple_cpu.cc:
Try to make the trace more representative of what's going on. (Mainly around
disruptions.)
sim/simple_cpu.cc:
Disable this code since it uses a hardcoded address. This may be more useful
in the future though.
sim/simple_cpu.cc:
base/statistics.hh:
oops
base/trace.hh:
style
base/trace.hh:
add tracing to interrupts
sim/simple_cpu.cc:
Removed old access call in CPUMemInterface and added MemREqs to the pipeline.
sim/prog.cc:
Give main memory a name to fix statistics.
sim/main.cc:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_object.cc:
sim/sim_object.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
Added basic infrastructure to do checkpointing. Simple test in SimpleCPU.
base/trace.hh:
Added support for checkpoint/serialization
Added Serilize to list of know flags
sim/param.cc:
sim/serialize.hh:
Added support for checkpoint/serialization
Added Serilize to list of know flags
Now add implicit SimObjects to the ConfigHierarchy so they can be unserialized.
sim/serialize.hh:
sim/simple_cpu.cc:
Added WH64 implementation and dependencies
Added WH64 implementation, and added the ability to do stores of more than 4 bytes, and sett loads to 8 bytes.
base/inifile.hh:
base/str.hh:
Use functors for the hash functions for the hashtable class.
Pulled up from the pisa branch with a few modifications.
sim/eventq.cc:
sim/eventq.hh:
sim/serialize.cc:
sim/serialize.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
Updated to Hierarchical naming
Infrastructure for checkpointing.
base/inifile.cc:
base/inifile.hh:
base/trace.hh:
sim/exec_context.hh:
sim/exetrace.cc:
sim/main.cc:
sim/param.cc:
sim/param.hh:
sim/simple_cpu.cc:
test/Makefile:
- Merge PISA branch onto HEAD
- Tag before merge: HEAD_PRE_BR_PISA_MERGE
- Tag after merge: HEAD_POST_BR_PISA_MERGE
- Similar tags on PISA branch
- Add port to SimpleScalar/PISA
- New PISA instructions:
itouch
spill
reload
map
unmap
- Add prefetch implementation
- Prefetch cache
- Cache buffer (victim/prefetch buffers)
- Prefetch queue
- itouch instruction
- Add functional SLAT implementation
sim/main.cc:
Make this work in non Linux
base/remote_gdb.cc:
sim/base_cpu.hh:
sim/simple_cpu.cc:
Make FULL_SYSTEM work again after the pisa merge.
Random cleanups.
sim/main.cc:
sim/memtest.cc:
sim/memtest.hh:
Removed rules to make SIM_MEMTEST, added memtest.cc to smt source list
Renamed sim_memtest to memtest. Memtest now extends BaseCPU and can be dropped into sim_smt. Still need to add the ability to stop it running without a manual ctrl-C though.
Memtest currently does not test copies, just reads and writes. The multiple MSHR/Cache changes broke copying along the way.
Just touched main to help debug (needed to give a set random seed). Its back to normal.
sim/main.cc:
undo erik's mistaken commit
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/vtophys.cc:
base/circlebuf.cc:
base/circlebuf.hh:
base/inifile.cc:
base/inifile.hh:
base/pollevent.cc:
base/pollevent.hh:
base/range.hh:
base/remote_gdb.cc:
base/str.cc:
base/str.hh:
base/symtab.cc:
base/symtab.hh:
base/trace.cc:
base/trace.hh:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/console.cc:
dev/console.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/simple_disk.cc:
dev/simple_disk.hh:
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/eventq.cc:
sim/eventq.hh:
sim/exec_context.cc:
sim/exetrace.cc:
sim/exetrace.hh:
sim/hybrid_pred.hh:
sim/intr_control.cc:
sim/intr_control.hh:
sim/main.cc:
sim/memtest.cc:
sim/memtest.hh:
sim/param.cc:
sim/param.hh:
sim/prog.cc:
sim/prog.hh:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_object.cc:
sim/sim_object.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
test/bitvectest.cc:
test/foo.ini:
test/initest.cc:
test/initest.ini:
test/paramtest.cc:
test/rangetest.cc:
test/strnumtest.cc:
test/symtest.cc:
test/tokentest.cc:
- Get rid of my String class, the Vector class, the bitvector class, and my
doubly linked list class.
- Convert tokenize, to_number (formerly StringToNumber) and eat_white to
function on stl strings.
- Change most cases of char * and const char * to string, or const string &
- Some formatting and style nits, but not too many.
sim/param.cc:
test/bitvectest.cc:
use resize, not reserve to change the size of the actual vector
base/str.hh:
fix to_lower
dev/console.cc:
better tracing
sim/memtest.cc:
sim/memtest.hh:
Added support for CoherenceTest
Fixed small error that was leading to a fixed address being used half of the time.
sim/exetrace.cc:
sim/exetrace.hh:
Improvements to EXE-Trace:
Displays thread number (optionally)
Doesn't display 'count' field (optionally)
'Extended' output lines up nicely
sim/memtest.cc:
Fixed a print warning in memtest.cc
sim/exetrace.hh:
sim/main.cc:
sim/serialize.cc:
sim/serialize.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
- Merge SLAT changes
- Add stats to prefetch cache to track cycles lost due
to each miss address
- Get simple_cpu and FULL_SYSTEM to compile again. I'm
not sure these will run correctly (simple_cpu should)
but it is an improvement over what's currently available.
Split the engine files into generic, cpu-specific
and isa-specific files to isolate the various parts of
the engine code. This is quite hackish in places due to
machine.def (e.g. see comments in execute.cc). Further
cleanup is warranted but it compiles and passes smt-test.
Later commits will remove unused code.
base/trace.hh:
sim/param.cc:
sim/sim_object.cc:
add a new DTRACE macro that tests a trace variable if tracing is on, or
evaluates to fals if tracing is off. Avoids #if TRACING_ON/#endif
add an option for wheter or not you want the parameter stuff dumped while
the simulator is starting
sim/exetrace.cc:
sim/exetrace.hh:
Make the execution trace print the way it did before steve's last change.
Also, pass the flags in a more intelligent manner rather than adding new
function parameters all over the place.
sim/exetrace.hh:
sim/simple_cpu.hh:
make exetrace work in FULL_SYSTEM after dave's last changes.
Exetrace could probably be improved more to remove most of the
#ifdef FULL_SYSTEM junk. Not today though
base/trace.hh:
new trace flags
dev/alpha_console.cc:
size was too big
dev/pcireg.h:
new device ID for simos ethernet device
dev/disk_image.cc:
dev/simple_disk.cc:
dev/simple_disk.hh:
be smarter about using stl strings
sim/pc_event.cc:
sim/pc_event.hh:
PC based event system
sim/simple_cpu.cc:
Make all existing pc based stuff use the new pc based events
base/trace.cc:
base/trace.hh:
sim/param.cc:
sim/sim_object.cc:
If we're not tracing, print out the configuration junk. If we are tracing,
the configuration printing is default
sim/exetrace.cc:
- Fix bogus references to omitCount and includeTnum.
base/kgdb.h:
base/remote_gdb.cc:
base/remote_gdb.hh:
TONS of improvements to remote kernel debugging.
- Use the pc based events stuff to simulate hardware breakpoints.
- Implement the set/clear breakpoint/watchpoint function, though
only breakpoints are implemented right now.
Both software and hardware breakpoints are implemented as hardware
breakpoints.
- Fix numerous bugs in single stepping, and make temporary breakpoints
use hardware breakpoints instead of software breakpoints.
- Add tons of debugging stuff to help with future remote debugger debugging.
(No, that was not an accidental doubling.)
- Implement part of the query variable function.
- Remove old cruft that we don't need.
- Improve comments
dev/disk_image.cc:
dev/disk_image.hh:
Copy on write disk support
This code uses a hash table to implement copy on write support to disk image
blocks. There is also support to write out the table and load it back in.
dev/simple_disk.cc:
This class uses std::string
sim/simple_cpu.hh:
don't need these
base/circlebuf.cc:
base/circlebuf.hh:
Add some size information so we can keep track of wheter or not the buffer
is empty
arch/alpha/vtophys.cc:
simplify
base/object_file.cc:
base/object_file.hh:
initial framework for sucking in an object file and figuring out some stuff
for it. Support for ecoff and a header for elf. There is nothing for
relocations, but the symbol information is available so an external
program is no longer required for that.
base/symtab.cc:
base/symtab.hh:
Update some of the symbol table stuff to add support for manual insertion of
symbols. This is used by the object file code so that we can read the
table from the object file and stick it into the more efficient symtab
test/Makefile:
test/nmtest.cc:
test program for using the symbol table code. Basically allows one to look
up a symbol in an object file
dev/console.cc:
dev/console.hh:
Clean up the console code, add an input buffer queue to avoid leaving data in
the socket buffer. This allows us to preprocess data as it comes in for
things such as telnet support. There is some minimal telnet support in here
but it isn't working very well, and isn't enabled by default
sim/simple_cpu.cc:
sim/simple_cpu.hh:
Make the various pc based events part of the CPU object instead of being
global
sim/simple_cpu.cc:
sim/simple_cpu.hh:
Do the badaddr stuff far more intelligently. Basically, what we do now
is first determine if the address goes to any proper device. If not, the
address is bad. If so, ask the device whether the address is any good or
not. The default case is that a device will say that all of its addresses
are good, but there are some devices that don't follow this paradigm.
dev/alpha_console.cc:
dev/alpha_console.hh:
sim/intr_control.cc:
sim/intr_control.hh:
sim/universe.cc:
Make the tick frequency a global parameter and have all devices work from that
Also, make the timer interrupt delay parameterizeable (and make the default
shorter). This should make boot happen a little faster
base/refcnt.hh:
Simple reference counting class. Could be replaced by boost shared_ptr some
day.
Classes that are reference counted must have exported functions incref()
and decref() for manipulating the reference count. This doesn't have the
convenience of shared_ptr where the shared classes can be used unmodified,
but it also means that the refcnt pointer (the pointer in this code) is
the size of a normal pointer for this system.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherpkt.hh:
Initial hack at a ethernet device model and an ethernet bus model. Known to
be broken at this point
arch/alpha/alpha_memory.cc:
sim/simple_cpu.cc:
Memory system enhancements:
- Functional implementation of load-locked/store-conditional in
main_memory object (the functional memory object for non-full-system
mode). This code should eventually be extracted out and applied to
both main_memory and physical_memory so that it works in full-system
mode as well. Moved lock_flag & lock_addr from system registers to
control registers so they're available in non-full-system mode.
- Moved Alpha unaligned access handling back into machine.def. (It
was a flag on the mem request and handled in the memory system, but
that approach appears to be unnecessarily complicated.)
- Cleanup of AlphaMemoryRequest: down from five constructors to one;
Erik's full-word flags are now bits in Nate's flag word.
- Eliminate obsolete memory.h functions, and some unused memory_object
functions.
arch/alpha/vtophys.cc:
base/remote_gdb.cc:
sim/prog.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
Renamed SimpleCPU::(read|write)_(byte|half|word|qword) to just read &
write, overloaded on the type of the 'data' argument. Merged the
full-system and non-full-system implementations of these eight
original functions into two common template functions.
To support this, also renamed (read|write)[1248] on memory_object and
derivatives to just read & write, again overloaded on the type of the
'data' argument. Many of these functions could now be condensed into
a few template functions (though with a level of indirection so that
the interface can remain virtual). I did not do that though.
sim/exec_context.hh:
sim/pc_event.hh:
- Eliminate static SLAT variables when building FULL_SYSTEM
base/remote_gdb.cc:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
make it easier to drop into the remote debugger from within the local debugger
dev/pcireg.h:
Instead of having each pci device define its own sim object to represent
the configuration space, just define one TlaserPciDev type and change the
configuration regs as needed.
base/range.hh:
Fix bugs in range parsing code.
sim/eventq.hh:
Uncomment inlined event check (not sure why it was commented out
to begin with).
base/str.hh:
- Add some missing #includes.
- Remove some prefetching stats to shorten log lengths.
- Fix perfect cache to work with new coherence mechanism
(or at least not fail when there is no coherence protocol).
base/range.hh:
Consider whether a range object is valid or not when doing range tests.
Reorganization & minor documentation of range comparison code.
sim/exetrace.hh:
Bug fix related to previous commit on range.hh.
test/nmtest.cc:
Add ability to do lookups by address
dev/etherbus.cc:
base/statistics.cc:
fix
sim/simple_cpu.cc:
make it so we can change the boot flag
sim/simple_cpu.cc:
Bit more debugging info
base/circlebuf.cc:
Must initialize the size
dev/console.cc:
sim/simple_cpu.cc:
better debugging
base/remote_gdb.cc:
Don't panic if the execution context isn't the same, just don't execute the
breakpoint since it probably belongs to another instance
sim/memtest.cc:
Removed bcopy_in & bcopy_out (needless aliases for prot_write &
prot_read, respectively). Made prot_read & prot_write public methods
(not protected). Had to change some char arrays to byte_t to keep
compiler happy.
Renamed strcpy_in and strcpy_out to writeString and readString,
respectively, to reduce confusion about the direction they operate.
Also some reformatting for style.
sim/main.cc:
Move some more old simplescalar I/O from stdio to C++ streams.
Some reformatting for style in main.cc as well.
base/inifile.cc:
base/inifile.hh:
Pass -D, -U, and -I args to cpp for ini-file processing. Should make
use of #defines in .ini files much handier, once we get our parser up
to dealing with the resulting whitespace issues.
Some reformatting for style as well.
sim/main.cc:
Pass -D, -U, and -I args to cpp for ini-file processing. Should make
use of #defines in .ini files much handier, once we get our parser up
to dealing with the resulting whitespace issues.
sim/exetrace.cc:
sim/exetrace.hh:
sim/simple_cpu.cc:
Changes to exetrace code to make it somewhat less schizophrenic so
that it works under non-full-system SimpleCPU. (Previous code assumed
either full-system+simple CPU or non-full-system+detailed CPU.)
Also removed a lot of unused code in simple_cpu.cc.
base/trace.hh:
Added trace flags to display all syscalls or common syscall-related
warnings (which are suppressed by default).
arch/alpha/fake_syscall.cc:
sim/exec_context.cc:
sim/exec_context.hh:
sim/prog.cc:
sim/prog.hh:
sim/simple_cpu.cc:
Syscall emulation (non-full-system) support for multithreaded apps
compiled using Tru64 5.1's pthreads library.
More specifically, you can now associate multiple processors with a
single LiveProcess object (via their workload parameters). Only one
processor will be active initially. The additional processors will
be assigned to handle new "virtual processor" threads as they are
created by the pthreads user library. Functionality is limited, as
we do *not* emulate any kernel scheduling: once a VP thread is created,
it is permanently bound to a simulated CPU. However, most of the
SPLASH-2 benchmarks seem to run on both uni- and dual-processor targets.
Includes total rewrite of syscall emulation (fake_syscall.cc). Only
syscalls that have been needed thus far have been re-implemented in
the new framework. Others will be moved over on demand.
base/trace.cc:
Better dump function
sim/simple_cpu.cc:
The active field of exe_ctx is not used in FULL_SYSTEM
sim/eventq.cc:
dev/etherbus.cc:
more debugging
sim/memtest.cc:
Added support for mem_cmd.cc
Transitioned from enum mem_cmd to class MemCmd
sim/eventq.hh:
sim/param.hh:
sim/serialize.hh:
sim/sim_object.hh:
test/sized_test.cc:
- Fix PISA syscalls to use new memory interface.
- Make prefetching a real SimObject and port existing
prefetchers to the new framework.
base/inet.cc:
base/inet.hh:
Move functions for networking into a separate file
sim/exec_context.cc:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
Add basic support for a quiesce instruction.
- Suspend the current thread on quiesce
- Resume on interrupt
Add an arm instruction that doesn't do anything yet
sim/simple_cpu.cc:
Added FULL_SYSTEM wrapper to use of "proc" in tick().
Nate, please check to make sure I didn't break it.
base/inifile.hh:
Added include of vector
base/trace.hh:
- Create a ScsiDevice base class that represents all of the functions that a
SCSI device might want to implement
- Clean up the ScsiDisk class: remove unneeded junk and give better names
- Create a ScsiNone class that is used when a given target has no device
sim/main.cc:
Always use the same random seed to make the memory tester repeatable.
As the comment says, someday we should make this a parameter.
(Do we still need "mysrand()" and "myrand()"?)
sim/memtest.cc:
sim/memtest.hh:
- Get rid of CoherenceTest... MemTest is just as capable.
- Lots of new parameters for MemTest.
sim/pc_event.cc:
Don't execute a pc event twice
dev/disk_image.cc:
Add a config node of the copy on write disk image
base/trace.hh:
dev/disk_image.cc:
More debugging
base/trace.hh:
Major update in dma code.
- Separate the io callback into a read callback and a write callback
- Fix the write callback so that the proper data is written back to the
disk and data is copied to the proper place in the data buffer
- Use sim_freq for the tick frequency. (There is still no delay)
- Remove a bunch of unnecessary code
- Make code more concise and remove old cruft
- More Debugging (of course)
- Formatting fixes
- mprotect hack to make sure that dma buffer is not overwritten
sim/exec_context.cc:
sim/exec_context.hh:
Fix broken assertion in main_memory::checkLockedAddrList().
Check for lots of failed store-conditionals and print deadlock warning message.
arch/alpha/fake_syscall.cc:
Use actual number of CPUs allocated to process (not const 2!).
A few additional syscalls for pthreads support (not quite there yet though).
sim/prog.cc:
sim/prog.hh:
Use actual number of CPUs allocated to process (not const 2!).
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/fake_syscall.cc:
base/remote_gdb.cc:
base/remote_gdb.hh:
sim/exec_context.cc:
sim/exec_context.hh:
sim/exetrace.cc:
sim/exetrace.hh:
sim/pc_event.cc:
sim/pc_event.hh:
sim/prog.cc:
sim/prog.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
exec_context_t -> ExecContext
spec_exec_context_t -> SpecExecContext
dev/disk_image.cc:
quell warnings
base/trace.hh:
remove more warnings
sim/exec_context.cc:
sim/exec_context.hh:
sim/prog.cc:
sim/prog.hh:
sim/simple_cpu.cc:
remove the Process object from FULL_SYSTEM since it doesn't really make
any sense
sim/simple_cpu.cc:
move SIM_OBJECT junk to the end like other files
sim/simple_cpu.cc:
sim/simple_cpu.hh:
Make it so we can use a memory hierarchy in FULL_SYSTEM SimpleCPU
arch/alpha/fake_syscall.cc:
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/exec_context.cc:
sim/exec_context.hh:
sim/prog.cc:
sim/prog.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
- Add pointer from execution context to the CPU it's running on.
- Just pass execution context pointer to the syscall emulation code,
instead of a bunch of individual field arguments.
- A few more exec_context_t -> ExecContext changes for non-full-system.
- Rudimentary thread scheduling for non-full-system support of
pthreads apps. Hopefully this won't go much farther.
sim/exec_context.cc:
Oops... fix minor bug from merge.
arch/alpha/fake_syscall.cc:
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/exec_context.cc:
sim/exec_context.hh:
sim/prog.cc:
sim/prog.hh:
sim/simple_cpu.cc:
- We really don't want to build a thread scheduler in the simulator...
rip all that out, and replace with some basic synchronization
primitives implemented as syscalls. Non-full-system MP apps thus
need to be compiled specially to use these primitives, but it's
plenty good enough to get SPLASH-2 up and running.
These primitives block by suspending the execution context (for
efficient simulation). Studies that care about synch operation
costs should use user-level LL/SC-based primitives instead.
- Implement more than two states (active vs. !active) for an ExecContext.
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/fake_syscall.cc:
arch/alpha/vtophys.cc:
base/circlebuf.cc:
base/fast_alloc.cc:
base/inifile.cc:
base/inifile.hh:
base/object_file.cc:
base/object_file.hh:
base/range.hh:
base/remote_gdb.cc:
base/res_list.hh:
base/socket.cc:
base/str.cc:
base/str.hh:
base/symtab.cc:
base/symtab.hh:
base/trace.cc:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/console.cc:
dev/console.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/simple_disk.hh:
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/eventq.cc:
sim/exetrace.cc:
sim/exetrace.hh:
sim/hybrid_pred.hh:
sim/intr_control.cc:
sim/intr_control.hh:
sim/main.cc:
sim/memtest.cc:
sim/memtest.hh:
sim/param.cc:
sim/param.hh:
sim/pc_event.hh:
sim/prog.cc:
sim/prog.hh:
sim/sat_counter.hh:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_object.cc:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
sim/universe.cc:
First pass at compiling with gcc 3.x. Lots of "std::" in header files,
"using namespace std" in source files. (Note policy of not putting "using"
statements in headers or before includes in sources.)
Still not able to compile with gcc 3.2.
Errors:
- Can't create an ifstream from a file descriptor anymore (breaks IniFile).
- "`class MSHR::MSHRegister' is private" errors in mshr.cc and prefetch_cache.cc:
not clear why since it's in the public part of the class declaration.
- cpu.cc:879: can't match a reference and 0 (specifically "no match for `bool ?
SimObjectParam<PipeTrace*>& : int' operator")
- pipetrace.cc: "invalid conversion from `int' to `std::_Ios_Fmtflags'"
Warnings:
- strstream now deprecated... needs some rewriting in sat_counter.hh
and hybrid_pred.hh (need to get all that code out of the headers anyway)
- trace.hh macro problem: cpp now says 'pasting "::" and "Event" does not
give a valid preprocessing token'
- major "implicit typename" issues in base/sized.hh
base/trace.hh:
Token pasting not necessary. Quiets g++ 3.2 warning
base/inifile.cc:
base/inifile.hh:
Make this compile in g++ 3.2
base/remote_gdb.hh:
dev/etherbus.hh:
dev/pcireg.h:
dev/simple_disk.cc:
Make this stuff g++ 3.2 happy
base/inifile.cc:
Make this still compile in g++ 2.95
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
dev/alpha_console.cc:
dev/alpha_console.hh:
sim/serialize.hh:
sim/simple_cpu.cc:
Added serialization for simple FULL_SYSTEM objects. Working on the hard ones
sim/simple_cpu.cc:
Make this code actually compile. Fix style while we're at it
sim/base_cpu.cc:
Fixes to recent updates to maintain gcc 3.2 compatibility
(mostly more std:: in header files).
test/Makefile:
SS -> M5
base/cprintf.cc:
base/cprintf.hh:
test/Makefile:
test/cprintftest.cc:
printf replacement that uses C++ io streams and is typesafe
Any type that overloads operator<< for use with streams will work with this
structure.
The format string is backwards compatible with printf style format strings,
but the types are not checked, for example, %s doesn't verify that the
type being printed is a string, %d doesn't verify that the type being
printed is an integer. Instead, the various formats just set up the proper
io stream manipulators for printing. So, %#s doesn't mean anything different
from %s, but %#x does mean something different from %x. If the type you are
printing does't care about the #, then nothing changes.
base/cprintf.hh:
test/cprintftest.cc:
Fix case where there is only a format string, and no arguments
base/cprintf.hh:
base/cprintf_formats.hh:
std::
base/trace.cc:
base/trace.hh:
Make the tracing stuff use cprintf
base/cprintf.cc:
Save and restore iostream state
dev/etherbus.cc:
Rewrite the dma engine support so that it can interact with the dma_interface
to the timing memory model. This way, all of the timing of the dma transfers
themselves can come from the memory system. Simos copyright removed since
this code shares nothing with Simos
sim/hybrid_pred.hh:
sim/predictor.hh:
sim/sat_counter.hh:
Fixes to stat names in segmented IQ
Changes from strstream to stringstream to remove warnings
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherint.hh:
Separate the interface to the bus from the device
sim/simple_cpu.cc:
Move progress message from SimpleCPU::tick() to new ProgressEvent.
(Much more efficient, and available independent of CPU model.)
dev/console.cc:
dev/console.hh:
Added [DoEvents] default so command line --DoEvents:do_events=1 turns on events for all busses
Added serlization function headers (not implemented yet).
sim/eventq.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
Added [DoEvents] default so command line --DoEvents:do_events=1 turns on events for all busses
Added serlization function headers (not implemented yet).
Added EventQueue::nextEventTime(), returns time head is scheduled, or sim_cycle if empty.
Added support for uniprocessor SimpleCPU with timing memory.
arch/alpha/fake_syscall.cc:
base/remote_gdb.cc:
sim/exec_context.hh:
sim/prog.cc:
sim/simple_cpu.cc:
Get rid of redundant ExecContext PC field.
sim/main.cc:
Add -n option to suppress loading default.ini.
Added a little more help to the help message.
sim/main.cc:
Oops... make sure we still load it when we don't say '-n'.
sim/main.cc:
Minor formatting.
sim/exetrace.cc:
sim/exetrace.hh:
Merge full-system & non-full-system exetrace code.
base/cprintf.cc:
base/cprintf.hh:
Previous two commits were (somewhat) broken... this is the real one
test/cprintftest.cc:
more testing
base/remote_gdb.cc:
base/remote_gdb.hh:
dev/alpha_console.cc:
dev/alpha_console.hh:
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/exec_context.cc:
sim/exec_context.hh:
sim/pc_event.cc:
sim/pc_event.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
sim/system.cc:
sim/system.hh:
Moved a lot of full-system variables out of SimpleCPU so that they can
(eventually) be used with the detailed CPU model. Several fields
moved into the ExecContext, while a few others moved into a new System
object (which replaces the old Kernel object, for now at least).
sim/exetrace.cc:
sim/pc_event.cc:
sim/pc_event.hh:
sim/simple_cpu.cc:
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
dev/alpha_console.cc:
dev/alpha_console.hh:
- Many g++ 3.2 fixes
- Added Makefile magic to allow a comprehensive build of
all simulator variants on all archtectures. 'make all'
or 'make TARGET=<arch> all_flavors'
- Added container adaptors and associative_table. Don't
use these quite yet -- they are very expensive to
compile. Am currently converting them over to boost::mpl.
They are used by the new BHGP prefetcher.
- Moved md_sysreg_t reg_t entries to isa_traits. PISA
does not have these sorts of registers.
- Moved ipr accesses to theISAEngineTraits because they
are not generally applicable. These are #ifdef FULL_SYSTEM
in the simulator code -- eventually this should get worked
into the traits structure.
base/fifo_buffer.cc:
base/fifo_buffer.hh:
Initial add of this incredibly usefull utility object
arch/alpha/ev5.cc:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
base/remote_gdb.cc:
sim/exec_context.cc:
sim/exec_context.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
sim/system.cc:
Implement some interval statistics for full system mode.
Create a callpal function that is called when a callpal occurs so it's easier
to manipulate the statics.
Rework the vtophys stuff to make it a bit cleaner.
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
Keep track of all callpals in the interval stats
base/res_list.hh:
base/sched_list.hh:
sim/eventq.cc:
sim/eventq.hh:
sim/exetrace.cc:
sim/exetrace.hh:
sim/hybrid_pred.hh:
sim/main.cc:
sim/predictor.hh:
sim/prog.cc:
sim/sat_counter.hh:
TA DA!!!!
The giant, huge, amazing, i-hope-i-never-have-to-do-that-again,
CLUSTERING MERGE!!!!
\
base/fifo_buffer.hh:
sim/exetrace.hh:
Minor adjustments for GCC 3 compatibility
Turn ptrace features back on
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/ev5.cc:
arch/alpha/fake_syscall.cc:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
base/remote_gdb.hh:
dev/alpha_console.cc:
dev/simple_disk.cc:
dev/simple_disk.hh:
sim/exec_context.cc:
sim/exec_context.hh:
sim/exetrace.hh:
sim/memtest.cc:
sim/memtest.hh:
sim/prog.cc:
sim/prog.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
sim/system.cc:
sim/system.hh:
Get rid of almost all old-style object names. This commit is equivalent
to running the following script on the current head:
#! /bin/sh
find \( -name '*.cc' -o -name '*.hh' \) -exec perl -pi -e '\
s/\bmemory_object\b(?!\.hh)/FunctionalMemory/g;\
s/\bvirtual_memory\b(?!\.hh)/VirtualMemory/g;\
s/\bmain_memory\b(?!\.hh)/MainMemory/g;\
s/\bphysical_memory\b(?!\.hh)/PhysicalMemory/g;\
s/\bspec_memory\b(?!\.hh)/SpeculativeMemory/g;\
s/\bMemObj\b(?!\.hh)/TimingMemObj/g;\
s/\bmemory_translation\b(?!\.hh)/AddressTranslator/g;\
s/\balpha_tlb\b(?!\.hh)/AlphaTlb/g;\
s/\balpha_itb\b(?!\.hh)/AlphaItb/g;\
s/\balpha_dtb\b(?!\.hh)/AlphaDtb/g;\
s/\bmemory_controller\b(?!\.hh)/MemoryController/g;\
s/\bstorebuffer_t\b(?!\.hh)/StoreBuffer/g;\
s/\bstorebuffer_entry_t\b(?!\.hh)/StoreBufferEntry/g;\
s/\bcreate_vector_t\b(?!\.hh)/CreateVector/g;\
s/\bcv_spec_state\b(?!\.hh)/CreateVecSpecState/g;\
s/\bspec_state_list\b(?!\.hh)/SpecStateList/g;\
s/\bdyn_inst_t\b(?!\.hh)/DynInst/g;' {} \;
arch/alpha/fake_syscall.cc:
sim/exec_context.hh:
sim/memtest.hh:
sim/simple_cpu.cc:
Renamed files to better match new object names:
base_memory.{cc,hh} --> functional_memory.{cc,hh}
mem_obj.{cc,hh} --> timing_mem_obj.{cc,hh}
sim/exec_context.cc:
sim/exec_context.hh:
sim/prog.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
Detailed CPU now compiles in full-system mode (but doesn't run, so I
didn't add it to the makefile).
SLAT code is now protected by '#ifdef USE_SLAT', since it's not currently
compatible with full-system mode. Also, slat.cc is not compiled by
default. We will need a makefile option to do '-DUSE_SLAT' and add
slat.cc to the source list.
CPU::Thread object is gone; these are now just bare SpecExecContexts.
Changed all remaining {read,write}_{byte,half,word,qword} sets of methods
to just read/write template methods, where possible.
sim/system.cc:
sim/system.hh:
Make the system boot flag a paramter
arch/alpha/ev5.hh:
sim/intr_control.hh:
The ethernet device was interrupting on the wrong interrupt line. Line 0x17
is too high (it's higher than the clock interrupt) and it doesn't correspond
with the spl protection in the driver source.
To solve this, we hack in support to support multiple interrupts at a single
level and have scsi and ethernet share the same interrupt level.
dev/etherbus.cc:
dev/etherint.hh:
Make the bus call back to the ethernet interface when the transfer is
complete. This allows the interface to do the next request in the transmit
buffer if there is one.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
Add etherdump object which accepts packets and spits them out in tcpdump
format for analysis with tcpdump and ethereal.
Make the etherbus support the dump object
dev/etherint.cc:
make the ethernet interface a SimObject that you can refer to
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
Add a different connection type between ethernet interfaces.
The ether link is a unidirectional fixed bandwidth link. To simulate
a full duplex 100MB/s ethernet, you need two etherlinks. It's just much
easier to simulate a full duplex link this way. Maybe encapsulate this into
another bidirectional link sometime.
sim/exec_context.hh:
sim/main.cc:
sim/simple_cpu.cc:
sim/system.cc:
Add a halted state to the simulator and only actually exit the simulator
when all systems have halted. While we're at it, remove an if statement
from the common code path in SimpleCPU::tick
sim/exec_context.hh:
sim/simple_cpu.cc:
IntervalStatsObject -> IntervalStats
test/Makefile:
Make this work again
base/cprintf.hh:
#include guard
arch/alpha/alpha_memory.cc:
arch/alpha/vtophys.cc:
base/remote_gdb.cc:
dev/alpha_console.cc:
dev/console.cc:
dev/disk_image.cc:
dev/etherbus.cc:
dev/simple_disk.cc:
sim/eventq.cc:
sim/pc_event.cc:
sim/simple_cpu.cc:
since cprintf properly deals with 64-bit types, stop using FMT* as much as
possible
base/circlebuf.cc:
base/inet.cc:
base/inet.hh:
base/object_file.cc:
base/res_list.hh:
convert some stdio stuff to use cprintf/c++ streams
dev/console.cc:
dev/console.hh:
convert some stdio stuff to use cprintf/c++ streams
better use of format strings
sim/exec_context.hh:
sim/exetrace.cc:
sim/exetrace.hh:
- Make SLAT work with new execution context
- Temporarily fix include file problems (circular includes)
arch/alpha/alpha_memory.cc:
arch/alpha/ev5.cc:
arch/alpha/fake_syscall.cc:
sim/eventq.hh:
sim/hybrid_pred.hh:
sim/main.cc:
True and false are keywords in C++, don't use TRUE and FALSE
This can be done with the following script:
#!/bin/sh
for each in `find . \( -name '*.cc' -o -name '*.hh' \)`; do
perl -pi -e '\
s/\bFALSE\b/false/g;\
s/\bTRUE\b/true/g;' $each
done
base/cprintf.cc:
base/cprintf.hh:
test/Makefile:
test/cprintftest.cc:
Add support for 'terminators' to cprintf. This is esentially a special
manipulator that can cause some sort of event to occur when the stream
is outputted. (Will be used for panic, fatal, etc.)
base/cprintf.cc:
base/cprintf.hh:
Another cleanup fo the cprintf stuff. This should make it much easier to do
panic, etc.
sim/simple_cpu.cc:
Rename sim_num_refs to SIM:num_refs to match Steve's new naming
in the detailed CPU stats.
base/cprintf.cc:
base/cprintf.hh:
Get rid of the reference counting and the pass by value, and come up with
a way to remove all of the temporary variables that are created, and only
create one. Should make the compiler's burden much less
sim/pc_event.hh:
quell warning
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/fake_syscall.cc:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
base/inet.cc:
base/inet.hh:
base/object_file.cc:
base/object_file.hh:
base/remote_gdb.cc:
base/remote_gdb.hh:
base/trace.cc:
base/trace.hh:
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/console.cc:
dev/console.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/etherpkt.hh:
dev/simple_disk.cc:
dev/simple_disk.hh:
sim/exetrace.hh:
sim/memtest.cc:
sim/memtest.hh:
sim/pc_event.cc:
sim/serialize.cc:
sim/serialize.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
sim/system.cc:
Change byte_t etc. to C99 standard int8_t etc.
Other than old/host.h, all other changes were produced by this script:
#! /bin/sh
find \( -name '*.cc' -o -name '*.hh' -o -name '*.c' -o -name '*.h' -o -name 'machine.def' \) -exec perl -pi -e '\
s/\bbyte_t\b(?!\.hh)/uint8_t/g;\
s/\bsbyte_t\b(?!\.hh)/int8_t/g;\
s/\bhalf_t\b(?!\.hh)/uint16_t/g;\
s/\bshalf_t\b(?!\.hh)/int16_t/g;\
s/\bword_t\b(?!\.hh)/uint32_t/g;\
s/\bsword_t\b(?!\.hh)/int32_t/g;\
s/\bqword_t\b(?!\.hh)/uint64_t/g;\
s/\bsqword_t\b(?!\.hh)/int64_t/g;\
s/\bbool_t\b(?!\.hh)/bool/g;\
s/\bdfloat_t\b(?!\.hh)/double/g;\
s/\bsfloat_t\b(?!\.hh)/float/g;' {} \;
sim/simple_cpu.cc:
Assume preprocessor can do ANSI '##' token pasting.
arch/alpha/fake_syscall.cc:
base/misc.cc:
base/misc.hh:
base/pollevent.cc:
base/sched_list.hh:
base/socket.cc:
base/symtab.cc:
dev/console.cc:
dev/disk_image.cc:
dev/simple_disk.cc:
sim/base_cpu.cc:
sim/eventq.cc:
sim/intr_control.hh:
sim/main.cc:
sim/memtest.cc:
sim/param.cc:
sim/serialize.cc:
sim/sim_object.cc:
sim/simple_cpu.cc:
Get closer to removing all FMT64 junk and myfprintf stuff
Make panic, flatal, warn use cprintf.
Start moving away from the old/misc.(cc|h) files.
dev/simple_disk.cc:
Get rid of some FMT junk
dev/etherdump.cc:
dev/pcireg.h:
u_int* -> uint*
dev/etherdump.cc:
sys/time.h instead of time.h
arch/alpha/ev5.cc:
sim/exec_context.cc:
sim/exec_context.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
Do some clean up in the manner that the interval stats object is created
Also, use the interval stats range when doing my full-system istats.
Finally, don't make the interval stats part of the exec_context since it makes
little sense to do so. We're only going to have one interval stats
object (at least for now.)
base/mod_num.hh:
Initial addition of a "modulo-number" class
sim/eventq.cc:
sim/eventq.hh:
convert some stdio to iostream
sim/eventq.cc:
sim/eventq.hh:
sim/main.cc:
sim/sim_events.cc:
sim/sim_events.hh:
sim/simple_cpu.cc:
Move some common events into a new sim_events file. Rearrange some other
things to move towards having only events in the main loop.
sim/eventq.hh:
Change protections
base/pollevent.cc:
base/pollevent.hh:
proper destruction
dev/console.cc:
don't panic on connection error. detach.
sim/eventq.cc:
sim/eventq.hh:
Clean up event queue and add support for priorities
sim/eventq.cc:
sim/main.cc:
sim/memtest.cc:
sim/serialize.cc:
sim/sim_events.cc:
sim/sim_events.hh:
Get rid of sim_exit_now and make it an event.
Get rid of sim_dump_stats and make it an event.
Main loop is now reduced to servicing the event queue, ticking the
CPUs, and incrementing sim_cycle
sim/simple_cpu.hh:
formatting nits
base/cprintf.hh:
dev/etherdump.cc:
dev/etherdump.hh:
sim/eventq.hh:
sim/sim_events.cc:
- ANSI/ISO C++ fixes
- Improve SLAT efficiency
- Add build_test rule to compile across all archs
and options. This builds one simulator from each
combination including the optimized Alpha simulator
to run smt-test. Please run this before committing.
base/misc.cc:
make warnings less verbose
sim/eventq.hh:
Generic function that will delay the calling of a member function until a
specified cycle.
Has problems if you use it with gcc 2.95, but 3.2 compiles it ok.
dev/etherbus.cc:
Better debugging
dev/etherbus.cc:
dev/etherint.cc:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
Rework the EtherInt class to represent a generic Ethernet interface. Any
object that wishes to connect to another device and pass ethernet packets
must export an ethernet interface. This makes it possible to connect any
two objects that have ethernet interfaces. For example, one EtherDev can
connect directly to another etherdev, or the two EtherDevs can each attach
to one of the interfaces on an EtherLink to get a fixed bandwidth.
dev/ethertap.cc:
dev/ethertap.hh:
util/tap/Makefile:
util/tap/tap.cc:
The ethertap device and ethertap utility allow a simulator to connect to a
real physical ethernet. Currently, the tap utility only works on OpenBSD,
but that should be easily fixed.
dev/ethertap.cc:
dev/ethertap.hh:
better bounds checking
base/cprintf.hh:
change function names in cprintf
base/trace.cc:
base/trace.hh:
Make DPRINTF work more like panic, fatal, warn, etc. Also make it possible
to redirect trace output to a file instead of stdout.
dev/etherlink.cc:
dev/etherlink.hh:
Make EtherLink::Link Serializeable
arch/alpha/alpha_memory.cc:
base/remote_gdb.cc:
base/res_list.hh:
base/trace.cc:
base/trace.hh:
dev/console.cc:
dev/disk_image.cc:
dev/etherbus.cc:
dev/etherlink.cc:
dev/ethertap.cc:
dev/simple_disk.cc:
sim/eventq.cc:
sim/eventq.hh:
sim/pc_event.cc:
sim/serialize.cc:
sim/simple_cpu.cc:
rework DPRINTF to automatically print the cycle and get the name of the
object from which it was called.
Additionally, while we're at it change 0x%x -> %#x
dev/disk_image.cc:
sim/pc_event.cc:
sim/serialize.cc:
dont use c_str() if we don't have to
base/trace.cc:
Only delete the stream if we created it
base/trace.cc:
base/trace.hh:
Expose ostream to which tracing statements are sent via DebugOut()
dev/console.cc:
carriage return not necessary
arch/alpha/arguments.cc:
arch/alpha/arguments.hh:
Add support for accessing function arguments from a kernel function.
The class behaves somewhat like a random access iterator so that the user can
access any argument desired, but to get at the data, the user uses the
casting operators to get at the data pointed to by the arguments
sim/pc_event.cc:
sim/pc_event.hh:
inline
sim/pc_event.cc:
sim/pc_event.hh:
sim/system.cc:
sim/system.hh:
create a pc based event that traps kernel printfs for debugging statements
arch/alpha/arguments.hh:
rename to CopyData and use void * to avoid compiler problems
sim/pc_event.cc:
Make Kernel::Printf take AlphaArguments as a parameter so that a user may
add initial arguments to another version of the kernel function and then
pass an offset arguments class to the function for printing the data.
Also, while we're at it, remove the printing of the cycle. That can be done
by the caller.
base/trace.hh:
sim/pc_event.cc:
sim/pc_event.hh:
sim/system.cc:
sim/system.hh:
Separate the printf event from the debugging printf event. The kernel will
call the debugging printf event m5printf. There is also a raw version
m5printfr that indicates to the simulator that it shouldn't print
any extra information in the context of this debuggin printf because
it would screw up fromatting.
sim/pc_event.cc:
symmetry
arch/alpha/arguments.cc:
arch/alpha/arguments.hh:
plug huge leak
arch/alpha/arguments.hh:
Add std:: to list
arch/alpha/arguments.hh:
make the execution context available
dev/etherlink.cc:
formatting, typeo, paranoia
sim/system.cc:
sim/system.hh:
enable the mbuf dump code
sim/pc_event.cc:
sim/pc_event.hh:
Add a pc event for the kernel mbuf dump function
arch/alpha/fake_syscall.cc:
sim/main.cc:
I can see no good reason at all for doing setjmp/longjmp
arch/alpha/arguments.cc:
arch/alpha/arguments.hh:
reference count the argument data so that the data doesn't disappear before
we're done using it.
sim/main.cc:
move all signal stuff into main.cc
sim/sim_events.cc:
Move termination and progress event initialization to sim_events
sim/debug.cc:
sim/debug.hh:
sim/main.cc:
sim/pc_event.cc:
sim/simple_cpu.cc:
Move some of the debug break stuff to its own file
Use SIGTRAP to initiate a break and set up the simulator to ignore the signal.
This will make gdb automatically stop in these functions, but won't interfere
with normal simulator workings.
sim/sim_events.cc:
Id string
sim/sim_events.cc:
make g++ 3 happy
base/cprintf.cc:
base/cprintf.hh:
base/misc.cc:
base/misc.hh:
base/trace.cc:
base/trace.hh:
- Rename debug rule to dbg so it doesn't interfere
with debug.cc.
- Reorganize build_test so it generates dependencies
correctly.
- Remove HashTable from spec_memory and replace with
SGI's hash_map extension.
- Put cprintf/ArgList in namespace cp so it doesn't
interfere with g++ 2.95 std::deque (comma operator
gives problems -- this is a g++ 2.95 bug).
- Fix FP register decode in dispatch. PISA registers
> 31 were being counted as FP registers and using
up all of the FP hpysical registers. The code in
commit correctly identified FP registers so the
bogus FP physical register usage was never cleared,
locking up the machine. This is why the SLAT didn't
work correctly. Added isa_traits::isFloatingPointRegister
and ::isIntegerRegister to do this tracking in a
machine-independent way.
sim/sim_events.cc:
simple way to dump stats on specified cycles
sim/eventq.hh:
Re-insert assignment of description string into event
sim/eventq.cc:
If event is the head in remove() return
arch/alpha/fake_syscall.cc:
Clustering changes....
- clusters can share data using the ClusterSharedInfo structure
- Pulled the register info file from the segmented IQ --> dispatch stage
(this info can be used by the dispatch stage and any IQ model)
- Segmented IQ's share the chain-info-table now
base/misc.hh:
- Add m5_assert() macro to print the sim_cycle if the
assert fails.
- Add simple_trace, simple_trace_data and simple_trace_start
parameters to generate a sim-safe-like trace for easy
comparison with simplescalar results. Needed for PISA
debugging.
sim/sim_events.hh:
remove extra space
sim/main.cc:
Fix dump() for floss-reasons
Segfault can now dump core
sim/simple_cpu.cc:
sim/simple_cpu.hh:
Get rid of obsolete call from misguided thread scheduling experiment.
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
add new alpha instructions for starting and ending intervals
dev/disk_image.cc:
dev/disk_image.hh:
Make the copy-on-write disk image use hash_map
base/callback.hh:
Generic callback class and callback queue for random use
sim/main.cc:
sim/sim_events.cc:
sim/sim_exit.hh:
Move exit stuff into it's own file. Make an exit callback queue so that
generic callbacks can be invoked upon simulator exit
dev/disk_image.cc:
give a mode that makes sense
dev/disk_image.cc:
dev/disk_image.hh:
Rework the object implementation of the copy-on-write disk image.
- Allow a child name and an initial table size to both be specified
- Add a read only flag that determines if changes to the image are written
back to disk.
- If the flag is not read only, and there is no initial image to open, that's
ok, just create an initial empty table.
- If the table is to be written back to disk, schedule an ExitCallback to
write the image back when the simulator exits.
base/callback.hh:
make this work in g++ 3
base/misc.cc:
base/pollevent.cc:
base/pollevent.hh:
base/trace.hh:
sim/pc_event.cc:
sim/universe.cc:
declare sim_cycle in one place
arch/alpha/alpha_memory.cc:
dev/alpha_console.cc:
more sim_cycle cleanup
sim/eventq.hh:
fix priority handling in the event queue:
if an event is scheduled with a priority once, then don't overwrite the
priority if it is subsequently scheduled without a priority
dev/console.cc:
send a carriage return/newline pair to the output manually since cprintf
and friends would interpret this and send out endl
dev/console.cc:
dev/console.hh:
add option to save console output to a file
sim/simple_cpu.cc:
sim/simple_cpu.hh:
Rework cache interface to avoid trying to loop inside of tick().
Should work much more cleanly with timing memory now (even for
multiprocessor systems).
sim/simple_cpu.cc:
a whole bunch of cleanup foo
sim/eventq.cc:
events can't be scheduled in the past anymore
sim/eventq.cc:
sim/eventq.hh:
create doEventLoop(), this continually cycles through the event queue
consuming events until there are none left
dev/console.hh:
Make this work in g++ 3
sim/sim_events.cc:
sim/sim_events.hh:
Make the act of ticking all cpus an event. Automatically schedule it
every cycle
sim/debug.cc:
sim/main.cc:
sim/sim_events.cc:
rearrange code to get rid of sim_smt.cc
sim/main.cc:
oops. bring back the SIM:cycle stat
arch/alpha/ev5.cc:
sim/simple_cpu.cc:
move the break_ipl check to the point where the IPL is actually set
sim/debug.cc:
Make the debug break event first in any given cycle
sim/simple_cpu.cc:
sim/simple_cpu.hh:
Split I-cache and D-cache stall cycles out from idle cycles in statistics.
sim/prog.hh:
- Replace SLAT maps with hash_maps
- Add hash<> specializations for md_addr_t,
counter_t, etc.
- Increase max file descriptors from 15 to 100
(parser00 was running out)
sim/simple_cpu.cc:
A few baby steps toward full-system detailed CPU.
ev5_trap() now sets both PC & NPC (not just NPC).
base/misc.cc:
base/trace.cc:
New memory model
Doxyfile:
Configuration file for doxygen. Generates documentation in /n/zizzer/z/m5docs.
To generate docs, run "doxygen Doxyfile" in the root directory of your copy of the head.
To comment your code you use a javadoc like syntax, a cstyle comment with 2 stars at the front (/**). For example
/** Everything before the first period is a brief description. This is a detailed description.
@param <name> description of parameter to function
@retval <name/type> description of function return value.
@sa (for see also) generate links to other class/enum/member/etc.
*/
You should start your files out with a comment like:
/** @file
Brief description of the file.
Detailed description if needed.
*/
See TimingMemobj.hh for more examples.
dev/ethertap.cc:
Make this work on OpenBSD
sim/main.cc:
sim/sim_events.cc:
sim/sim_events.hh:
sim/sim_exit.hh:
Make it possible to set an exit code for the exit event.
Also, make exit_now not visible to the rest of the simulator so that people
will know to create an exit event.
Finally, don't include callback.hh since we don't have to.
sim/sim_events.cc:
use the SimExitEvent to make sure that we exit at the end of the cycle
arch/alpha/fake_syscall.cc:
don't use exit_now() create a SimExitEvent()
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
Add an instruction that causes M5 to exit, allowing processes running under
simulation to cause the simulation to terminate
sim/simple_cpu.cc:
in full system mode, don't panic on an unknown opcode
dev/disk_image.cc:
dev/disk_image.hh:
convert stdio to streams
sim/system.cc:
remove uneeded include
base/cprintf.cc:
%p is an integer (more or less)
sim/system.cc:
sim/serialize.cc:
missing include
dev/disk_image.cc:
cast to correct types for proper interface usage
base/circlebuf.cc:
base/intmath.h:
base/remote_gdb.cc:
base/res_list.hh:
In c++, we use std::min, std::max, true, and false, not ano of the other junk
sim/sim_events.cc:
make a local copy of the data since the object can get deleted
dev/alpha_console.cc:
dev/alpha_console.hh:
Added parameter for number of CPUs to console, defualt=1
sim/sim_events.cc:
sim/simple_cpu.cc:
sim/system.cc:
sim/system.hh:
use cprintf.
general cleanup
remove unneeded c_str() calls.
base/cprintf.cc:
make %% work
base/cprintf.cc:
handle %% better
test/cprintftest.cc:
better testing
arch/alpha/alpha_memory.cc:
convert to use iostream and cprintf instead of stdio and fprintf
base/cprintf.cc:
more accurately implement formatting for floating point numbers
test/cprintftest.cc:
more tests
base/inifile.cc:
base/inifile.hh:
base/symtab.cc:
base/symtab.hh:
dev/disk_image.hh:
sim/base_cpu.cc:
test/Makefile:
convert everything to use hash_map instead of my old hash table junk
base/hashmap.hh:
base/inifile.hh:
dev/disk_image.hh:
since people don't agree on where hash_map belongs, pull it into the
m5 namespace and include hashmap.hh whenever a hashtable is needed
sim/memtest.cc:
Move Cache only calls (block_size, hit_latency, etc.) out of TimingMemObject and into CPUMemInterface. Changes to everywhere they were called on a TimingMemObj.
sim/param.hh:
Fix handling of operator[] for EnumVectorParam classes.
Also fix some line wrapping problems caused by adding 'std::'.
base/trace.cc:
base/trace.hh:
Extend trace facility to either print immediately to an ostream or
maintain a circular buffer of trace entries (dumpable from debugger
by calling dumpTrace()). Also change flags to use SimpleEnumVectorParam
so we can just give a list of names instead of a big hex value.
sim/exetrace.cc:
sim/exetrace.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
Integrate execution trace code into new trace facility. Eliminates
the need for a separate execution trace log. Enable instruction tracing
using --trace:flags=InstExec.
base/misc.cc:
Dump trace buffer in panic().
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
sim/simple_cpu.cc:
set up an annotations.hh file where inline annotation functions that do
nothing exist. This allows people to hack in annotations all in one file
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
intervals are really annotations
arch/alpha/ev5.cc:
Factor out more annotations
arch/alpha/ev5.cc:
sim/simple_cpu.cc:
Make an Annotate namespace, and add a DumpStats method to it
dev/disk_image.cc:
sim/main.cc:
sim/sim_events.cc:
sim/sim_exit.hh:
Normalize exit-related function names.
Move exitNow() prototype to simexit.hh.
base/misc.cc:
base/trace.cc:
base/trace.hh:
sim/eventq.cc:
sim/eventq.hh:
sim/exetrace.cc:
sim/exetrace.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
Minor cleanup on new tracing code:
- namespace cleanup
- fix bug in Trace::Log::dump
- added new RawDumpRecord to put raw data in trace buffer
(call Trace::rawDump, was Trace::dump)
- added --trace:flags=All to set all trace flag bits
- added --trace:dump_on_exit option to dump trace buffer on normal exit
- DPRINTF now requires 'const char *' for format (not string) so it
doesn't go away by the time buffer is dumped
sim/sat_counter.hh:
sim/serialize.hh:
foo(void) --> foo()
This commit is equivalent to doing the following in the sim directory:
perl -pi -e 's/\(void\)/()/' *.cc *.hh
sim/base_cpu.hh:
sim/eventq.cc:
sim/hybrid_pred.cc:
sim/hybrid_pred.hh:
sim/memtest.cc:
sim/predictor.hh:
sim/sat_counter.cc:
sim/sat_counter.hh:
Move dump() and reg_stats() implementations out of header files.
Clean up #includes.
sim/exec_context.hh:
sim/exetrace.cc:
sim/exetrace.hh:
sim/main.cc:
Clean up identification and handling of prefetches and no-ops.
Added is_data_prefettch() method to DynInst. (One of these days
we'll have to change all those functions to isFoo() style.)
Changes nop count statistic... we were only counting Alpha UNOPs
before, not all Alpha NOP forms.
sim/pc_event.cc:
sim/simple_cpu.cc:
- Strip opt binaries after build
- Update Makefile for new source files
- Fix BHGP prefetcher to use compressed addresses
- Fix FULL_SYSTEM compile problems (missing header includes)
base/inifile.cc:
Make it possible to override variables in the inifile and on the command line
sim/simple_cpu.cc:
sim/simple_cpu.hh:
- Make the SLAT useable with SimpleCPU for quick
and easy debugging. This required refactoring some
of the traits classes which should make them
marginally more independent.
- Fix bogus assert in the SLAT code. Alias load/store
values should only be assumed equivalent in non-spec mode.
sim/simple_cpu.cc:
- Must send the saved address to the SLAT for all memory
operations because execution could have overwritten
the base register.
sim/simple_cpu.cc:
sim/simple_cpu.hh:
Added Parameter for CPU identification number in Full System
Primary CPU ID is 0, which is the default value
Modified to start all CPU's in Halted status except the primary CPU
dev/alpha_console.cc:
Added comments to code for needed implementation in order to boot second CPU
dev/alpha_console.cc:
sim/exec_context.cc:
sim/exec_context.hh:
sim/simple_cpu.cc:
sim/system.cc:
sim/system.hh:
Added array of Execution Contexts to system.hh
Used when trying to launch another CPU
Added cpu_id to Full System ExecContext
Fixed the launch in alpha_console.cc to access the correct exe_ctx
dev/alpha_console.cc:
sim/simple_cpu.cc:
Fixed initializtion and launch of the second processor
Added a gdb-alpha debug port for non-primary processor
Cleaned up the .ini file of unneeded disk images
sim/simple_cpu.cc:
Add cpu_id (see Ron's recent commit) to full-system detailed CPU.
base/trace.cc:
Fix bug in calling dumpTrace() on partially filled trace buffer.
test/Makefile:
test/lru_test.cc:
- Replace BHGP associative table with something
simpler.
- Add lru_test to test out new AssociativeTable
class.
Doxyfile:
Only create documentation for documnented classes
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
cleanup and formatting
sim/simple_cpu.cc:
Fix bus queueing delay and idle stats. Slight change to one scheduling case. Set req->time in SimpleCPU so delays are correctly computed.
sim/simple_cpu.cc:
Don't do an icache fetch if we had an ITLB miss.
arch/alpha/alpha_memory.cc:
dev/alpha_console.cc:
sim/serialize.cc:
sim/serialize.hh:
Replace include of inifile.hh in serialize.hh with forward decl
of class IniFile. Requires adding explicit include of inifile.hh
in several .cc files.
sim/eventq.hh:
Get rid of needless include of inifile.hh.
sim/main.cc:
base/inifile.cc:
base/inifile.hh:
Check for unreferenced parameters to detect obsolete settings and
typos. A warning for an unreferenced parameter section can be
suppressed by adding a 'unref_section_ok=y' parameter to the section.
Warnings for any unreferenced parameters within a section can be
suppressed by adding a 'unref_entries_ok=y' parameter to the section.
(The value doesn't matter; the presence of the parameter is all that
is tested.)
By default any unreferenced parameter or parameter section warnings
will cause the simulator to terminate. Use the '-u' command-line
option to suppress this behavior (at your own risk!).
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/console.cc:
dev/console.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/pcireg.h:
dev/simple_disk.cc:
dev/simple_disk.hh:
sim/eventq.hh:
sim/serialize.hh:
sim/sim_object.hh:
Add some Doxygen comments. Mostly putting in markers for the file and classes
Also some minor formatting fixes here and there
arch/alpha/ev5.cc:
Reindent to 4 spaces (plus a few other very minor formatting changes).
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
Reindent.
sim/eventq.hh:
Don't even bother with the description unless TRACING_ON is defined.
Not a big deal at this point, since TRACING_ON is currently hardcoded
to 1 in base/trace.hh.
base/remote_gdb.cc:
base/trace.hh:
sim/eventq.cc:
sim/eventq.hh:
sim/system.cc:
Clarify debugging defines:
- DEBUG is either defined or not, but is not given a value. It should
be tested with #ifdef.
- TRACING_ON is always defined, either with a 0 or 1 value. It should
always be tested with #if.
Automatically set TRACING_ON value according to whether DEBUG is defined.
Added -Wundef to warnings to catch '#if DEBUG' cases.
(Yes, '#if DEBUG' does the right thing if DEBUG is not defined, but the
same is not true for '#ifdef TRACING_ON' if TRACING_ON is defined to 0.)
In the long run, perhaps the uses of TRACING_ON outside of the trace
package itself should be converted to use DEBUG.
sim/pc_event.cc:
Looks like a lot of device code has never been compiled w/o TRACING_ON set;
fix up several warnings (mostly unused variables).
sim/pc_event.cc:
Oops... needs to compile w/o FULL_SYSTEM too.
base/trace.hh:
sim/main.cc:
sim/param.cc:
sim/param.hh:
sim/sim_object.cc:
Fix up parameter printing controls. Parameters are always printed by
default; new command-line parameter '-q' turns this off. Old system
was broken in two ways: there was no way to turn off printing in the
optimized binary, and controlling printing with a trace flag bit (specified
as an .ini parameter) meant that parameters parsed *before* trace:flags
never got printed.
Also added code to print the names of unspecified parameters as comments
in the output.
base/remote_gdb.cc:
base/trace.hh:
A couple more changes to get full-system to compile w/o tracing.
sim/simple_cpu.hh:
sim/simple_cpu.cc:
- Add stats for simple SLAT profiling
sim/simple_cpu.cc:
Extend HAVE_TSL protection so it can compile without TSL
base/trace.cc:
Need to update flag strings to match enum... yuck.
sim/system.cc:
sim/system.hh:
Build global list of system objects.
Add gdb-callable printSystems() function so we can find system
object pointers from inside debugger.
sim/eventq.cc:
sim/simple_cpu.cc:
base/pollevent.cc:
base/pollevent.hh:
Move pollQueue handling into main event loop so it works regardless
of the CPU model.
arch/alpha/ev5.cc:
Protect IPRs etc. from being modified on misspeculated paths.
arch/alpha/ev5.hh:
Eliminate some unused macros.
arch/alpha/alpha_memory.cc:
Don't update IPRs for TLB misses on misspeculated instructions.
Set req.flags PHYSICAL and UNCACHEABLE bits as appropriate
based on results of translation.
sim/param.cc:
Move ConfigHierarchy::Node definition into separate file so it can be
included only where necessary.
arch/alpha/fake_syscall.cc:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
base/circlebuf.cc:
base/circlebuf.hh:
base/cprintf.hh:
base/fifo_buffer.cc:
base/fifo_buffer.hh:
base/inifile.cc:
base/inifile.hh:
base/misc.hh:
base/mod_num.hh:
base/pollevent.cc:
base/remote_gdb.cc:
base/sched_list.hh:
base/socket.cc:
base/socket.hh:
base/str.cc:
base/str.hh:
base/symtab.cc:
dev/alpha_access.h:
dev/etherint.cc:
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/debug.cc:
sim/hybrid_pred.cc:
sim/hybrid_pred.hh:
sim/param.cc:
sim/param.hh:
sim/pc_event.cc:
sim/predictor.hh:
sim/sat_counter.cc:
sim/sim_object.cc:
sim/simple_cpu.hh:
test/cprintftest.cc:
test/lru_test.cc:
test/nmtest.cc:
test/offtest.cc:
test/sized_test.cc:
test/symtest.cc:
util/tap/tap.cc:
Add CVS Id tags
dev/alpha_console.cc:
dev/alpha_console.hh:
Get rid of pmask field in MemReq; move address mask into devices
by adding to common base class FunctionalMemory.
base/inifile.cc:
Don't complain if "unref_section_ok" or "unref_entries_ok"
are not referenced.
base/inifile.cc:
Add functionality to "unref_entries_ok":
Now, the RHS is parsed for a list of unreferenced entries, only these will be "OK"
Note that this will not be needed very often...
base/trace.cc:
sim/exetrace.cc:
Make trace cycle number position and format consistent between DPRINTF
trace records and exetrace records.
sim/debug.cc:
Add "debug" parameter context for global debug options.
Add parameter "debug:break_cycles" to set DebugBreakEvent(s)
from ini file/command line.
sim/pc_event.cc:
sim/system.hh:
sched_break_pc() now sets a breakpoint on *all* systems.
Use sched_break_pc_sys() to set a breakpoint on just one system.
sim/debug.cc:
sim/pc_event.cc:
base/cprintf_formats.hh:
using namespace std
dev/alpha_console.cc:
sim/exec_context.cc:
sim/exec_context.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
arch/alpha/fake_syscall.cc:
sim/prog.cc:
use accessor functions to set/get status to prepare to not call
SimpleCPU::tick if there is nothing to do
sim/simple_cpu.cc:
no more simplescalar here
base/trace.hh:
Only set TRACING_ON according to DEBUG if it hasn't already been
set on the command line.
base/trace.cc:
If compiled with TRACING_ON=0, give an error if the user tries to
turn on tracing.
sim/main.cc:
Get rid of do-nothing segfault handler... if you get a segfault in an exit
handler, you end up with an infinite recursion.
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
sim/exec_context.cc:
sim/exec_context.hh:
sim/pc_event.cc:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
Full-system detailed CPU almost almost there. Big reorganization of
virtual address translation code, so we can tell an access is uncached
soon enough to suppress it if it's on the wrong path: translation is its
own step now, not hidden inside the (former) VirtualMemory object.
Also a few other changes to avoid bad things on misspeculated paths.
This commit results in *very* small changes in IPCs and MSIPCs (a
few tenths of a percent max on the tests) because some wrong-path
instructions get handled a little differently.
sim/main.cc:
Put quotes around args with spaces when echoing command line.
sim/pc_event.cc:
Process PC Events just before fetching the relevant instruction instead
of just after the previous instruction. Keeps us from missing events
when we take off on misspeculated paths.
** Detailed CPU now gets to single-user prompt!! **
sim/base_cpu.hh:
sim/eventq.hh:
sim/main.cc:
sim/sim_events.cc:
sim/sim_events.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
get rid of the TickAllEvent and make it so each cpu has its own tick event.
In the process, the implementation of the virtual functin tick() got moved
into a non virtual function _tick() so that the tick event could be CPU
specific and you wouldn't pay the virtual function call overhead.
This is another step towards being able to not tick a cpu if it has nothing
to do
sim/base_cpu.hh:
sim/simple_cpu.hh:
Now that tick is called via an event, we no longer need a virtual function
sim/base_cpu.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
clean up the tick event stuff and get rid of the TickEvent template class
and just make one for each class since you may want a different process()
function anyway
base/trace.cc:
base/trace.hh:
sim/base_cpu.hh:
sim/pc_event.cc:
sim/pc_event.hh:
Fix up branch predictor's return address stack when we do a SkipFuncEvent.
Since there's no easy way to figure out what thread ID we're on from
the SkipFuncEvent, we just fix thread 0's RAS... will need to fix this
when we get SMT full-system up.
Also:
- Moved RAS tracing stuff to DPRINTFs; added BranchPredRAS trace flag.
- Made BadAddrEvent derive from SkipFuncEvent to eliminate code duplication.
base/trace.cc:
sim/eventq.cc:
sim/eventq.hh:
sim/serialize.cc:
Create a flags bitvector in the event to store flags. Holds what used to be
squashed and scheduled, and also contains a new flag for auto delete.
The auto delete flag will make the eventq responsible for calling delete on
an event. This makes 'delete this' unnecessary in the process() function.
This is most beneficial for events that get squashed since process() never
gets called, and one might want to have the data reclaimed.
To use the autodelete functionality with squash, a few events were cleaned up
and reorganized
sim/exec_context.cc:
sim/exec_context.hh:
sim/pc_event.cc:
sim/simple_cpu.cc:
Add thread_num field to ExecContext so it knows which CPU thread
context it represents. Need this for the SkipFuncEvent RAS fixup,
but seems generally useful.
dev/etherdump.cc:
use time.h instead of sys/time.h
sim/simple_cpu.cc:
sim/simple_cpu.hh:
move the tick schedule() to where it's needed
dev/alpha_console.cc:
dev/alpha_console.hh:
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/exec_context.cc:
sim/exec_context.hh:
sim/intr_control.cc:
sim/intr_control.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
get rid of the processor SimObject and move all of the interrupt stuff into
BaseCPU since it really is part of the CPU anyway
sim/exec_context.hh:
fix store conditional
sim/exec_context.hh:
clean up conditional store so that it's more understandable
sim/base_cpu.cc:
sim/base_cpu.hh:
move interrupt set/clear routines into the .cc file and make them virtual
so that CPUs derived from BaseCPU can modify the behaviour of the interrupt
routine.
base/trace.cc:
base/trace.hh:
New trace flags generation via perl script. Now if you want to add a
flag you just type it once (in the script) and all the C++ is generated
automagically. Also supports "compound" flags that can be specified
on the command line and map to multiple regular flags.
Switched trace flags from 64-bit bitmap to vector<bool> for scalability.
base/trace.cc:
comment out the offending assign since it is commented as not needed
base/trace.cc:
Get rid of useless code.
sim/base_cpu.cc:
sim/base_cpu.hh:
change variable name to avoid confusion
arch/alpha/ev5.cc:
sim/simple_cpu.cc:
Remove a bunch of istats stuff and insert some annotations for where they
were.
sim/debug.cc:
add a function to force stats to be dumped from the debugger
sim/base_cpu.hh:
sim/exec_context.cc:
sim/exec_context.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
Don't schedule tickEvent until it is known that there will be something to do
test/Makefile:
Make tests compile again
test/Makefile:
Make the whole build process for tests a bit simpler
util/tap/Makefile:
make this build again, clean stuff up
sim/exec_context.cc:
sim/simple_cpu.cc:
make stuff compile when not FULL_SYSTEM
sim/main.cc:
Add the name of the execution host to the output
sim/main.cc:
Don't free() data returned by getenv.
besides, free() is a function, not an operator like sizeof
sim/eventq.cc:
That assertion should have never been committed
sim/simple_cpu.cc:
don't tick here
sim/eventq.cc:
the squashed flag should be cleared once the event has actually been processed
sim/simple_cpu.cc:
we can get here with a dcache miss as well.
sim/simple_cpu.cc:
only schedule the event if it is not already scheduled.
arch/alpha/fake_syscall.cc:
Zero out syscall arg buffer to avoid copying garbage into simulator space.
sim/exec_context.hh:
Translation in non fullsystem mode. And use the FALRU class to implement FA LRU caches.
sim/base_cpu.hh:
sim/exec_context.cc:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
Reorganize code a bit so that multiple CPUs can properly work with the
new tick as event stuff.
arch/alpha/arguments.hh:
base/cprintf.hh:
base/refcnt.hh:
dev/etherpkt.hh:
Make a refcounted base class that contains the refcounting stuff and make
everything use it
sim/main.cc:
don't print out the host if we didn't find one
dev/alpha_console.cc:
dev/alpha_console.hh:
s/memreq/MemReq/
base/trace.cc:
Add support to echo trace output (DPRINTF etc.) to cerr as well as
the trace buffer. From gdb, call "echoTrace(1)" to enable, or
"echoTrace(0)" to disable. As a side effect, semantics of setting
both trace:bufsize and trace:file are different now (will buffer
and send to file, where old version would just buffer), but I doubt
anyone ever did that anyway. See comments in file for more details.
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/debug.cc:
sim/eventq.cc:
sim/eventq.hh:
sim/memtest.cc:
sim/memtest.hh:
sim/sim_events.cc:
sim/sim_events.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
Revamp event debug/tracing structure.
- virtual const char *description() method replaces description string
constructor argument. Lets us associate a fixed description string
with each class of events with basically no overhead.
- virtual void trace(char *action) method lets event subclasses
customize tracing DPRINTF call to put in additional information.
Currently only used by WritebackEvent (to print sequence number
of associated instruction).
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.hh:
Fix up full-system events for new debug structure.
base/trace.cc:
Looks like g++ 3 doesn't like "string = bool ? string : char*".
sim/simple_cpu.cc:
the caches currently won't completion events for UNCACHEABLE accesses, so
don't send any.
Warning, this is a HACK!
dev/etherdump.cc:
sim/main.cc:
cleanup includes, and remove some #ifdef cruft for BFD
sim/sim_exit.hh:
Added GDB-callable exitNow() using char *
sim/sim_events.hh:
Need to include eventq.hh here.
test/Makefile:
There are no OPT_FLAGS
arch/alpha/fake_syscall.cc:
dev/etherdump.cc:
sim/eventq.cc:
sim/main.cc:
sim/memtest.cc:
sim/serialize.cc:
sim/sim_events.cc:
sim/sim_time.hh:
sim/simple_cpu.cc:
sim/system.cc:
Get rid of sim.h & sim_smt.hh. Most of what was in those was obsolete anyway.
Move needed externs into universe.hh & stats.hh, plus new header file
sim_time.hh.
sim/memtest.cc:
sim/memtest.hh:
Update memtest cpu to new tickEvent stuff
base/remote_gdb.cc:
Adding returns to make insure happy.
sim/simple_cpu.cc:
Rework Interporcessor Interrupts to properly signal second CPU, and unsuspend it
sim/intr_control.hh:
Fix clock interrupt to signal both proccesors correctly in MP system
sim/system.cc:
Fix seg fault in single proccesor mode from last commit, MP now boots with 2 CPUs
sim/simple_cpu.cc:
sim/system.cc:
sim/system.hh:
Changes to genaralize the interupt scheme to variable number of proccessors
base/misc.cc:
only dump the trace buffer if tracing is turned on
base/str.cc:
properly deal with the case where there is only one string in the list
base/cprintf.cc:
base/cprintf.hh:
Add csprintf() to print to a string (sort of like sprintf())
base/cprintf.cc:
be consistent about resetting parameters to original values
base/cprintf.cc:
cleanup
base/statistics.cc:
base/statistics.hh:
Finally commit my new stats package and stop tinkering with it.
This new stats package has support for all sorts of stuff.
Documentation will appear in the code in a future commit.
test/Makefile:
test/stattest.cc:
add tests for the statistics package. This exercises all sorts of different
capabilities of the stats package and can be used for examples.
util/rundiff:
rundiff utility
Normal diff reads in all of both input files and tries to generate a minimal
diff, for super long trace files, this is bad because it takes forever and
you run out of memory. rundiff is designed to scan the input files and
compare only 2000 lines at a time. This way memory won't run out and a user
can use fifos for input files.
sim/exetrace.cc:
Print all reg results as 0x%016x.
arch/alpha/fake_syscall.cc:
base/misc.cc:
base/misc.hh:
base/pollevent.cc:
base/pollevent.hh:
base/statistics.hh:
base/trace.cc:
base/trace.hh:
dev/alpha_console.cc:
dev/etherbus.cc:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/debug.cc:
sim/eventq.cc:
sim/eventq.hh:
sim/exec_context.hh:
sim/exetrace.hh:
sim/hybrid_pred.hh:
sim/main.cc:
sim/memtest.cc:
sim/memtest.hh:
sim/pc_event.cc:
sim/prog.hh:
sim/sat_counter.hh:
sim/serialize.cc:
sim/sim_events.cc:
sim/sim_events.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
sim/universe.cc:
test/nmtest.cc:
test/stattest.cc:
test/symtest.cc:
Global variable renaming. Basically equivalent to the following perl:
s/\btick_t\b/Tick/g;
s/\bsim_cycle\b/curTick/g;
s/\bcounter_t\b/Counter/g;
s/\bsim_freq\b/ticksPerSecond/g;
dev/console.cc:
dev/etherbus.cc:
dev/etherdump.cc:
dev/etherlink.cc:
dev/ethertap.cc:
Get rid of some explicit externs (use header files!).
dev/ethertap.cc:
Include for panic().
arch/alpha/alpha_memory.cc:
sim/exec_context.hh:
Various bug fixes. Charge all writebacks to thread 0
sim/eventq.cc:
sim/eventq.hh:
sim/main.cc:
rework the event loop a bit so that we can prepare for dealing with
asynchronous events properly.
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
base/refcnt.hh:
dev/alpha_console.cc:
dev/alpha_console.hh:
sim/exec_context.hh:
sim/memtest.cc:
sim/memtest.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
Initial move to reference counting MemReq objects. Switched to STL containers for storage in the memory hierarchy.
sim/exec_context.hh:
Fix LL/SC and got 1-6 CPUs working by fixing clock interrupt
sim/simple_cpu.cc:
Add the IIC as a selectable cache tag. Fix translation for now with a quick hack.
sim/exec_context.hh:
Put detection logic on failed Store Conditionals to help detect deadlock situations
util/term/Makefile:
util/term/term.c:
Whittle down netcat to the bare minimum to connect to another machine
and add the proper stuff to do some terminal handling to make this utility
sufficient for connecting to m5 to get a console
util/term/Makefile:
add an install target
base/pollevent.cc:
sim/async.hh:
sim/main.cc:
Don't create events in signal handlers since it really isn't safe. I'm not
positive if some bugs I've seen were caused by this, but we may as well
be safe
base/pollevent.cc:
base/pollevent.hh:
dev/console.cc:
dev/console.hh:
sim/async.hh:
sim/main.cc:
- clean up the pollevent stuff and just do the poll whenever requested since
we will request it with the proper frequency
- add an alarm to poll once every second in addition to waiting for sigio
- remove all of the telnet crap since I'm never planning on implementing it
- fix detaching and re-attaching of consoles
base/pollevent.cc:
base/pollevent.hh:
sim/main.cc:
only handle/raise SIGALRM if we're polling
sim/memtest.cc:
sim/cache/lzss_compression.hh:
sim/cache/null_compression.hh:
Initial check in of Compression stuff and IIC subblocking.
base/remote_gdb.cc:
Get rid of needless extern.
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/fake_syscall.cc:
dev/alpha_console.cc:
dev/alpha_console.hh:
sim/exec_context.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
Rename fault type and fault codes as follows:
s/md_fault_type/Fault/g;
s/md_fault_none/No_Fault/g;
s/md_fault_mcheck/Machine_Check_Fault/g;
s/md_fault_opdec/Unimplemented_Opcode_Fault/g;
s/md_fault_alignment/Alignment_Fault/g;
s/md_fault_overflow/Integer_Overflow_Fault/g;
s/md_fault_reset/Reset_Fault/g;
s/md_fault_arith/Arithmetic_Fault/g;
s/md_fault_interrupt/Interrupt_Fault/g;
s/md_fault_ndtb_miss/Ndtb_Miss_Fault/g;
s/md_fault_pdtb_miss/Pdtb_Miss_Fault/g;
s/md_fault_dtb_fault/Dtb_Fault_Fault/g;
s/md_fault_dtb_acv/Dtb_Acv_Fault/g;
s/md_fault_itb_miss/Itb_Miss_Fault/g;
s/md_fault_itb_fault/Itb_Fault_Fault/g;
s/md_fault_itb_acv/Itb_Acv_Fault/g;
s/md_fault_fen/Fen_Fault/g;
s/md_fault_pal/Pal_Fault/g;
s/md_fault_NUM/Num_Faults/g;
Also changed 'enum md_fault_type' to just 'Fault' where possible.
sim/exec_context.cc:
sim/exec_context.hh:
Add a constructor to specify a memory without a process
sim/eventq.hh:
clean up a bit.
When events are resecheduled or removed from the schedule, they are no longer
squashed. (Only scheduled events can be squashed.)
sim/simple_cpu.hh:
check to see if the tick event was squashed. If it was squashed, then it must
be rescheduled since squashed events are scheduled.
sim/exec_context.cc:
sim/exec_context.hh:
This new constructor is only for non FULL_SYSTEM
base/statistics.cc:
base/statistics.hh:
test/stattest.cc:
Remove unused variable
dumpStats -> dump
initStats -> init
use const string & instead of const char *
make Base constructor explicit
more consistent formatting widths
sim/main.cc:
sim/sim_events.cc:
make the new stats package useable in the simulator
base/statistics.cc:
base/statistics.hh:
test/stattest.cc:
create two standard stats that are to be used for calculations:
elapsedTicks - is the number of ticks that has elapsed during this
simulation. Currently, this is just curTick, but this may change when
we have checkpointing.
elapsedSeconds - is the number of simulated seconds that have elapsed during
the simulation. Currently, this is just elapsedTicks / ticksPerSecond.
sim/main.cc:
Need to initialize stats much sooner so that SimObject constructors can
register statistics
base/statistics.cc:
- use the stat_print_descriptions variable that the old stats package provides
this is just a quick hack for now. When the old stats package goes away,
we'll move this.
- Fix the sorting algorithm so it works as I had intended
- Make the output field widths equivalent to the old stats package
base/statistics.cc:
clean up memory
sim/sim_events.cc:
sim/sim_events.hh:
Use autodelete
sim/sim_events.cc:
oops. didn't mean to commit this part
util/tap/Makefile:
call it m5tap instead of ethertap
sim/exec_context.hh:
Get rid of a couple of unnecessary forward class declarations.
sim/memtest.cc:
sim/memtest.hh:
Adds compression to the memory hierarchy as well as using ExecContext to access memory. Added a few related config files.
base/cprintf.cc:
Default fill char is space, regardless of what stream fill char is.
sim/exetrace.cc:
Convert some of the hairier format things to ccprintf.
base/statistics.cc:
try getting the sorting a bit better
arch/alpha/arguments.hh:
base/refcnt.hh:
base/statistics.hh:
dev/etherpkt.hh:
s/refcounted/RefCounted/
s/refcnt/RefCountingPtr/
arch/alpha/fake_syscall.cc:
Zero out register files for newly created threads to make non-full-system
MP runs deterministic.
sim/exetrace.cc:
Don't trace the results of NOPs or prefetches (for easier comparison
with traces from new decoder).
sim/exetrace.cc:
Don't trace branch link values written back to R31 either.
Also put a ifdef TARGET_ALPHA around this hack.
sim/exetrace.cc:
Need another ifdef TARGET_ALPHA...
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/arguments.cc:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/fake_syscall.cc:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
base/object_file.hh:
base/remote_gdb.cc:
base/remote_gdb.hh:
base/symtab.cc:
base/symtab.hh:
dev/alpha_console.cc:
dev/simple_disk.cc:
dev/simple_disk.hh:
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/exec_context.cc:
sim/exec_context.hh:
sim/exetrace.hh:
sim/memtest.cc:
sim/memtest.hh:
sim/pc_event.cc:
sim/pc_event.hh:
sim/prog.cc:
sim/prog.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
sim/system.cc:
sim/system.hh:
test/nmtest.cc:
test/symtest.cc:
Massive renaming to (almost) eliminate all md_* and MD_* names
in preparation for total exorcism of machine.def.
Most of the changes in this commit were performed with the
following perl script (perl -pi <script> <files>). A small
amount of manual fixup was needed to (mostly getting rid of
the Addr typedefs in the various memory objects now that
the former md_addr_t has that name).
# rename machine-dependent types and constants (will be moving into ISA traits object)
s/md_addr_t/Addr/g;
s/md_intreg_t/IntReg/g;
s/md_gpr_t/IntRegFile/g;
s/md_fpreg_t/FloatReg/g;
s/md_fpr_t/FloatRegFile/g;
s/md_ctrlreg_t/MiscReg/g;
s/md_ctrl_t/MiscRegFile/g;
s/md_ipr_t/InternalProcReg/g;
s/md_anyreg_t/AnyReg/g;
s/md_inst_t/MachInst/g;
s/regs_t/RegFile/g;
# manually fix declaration in old/regs.h and a few forward decls
s/struct RegFile/RegFile/g;
s/MD_NUM_IREGS/NumIntRegs/g;
s/MD_NUM_FREGS/NumFloatRegs/g;
s/MD_NUM_CREGS/NumMiscRegs/g;
s/MD_IPR_NUM/NumInternalProcRegs/g;
s/MD_TOTAL_REGS/TotalNumRegs/g;
s/MD_REG_ZERO/ZeroReg/g;
base/statistics.hh:
test/stattest.cc:
Create a functor() wrapper for the stats package. This wrapper makes it
possible to write an actual function or functor that is evaluated in a
Formula
base/statistics.hh:
test/stattest.cc:
Implement operator += for formulas. This allows us to build a formula without
knowing all variables involved at compile time
sim/sim_object.cc:
sim/sim_object.hh:
Make a different regStats pass for the new stats package
base/statistics.cc:
base/statistics.hh:
sim/main.cc:
Move simulator specific stuff to its own file.
rename elapsedFoo to simFoo so it's clear we're talking about what's been
simulated.
Use the functor method to get the time.
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/main.cc:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
Convert instruction counting to new stats package.
Convert the rest of SimpleCPU to new stats
Do a bit of cleanup while we're at it
base/cprintf.cc:
attempt to deal with the badbit problem
sim/base_cpu.hh:
sim/simple_cpu.cc:
no need for reg_stats to be pure virtual
base/statistics.cc:
base/statistics.hh:
sim/simple_cpu.hh:
test/stattest.cc:
change names of stat classes so they are simpler
base/statistics.cc:
no unregestering stats
base/statistics.cc:
base/statistics.hh:
sim/main.cc:
test/stattest.cc:
make it so that none of the constructors for the various stats objects
take any parameters so that users may put them in arrays and stuff. Instead
provide initialization functions for the objects that needed parameters, and
provide a way to verify that all statistics that need initialization do
get initialized.
sim/cache/lzss_compression.hh:
Compression fixes. Added trivial data support to the IIC. Set the max write size in the compressed memory to 1024 bytes
sim/memtest.cc:
sim/memtest.hh:
Added 'percent_uncacheable' option to MemTest
base/statistics.cc:
base/statistics.hh:
keep track of more data in distributions
use a struct to pass data to the display function
take underflow and overflow out of the array
base/statistics.cc:
support for printing vector totals
sim/memtest.cc:
sim/memtest.hh:
Fix uncacheables to go to their own memory space.
sim/memtest.cc:
Change default percentage of uncacheables to 10%
base/statistics.cc:
base/statistics.hh:
Correctly calculate vector totals.
When a formula operates on vectors, it is incorrect to do calculate
the formula for each vector element, and then sum the final formula
vector. The correct way is to sum the individual vectors at the leaves
of the expression tree. And then perform the calculation as if it were
on scalar values.
Assume we have vectors A, and B, and X = A * B
The old way would have been: total(X) = total(A * B)
The new way is total(X) = total(A) * total(B)
Per thread miss rates are and example of something that would be calculated
incorrectly. If you were to sum all of the miss rates, you could get
a number greater than one. Calculating the overall miss rate should
just be overall misses / overall accesses
base/statistics.cc:
base/statistics.hh:
Create a #define STAT_DISPLAY_COMPAT that makes the new stat package output
match the old one.
arch/isa_parser.py:
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/arguments.cc:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/fake_syscall.cc:
arch/alpha/isa_desc:
arch/alpha/isa_traits.hh:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
base/bitfield.hh:
base/circlebuf.hh:
base/object_file.hh:
base/remote_gdb.cc:
base/symtab.hh:
dev/alpha_console.cc:
dev/console.cc:
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/exec_context.cc:
sim/exec_context.hh:
sim/exetrace.cc:
sim/exetrace.hh:
sim/main.cc:
sim/op_class.hh:
sim/pc_event.cc:
sim/pc_event.hh:
sim/prog.cc:
sim/prog.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
sim/static_inst.cc:
sim/static_inst.hh:
sim/system.cc:
sim/system.hh:
New ISA description system. No more machine.def!
Instructions are now decoded into StaticInst objects, and all static
instruction properties (including execution behavior) are associated
with those objects. Extended documentation in progress.
Currently supports Alpha only; PISA will not compile.
Use END_OF_MACHINE_DOT_DEF tag to extract previous version.
arch/isa_parser.py:
Make it more obvious that you shouldn't edit decoder.cc, and
harder to do so accidentally.
arch/alpha/isa_desc:
base/statistics.cc:
sim/exec_context.hh:
make stuff compile in g++ 3.x
fix some bad formatting
Doxyfile:
Put generated docs in local directory docs/doxygen.
Don't bother generating LaTeX, and a few other minor tweaks.
arch/isa_parser.py:
arch/alpha/isa_desc:
- Decouple isa_desc operand types from C++ types.
- Handle signed operand writebacks.
- Add a few comments to suppress doxygen warnings on decoder.cc.
sim/static_inst.cc:
sim/static_inst.hh:
Add some basic decode cache hash-table stats dumping (ifdef'd out).
sim/static_inst.cc:
Make it compile w/gcc3.
sim/static_inst.cc:
ostream doesn't seem to exist in 2.95
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
TLB statistics
arch/alpha/ev5.cc:
always pass the execution context to an annotation
arch/alpha/ev5.cc:
revert a bunch of crap from the last commit that I didn't want yet.
arch/isa_parser.py:
make it so that the ext source directory is grabbed from the right place
arch/alpha/alpha_memory.cc:
arch/alpha/ev5.cc:
arch/alpha/isa_desc:
arch/alpha/vtophys.cc:
base/remote_gdb.cc:
dev/alpha_console.cc:
sim/exec_context.hh:
sim/simple_cpu.cc:
get rid of MD_IPR_foo and call it IPR_foo
add some comments to describe what the various PALtemp registers do
formatting
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/exec_context.cc:
sim/exec_context.hh:
sim/simple_cpu.cc:
Keep a list of execution contexts in BaseCPU
Provide a mechanism to register per execution context statistics.
base/socket.cc:
base/remote_gdb.cc:
dev/console.cc:
dev/ethertap.cc:
don't panic if accept fails
sim/simple_cpu.cc:
sim/simple_cpu.hh:
keep track of fraction of cycles that are idle
base/statistics.hh:
make proxy nodes work better in formulas. (Now totals should work).
sim/op_class.hh:
Document OpClass enum.
sim/op_class.hh:
Need to document file for file members (enum, globals, etc.) to be extracted
arch/alpha/faults.cc:
arch/alpha/faults.hh:
arch/alpha/isa_traits.hh:
Move Fault into its own file, and provide a function to get the string name
of a fault
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/osfpal.cc:
arch/alpha/osfpal.hh:
move PAL code defines and such into their own file. Also provide a function
to get the name of a PAL code
arch/alpha/osfpal.cc:
make this actually compile and add it to the makefile
kern/tru64/tru64.hh:
dummy class for differentiating Tru64
kern/tru64/tru64_syscalls.cc:
kern/tru64/tru64_syscalls.hh:
Stuff on tru64 system calls
arch/alpha/ev5.cc:
arch/alpha/isa_desc:
sim/exec_context.cc:
sim/exec_context.hh:
Add a bunch of full system statistics
base/statistics.cc:
base/statistics.hh:
sim/sim_events.cc:
support for printing stats to a file. For now we will continue to print
to standard out so that the whole regression thing doesn't break.
While we're at it, move the Stat param context to the new stats package
sim/exec_context.hh:
sim/main.cc:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
Today saw the wholesale slaughter of greened's code. When we asked the accused, Erik Hallnor, why he did it he responded, 'Because I was bored. And the underlying prefetch cache was soon to be 2 generations out of date.'
sim/base_cpu.hh:
sim/exec_context.cc:
added a std::vector and using namespace std
arch/alpha/fake_syscall.cc:
Avoid conflicts with #defines in headers
arch/alpha/fake_syscall.cc:
I think this is what steve had in mind.
base/endian.hh:
get rid of the simplescalar endianness junk and make it a bit simpler
base/cprintf.cc:
base/cprintf.hh:
base/cprintf_formats.hh:
base/statistics.cc:
test/cprintftest.cc:
Break out the cprintf formatting stuff into per-type formatting so that we
can do special formatting based on type. This makes %c work correctly for
integer types. It also allows me to add a workaround for string format widths.
Finally, it allows me to accept stringstream directly as an argument without
having to use the .str() member.
Doxyfile:
Update Doxyfile to new version of doxygen and to use the newly install graphviz package.
Doxyfile:
Remove . from the file paths, instead of ..
base/cprintf.cc:
base/cprintf_formats.hh:
base/statistics.cc:
test/cprintftest.cc:
Fix printing of strings. Seems that I just can't do what I want with
templates. They're too smart for they're own good.
Fix format field widths for floating point numbers.
Remove some .str()'s that are no longer needed because cprintf supports them.
base/statistics.cc:
base/statistics.hh:
test/stattest.cc:
Make internal design a bit more consistent.
Re-work Bins and Vectors and how they work together to remove a level
of indirection.
base/statistics.cc:
base/statistics.hh:
revert that last change
base/statistics.cc:
base/statistics.hh:
test/stattest.cc:
let's try this again. This time we'll make DistStat classes initialize
their bins.
Also add a test for this
base/statistics.hh:
Proxy -> VectorProxy
Doxyfile:
Don't hide undocumented classes. This helps when tracking includes through the new graphs.
Doxyfile:
Make things run faster until documentation errors are gone
sim/prog.cc:
sim/simple_cpu.cc:
Change declarations to match defenitions.
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/console.cc:
dev/console.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/pcireg.h:
dev/simple_disk.cc:
dev/simple_disk.hh:
sim/eventq.hh:
sim/serialize.hh:
sim/sim_object.hh:
sim/simple_cpu.cc:
Removal of 1200 doxygen warnings. The 600 left are mostly from StaticInstBase and decoder.cc. I basically un-documented the partially documented code by changing /** to /*.
arch/alpha/ev5.cc:
Add FULL_SYSTEM protection to match header file.
Doxyfile:
dev/alpha_console.hh:
dev/etherint.hh:
dev/simple_disk.hh:
sim/simple_cpu.cc:
sim/static_inst.hh:
sim/cache/null_compression.hh:
Down to 464 warnings, all in static_inst.hh or decoder.cc. Punt on the template instantiation thing by making them invisible to doxygen.
arch/alpha/alpha_memory.cc:
base/statistics.cc:
base/statistics.hh:
sim/simple_cpu.cc:
test/stattest.cc:
New way of specifying information about printing stats.
old way:
stat.setFormat(name, ...);
new way:
stat
.name(...)
.desc(...)
.prereq(...)
.
.
;
This allows you to specify any information about the stats, and do it in any
order. It also cleans up the kinda crufty setFormat interfaces.
LICENSE:
This is the M5 license as agreed upon by the original M5 authors, and blessed
by the University of Michigan technology transfer office.
OK by Doug Hockstad <dhocksta@umich.edu>
base/statistics.hh:
missing_math is only for stats, so move it into its own place
base/statistics.cc:
test/stattest.cc:
Fix stats sorting
base/statistics.cc:
base/statistics.hh:
test/stattest.cc:
Fix description printing stuff. Add a flag to the test script to turn
descriptions on/off
base/str.hh:
wrapper to convert values to strings via stringstream
base/statistics.hh:
nitpick
base/statistics.cc:
base/statistics.hh:
test/stattest.cc:
Rework the printing of statistics to make the PrintOne function not need
to know about the stats themselves. Also remove the overloading of function
names for getting and setting parameters.
base/statistics.cc:
duh
base/statistics.cc:
Changes for _name issues
base/statistics.cc:
base/statistics.hh:
Reorganize the base Stat class a bit and clean up handling of data
base/statistics.cc:
base/statistics.hh:
Rework the stat printing stuff a bit so that the formatting parts need to know
as little as possible about the type of stat being printed.
base/statistics.hh:
maybe not all vector stats will be registered in the future. (VectorProxies)
base/statistics.hh:
test/stattest.cc:
VectorDistribution stat. To be used for per-thread distributions. Still need
to implement total and zero()
arch/alpha/isa_traits.hh:
sim/static_inst.hh:
don't use stdint.h, use either inttypes.h or host.h
sim/main.cc:
unneeded
arch/alpha/isa_desc:
only linux seems to support the rounding mode stuff right now
base/statistics.hh:
test/stattest.cc:
VectorStandardDeviation and VectorAverageDeviation
base/statistics.cc:
just make sure the size is correct
base/statistics.hh:
use pointers internally instead of references
arch/alpha/faults.cc:
base/bitfield.hh:
sim/cache/lzss_compression.hh:
sim/cache/null_compression.hh:
sim/op_class.hh:
sim/sim_time.hh:
sim/static_inst.cc:
sim/static_inst.hh:
test/stattest.cc:
consistent $Id$ tags
test/bitvectest.cc:
test/circletest.cc:
test/cprintftest.cc:
test/initest.cc:
test/lru_test.cc:
test/nmtest.cc:
test/offtest.cc:
test/paramtest.cc:
test/rangetest.cc:
test/sized_test.cc:
test/stattest.cc:
test/strnumtest.cc:
test/symtest.cc:
test/tokentest.cc:
arch/isa_parser.py:
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/arguments.cc:
arch/alpha/arguments.hh:
arch/isa_parser.py:
arch/alpha/faults.cc:
arch/alpha/faults.hh:
arch/alpha/isa_traits.hh:
arch/alpha/osfpal.cc:
arch/alpha/osfpal.hh:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
util/tap/tap.cc:
base/bitfield.hh:
base/callback.hh:
base/circlebuf.cc:
base/circlebuf.hh:
base/cprintf.cc:
base/cprintf.hh:
base/cprintf_formats.hh:
base/date.cc:
base/dbl_list.hh:
base/endian.hh:
base/fifo_buffer.cc:
base/fifo_buffer.hh:
base/hashmap.hh:
base/inet.cc:
base/inet.hh:
base/inifile.cc:
base/inifile.hh:
base/intmath.cc:
base/intmath.h:
base/misc.cc:
base/misc.hh:
base/mod_num.hh:
base/object_file.cc:
base/object_file.hh:
base/pollevent.cc:
base/pollevent.hh:
base/range.hh:
base/refcnt.hh:
base/remote_gdb.hh:
base/res_list.hh:
base/sched_list.hh:
base/socket.cc:
base/socket.hh:
base/statistics.cc:
base/statistics.hh:
base/str.cc:
base/str.hh:
base/symtab.cc:
base/symtab.hh:
base/trace.cc:
base/trace.hh:
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.cc:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/pcireg.h:
dev/simple_disk.cc:
dev/simple_disk.hh:
kern/tru64/tru64.hh:
kern/tru64/tru64_syscalls.cc:
kern/tru64/tru64_syscalls.hh:
sim/cache/null_compression.hh:
sim/async.hh:
sim/debug.cc:
sim/debug.hh:
sim/eventq.cc:
sim/eventq.hh:
sim/exetrace.cc:
sim/exetrace.hh:
sim/intr_control.cc:
sim/intr_control.hh:
sim/memtest.cc:
sim/memtest.hh:
sim/op_class.hh:
sim/param.cc:
sim/param.hh:
sim/pc_event.cc:
sim/pc_event.hh:
sim/predictor.hh:
sim/sat_counter.cc:
sim/sat_counter.hh:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_events.cc:
sim/sim_events.hh:
sim/sim_exit.hh:
sim/sim_object.cc:
sim/sim_object.hh:
sim/sim_time.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
sim/static_inst.cc:
sim/static_inst.hh:
sim/std_types.hh:
sim/system.cc:
sim/system.hh:
sim/universe.cc:
sim/exec_context.cc:
sim/exec_context.hh:
license
base/date.cc:
move
test/stattest.cc:
remove dave's scary container stuff
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/simple_cpu.cc:
rename the exec context list xc to contexts
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/fake_syscall.cc:
dev/alpha_console.cc:
sim/exec_context.hh:
sim/memtest.cc:
sim/prog.cc:
sim/prog.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
sim/system.cc:
sim/system.hh:
s/exe_ctx/xc/g
sim/base_cpu.cc:
Can't assume that context[0] exists.
sim/cache/lzss_compression.cc:
sim/cache/lzss_compression.hh:
Our compression code free and clear.
arch/alpha/fake_syscall.cc:
base/range.hh:
base/statistics.hh:
sim/param.cc:
sim/sim_object.cc:
Changes to build with g++-3.3. Mostly added a bunch of includes of
assert.h (not sure why older versions didn't need this). Also fixed
up a couple other new warnings.
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/ev5.cc:
arch/alpha/fake_syscall.cc:
arch/alpha/isa_traits.hh:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
dev/alpha_console.hh:
dev/console.cc:
dev/console.hh:
dev/disk_image.cc:
dev/etherdump.cc:
dev/simple_disk.cc:
sim/simple_cpu.cc:
sim/system.cc:
sim/system.hh:
a little style
sim/eventq.cc:
sim/main.cc:
sim/prog.cc:
sim/simple_cpu.cc:
sim/smt.hh:
smt.h -> smt.hh
add license
base/statistics.hh:
missing_math.hh isn't really needed I guess
arch/alpha/arguments.hh:
arch/alpha/fake_syscall.cc:
arch/alpha/isa_traits.hh:
base/hashmap.hh:
base/inet.cc:
base/inet.hh:
base/misc.cc:
base/pollevent.cc:
base/socket.cc:
base/statistics.hh:
base/symtab.cc:
base/symtab.hh:
base/trace.hh:
dev/alpha_console.hh:
dev/etherlink.hh:
dev/etherpkt.hh:
sim/eventq.hh:
sim/exec_context.hh:
sim/exetrace.hh:
sim/host.hh:
sim/main.cc:
sim/param.hh:
sim/serialize.hh:
sim/sim_object.cc:
sim/simple_cpu.cc:
sim/static_inst.hh:
sim/universe.cc:
test/stattest.cc:
Get rid of simplescalar host.h file and create our own host.hh file that has
less junk. (with our license.) While we're at it, we consolidate all of
the hashtable junk into one file hashmap.hh. (use this file if you need a
hash_map.)
Doxyfile:
Avoid infinite recursion on build/src link.
arch/alpha/isa_desc:
sim/static_inst.hh:
Add comments to get rid of doxygen warnings (and occasionally, as an
accidental side effect, make the code more maintainable).
Doxyfile:
Turn off information messages and route error messages to stderr.
arch/isa_parser.py:
arch/alpha/isa_desc:
sim/static_inst.hh:
- Add some comments clarifying the semantics of StaticInst flags.
- Make minor tweaks to the ISA description code to make corner cases
consistent with the above comments :-).
- Get rid of insn_counting code... instruction mix doesn't really change
through the pipeline, and the overall mix can already be derived from
existing stats. Plus it keeps changing when the ISA flags change
even though the pipeline doesn't care.
sim/hybrid_pred.cc:
sim/hybrid_pred.hh:
So said Steve Raasch:xi
"I know that the following files should be under our license"
base/fast_alloc.cc:
base/fast_alloc.hh:
David Wood said I could have my own code back :-).
sim/sim_object.cc:
sim/sim_object.hh:
create a regFormulas pass that will go AFTER the regStats pass.
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/debug.cc:
sim/eventq.cc:
sim/exec_context.hh:
sim/exetrace.cc:
sim/exetrace.hh:
sim/hybrid_pred.cc:
sim/hybrid_pred.hh:
sim/intr_control.hh:
sim/main.cc:
sim/memtest.cc:
sim/memtest.hh:
sim/op_class.hh:
sim/param.cc:
sim/param.hh:
sim/pc_event.hh:
sim/predictor.hh:
sim/prog.cc:
sim/prog.hh:
sim/sat_counter.cc:
sim/sat_counter.hh:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_object.hh:
sim/sim_time.hh:
sim/simple_cpu.hh:
sim/smt.hh:
sim/static_inst.cc:
sim/static_inst.hh:
sim/std_types.hh:
sim/system.cc:
style police
base/statistics.cc:
base/statistics.hh:
test/stattest.cc:
initial cut at a 2d vector stat
base/statistics.cc:
base/statistics.hh:
Added a std:: and removed an unused bool
arch/alpha/fake_syscall.cc:
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/prog.cc:
sim/prog.hh:
Steve Reinhardt says "I wrote these myself from scratch"
base/date.cc:
I probably changed this to a string in the first place, but it should be
a const char *
sim/main.cc:
make this compile again
base/random.cc:
base/random.hh:
sim/main.cc:
Get rid of the Simplescalar random number junk.
Since I didn't realize that we didn't even use it until after I wrote a
simple replacement, I figure I'll commit the replacement in case we ever
need it.
base/str.hh:
sim/main.cc:
quote may be more generally useful
sim/main.cc:
sim/sim_object.cc:
sim/sim_object.hh:
Make the old stats package a bit more self contained to prepare for
future extrication
sim/main.cc:
sim/sim_time.cc:
sim/sim_time.hh:
consolidate all of the time handling stuff
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/main.cc:
sim/smt.hh:
instead of initializing max_threads_per_cpu in main(), we turn it into
a static function and initialize it upon the first call
Users of this should beware that all CPUs must be built before this function
can be used.
sim/main.cc:
sim/universe.cc:
sim_running_systems makes more sense in universe.cc
sim/main.cc:
this is not a simplescalar file, use our copyright
say that the simulator is M5 and display our copyright
cleanup
change a few things here and there to use our style
use endl instead of "\n" (for future portablility)
sim/async.hh:
sim/main.cc:
sim/system.cc:
sim/system.hh:
sim/universe.cc:
- Clean up a few simplescalar comments from main.cc that Nate missed.
- Add some comments and some doxygen documentation.
- Move sim_running_systems to static System::numSystemsRunning.
arch/alpha/ev5.cc:
Update num_running_systems to System::numSystemsRunning for full-sys too.
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/smt.hh:
instead of polling all CPUs to find out the max number of threads across
all CPUs, just have the CPUs themselves update the variable as they are
created.
arch/alpha/isa_desc:
First pass at fixing cvtst... not tested.
arch/alpha/ev5.cc:
base/statistics.cc:
base/statistics.hh:
arch/alpha/isa_desc:
Just use the TYPEFUNC not FULLFUNC
arch/alpha/ev5.cc:
base/statistics.cc:
base/statistics.hh:
committing from the wrong directory is a bad thing
arch/alpha/isa_desc:
I hope a final solution for the cmptxx issue.
base/statistics.cc:
All printable stats must first be initialized, so throw an assertion if they
are not. This ought to help in debugging a bit.
base/statistics.cc:
base/statistics.hh:
Two new flags: nozero, and nonan. This will supress printing stats if they
are zero or NAN. For example, it will cause vector elements to be skipped
if there is no value, or it will cause distribution buckets to be skipped.
(or an entire scalar stat to be skipped.) This can be used in conjunction
with prereq. The difference with prereq, is that prereq just checks if the
other stat has ANY values, and won't selectively ignore individual vector
elements.
base/statistics.hh:
this does not belong here
arch/alpha/isa_desc:
Just happened to notice small insidious bug in itofs.
arch/isa_parser.py:
New isa description language feature: multiple constants can be
provided for a decode statement, e.g.:
decode OP {
0, 1: foo();
2, 3: bar();
}
Documentation update included at no extra charge.
sim/param.hh:
this can be const
sim/exec_context.cc:
be more terse
arch/alpha/isa_desc:
Revamp decoding of IEEE FP instructions (opcode 0x16). I think we've
got all the bases covered now.
Also implemented cvtql/v & cvtql/sv (actually the same instruction
from M5's perspective).
arch/isa_parser.py:
- If isa_desc defines the global Python variable rcs_id, echo it
into the output decoder.cc.
- Only print last three components of ISA description path name in output.
- Add RCS id string to this file.
arch/alpha/isa_desc:
Add RCS id string.
arch/isa_parser.py:
Get it right.
arch/isa_parser.py:
Oone more little glitch...
kern/tru64/tru64_syscalls.cc:
kern/tru64/tru64_syscalls.hh:
add support for mach syscalls.
base/trace.cc:
base/trace.hh:
Some reorganization and cleanup.
Add the ability to ignore trace output from certain sources. The option is
--trace:ignore. It takes a space separated list of SimObjects to ignore.
The SimObject is listed in the normal dotted herarchy notation. (e.g.
system0.cpu0.DL1) If an object is specified, the *all* child objects are
ignored as well. You can use a wildcard (*) to match any object.
To ignore all trace statements from system1:
--trace:ignore"system1"
To ignore all DL1 statements:
--trace:ignore="*.*.DL1"
sim/main.cc:
Try the HOST varilable if HOSTNAME isn't found
sim/exetrace.cc:
sim/exetrace.hh:
Minor tweeks to instruction execution tracing:
- add a correct-path sequence number to all instructions
- add colon characters to help delimit the instruction disassembly
arch/alpha/ev5.cc:
Move all of the kernel statistics into the .cc file while I am still messing
around with them.
Add support for tracking context switches, and mode switches.
More detailed tracking of ipl changes.
Don't display zeroes for stats such as syscalls, ipls, faults, since zeroes
are very common and there are a ton of stats.
base/hashmap.hh:
don't forget about the hash_multimap
oh, and string is used in here
base/str.cc:
convert strings that represent bool values to a bool
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/ev5.cc:
rework the tlb lookup code so that it uses a map instead of a linear
search.
base/statistics.cc:
a tiny bit of debugging assistance
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
sim/exec_context.hh:
No need for these functions to be virtual. Given that, they don't need to
have the same interface. This eliminates a useless check in an expensive
function.
arch/alpha/isa_desc:
This is an quick fix for the SimpleSclar-FP-Ops-Don't-Work-Right bug
The SS_COMPATIBLE_FP #define at the top of the file forces the precision to match SS.
This will change the precision for ALL CPU's.
Nate will be making a change shortly so that this not done for Full System
arch/alpha/alpha_memory.cc:
use i-> instead of (*i). (what was I thinking?)
also try to do i-> only once if it can be helped.
base/remote_gdb.cc:
sim/simple_cpu.cc:
Move remote debugger code to where it belongs
clean it up a tad while we're at it.
arch/alpha/isa_desc:
Changes for the SS FP bug:
SS-style FP done only if SS_COMPATIBLE_FP is defined in the makefile
arch/alpha/isa_traits.hh:
sim/memtest.cc:
sim/memtest.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
sim/cache/lzss_compression.cc:
sim/cache/lzss_compression.hh:
The new memory hierarchy. There is still some more changes to come, but this works now. IIC compression is broken, but no one else cares. DMA coherence might be broken (no way to test atm). There are doxygen warnings that I will clear up when I can stay connected for more than 3 minutes.
Doxyfile:
Turn Graphics back on since we have squashed the warnings.
base/misc.hh:
Add #include <assert.h> for those who use m5_assert() macro.
Somehow g++ 3.3 is pickier about this than 3.2.
sim/exetrace.hh:
sim/simple_cpu.cc:
sim/std_types.hh:
Style fixes... mostly changing 'struct foo_bar' to 'FooBar' for some
older parts of the code.
Doxyfile:
Always have a detailed section.
sim/host.hh:
Get rid of an old simplescalar comment (plus improve some other comments).
base/statistics.cc:
base/statistics.hh:
provide a way to get at the subdesc
base/statistics.hh:
Make it possible to counte a sample more than once
base/statistics.cc:
print the right value
base/statistics.cc:
base/statistics.hh:
A bit of debugging support
base/statistics.cc:
base/statistics.hh:
be more consistent
base/statistics.hh:
use the correct axis
base/statistics.hh:
remove dead code
sim/main.cc:
sim/param.cc:
sim/param.hh:
sim/sim_object.cc:
Stats now sent by default to a file called "m5.stats". Get the old
behavior back by saying "--stats:file=cerr" on cmd line.
Parameters and config-file stuff also sent to stats file where they belong.
A few informational messages are sent to both cerr and to the stats file.
Default output is pretty minimal now.
arch/alpha/faults.cc:
base/bitfield.hh:
base/random.cc:
base/random.hh:
sim/static_inst.cc:
test/stattest.cc:
Fix RCS Id strings.
sim/base_cpu.hh:
sim/main.cc:
Check if user forgot to specify any CPUs and print a meaningful
error message (not just "improperly exited event loop!").
base/statistics.cc:
base/statistics.hh:
Make subsequent calls to flags() add more flags instead of change them.
Also add the concept of a reserved flag that the user is not allowed to
set. (Basically for passing around extra parameters in the stats package.)
sim/debug.cc:
sim/param.cc:
sim/param.hh:
sim/prog.cc:
sim/sim_events.cc:
Check that VectorParam objects are valid before we let them be
referenced. Fix up a few places where we were just referencing them
w/o checking.
Also some const cleanup on Param object methods.
sim/sim_object.cc:
sim/sim_object.hh:
Print SimObject class name when complaining about missing/broekn params.
base/inifile.cc:
Add "-undef" to cpp flags to not define system-specific macros.
(A '#define linux 1' was giving me trouble.)
base/statistics.hh:
add support fo subnaming in the y direction for 2d vectors. make the printing of it pretty and compatible with the old style. also, suppress printing of a total for 2d vector if they x dimension is just 1.
base/statistics.cc:
rework a lot of the stuff between #ifdef STAT_DISPLAY_COMPAT so it's neater and
also more accurate. add support for printing subdescriptions.
LICENSE:
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/arguments.cc:
arch/alpha/arguments.hh:
arch/alpha/fake_syscall.cc:
arch/alpha/faults.cc:
arch/alpha/faults.hh:
arch/alpha/isa_traits.hh:
arch/alpha/osfpal.cc:
arch/alpha/osfpal.hh:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
base/bitfield.hh:
base/callback.hh:
base/circlebuf.cc:
base/circlebuf.hh:
base/cprintf.cc:
base/cprintf.hh:
base/cprintf_formats.hh:
base/date.cc:
base/dbl_list.hh:
base/endian.hh:
base/fast_alloc.cc:
base/fast_alloc.hh:
base/fifo_buffer.cc:
base/fifo_buffer.hh:
base/hashmap.hh:
base/inet.cc:
base/inet.hh:
base/inifile.cc:
base/inifile.hh:
base/intmath.cc:
base/misc.cc:
base/misc.hh:
base/mod_num.hh:
base/object_file.cc:
base/object_file.hh:
base/pollevent.cc:
base/pollevent.hh:
base/random.cc:
base/random.hh:
base/range.hh:
base/refcnt.hh:
base/remote_gdb.hh:
base/res_list.hh:
base/sched_list.hh:
base/socket.cc:
base/socket.hh:
base/statistics.cc:
base/statistics.hh:
base/str.cc:
base/str.hh:
base/symtab.cc:
base/symtab.hh:
base/trace.cc:
base/trace.hh:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.cc:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/simple_disk.cc:
dev/simple_disk.hh:
kern/tru64/tru64.hh:
kern/tru64/tru64_syscalls.cc:
kern/tru64/tru64_syscalls.hh:
sim/async.hh:
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/debug.cc:
sim/debug.hh:
sim/eventq.cc:
sim/eventq.hh:
sim/exec_context.cc:
sim/exec_context.hh:
sim/exetrace.cc:
sim/exetrace.hh:
sim/host.hh:
sim/hybrid_pred.cc:
sim/hybrid_pred.hh:
sim/intr_control.cc:
sim/intr_control.hh:
sim/main.cc:
sim/memtest.cc:
sim/memtest.hh:
sim/op_class.hh:
sim/param.cc:
sim/param.hh:
sim/pc_event.cc:
sim/pc_event.hh:
sim/predictor.hh:
sim/prog.cc:
sim/prog.hh:
sim/sat_counter.cc:
sim/sat_counter.hh:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_events.cc:
sim/sim_events.hh:
sim/sim_exit.hh:
sim/sim_object.cc:
sim/sim_object.hh:
sim/cache/lzss_compression.cc:
sim/cache/lzss_compression.hh:
sim/cache/null_compression.hh:
sim/sim_time.cc:
sim/sim_time.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
sim/smt.hh:
sim/static_inst.cc:
sim/static_inst.hh:
sim/std_types.hh:
sim/system.cc:
sim/system.hh:
sim/universe.cc:
test/bitvectest.cc:
test/circletest.cc:
test/cprintftest.cc:
test/initest.cc:
test/lru_test.cc:
test/nmtest.cc:
test/offtest.cc:
test/paramtest.cc:
test/rangetest.cc:
test/sized_test.cc:
test/stattest.cc:
test/strnumtest.cc:
test/symtest.cc:
test/tokentest.cc:
util/tap/tap.cc:
arch/isa_parser.py:
Add attribution to license.
sim/cache/lzss_compression.cc:
sim/cache/lzss_compression.hh:
Extend the compression algorithm to handle upto 4096 byte blocks. Improve compression of single bytes that can be sign extended.
sim/cache/lzss_compression.hh:
Remove some todos that I've already done.
sim/hybrid_pred.cc:
sim/hybrid_pred.hh:
sim/memtest.cc:
sim/prog.cc:
sim/sat_counter.cc:
sim/memtest.hh:
sim/predictor.hh:
sim/prog.hh:
sim/sat_counter.hh:
the new stats package. voila. the move to bitkeeper can go on, figuring what's happening can happen later.
base/trace.cc:
test/Makefile:
test/cprintftest.cc:
test/tracetest.cc:
separate the context stuff for tracing from the actual tracing facility to
make it easier to test.
Add a test for tracing
--HG--
extra : convert_revision : 28dd3568b0714296345f8a5cba282f0b937ce725
|
