| Age | Commit message (Expand) | Author |
|---|
| 2006-03-03 | Changes to support automatic renaming of the shadow registers at decode time.... | Kevin Lim |
| 2006-02-27 | Changes to put all the misc regs within the misc reg file. This includes the... | Kevin Lim |
| 2006-02-23 | Enable building only selected CPU models via new scons | Steve Reinhardt |
| 2006-02-23 | Create a Builder object for .isa files in arch/SConscript. | Steve Reinhardt |
| 2006-02-19 | Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5 | Gabe Black |
| 2006-02-19 | Merge gblack@m5.eecs.umich.edu:/bk/multiarch | Gabe Black |
| 2006-02-19 | Changes to untemplate StaticInst and StaticInstPtr, change the isa to a names... | Gabe Black |
| 2006-02-18 | Support NNPC and branch instructions ... Outputs to decoder.cc correctly | Korey Sewell |
| 2006-02-16 | Fixes to handle generating the initiateAcc and completeAcc functions a little... | Kevin Lim |
| 2006-02-15 | Gives separate methods for initiating and completing a memory access, which w... | Kevin Lim |
| 2006-02-12 | Polishing of isa_parser.py internal operand handling, resulting in | Steve Reinhardt |
| 2006-02-11 | Minor cleanup of operand type and traits code in isa_parser.py. | Steve Reinhardt |
| 2006-02-11 | Add keyword parameters and list-valued arguments to | Steve Reinhardt |
| 2006-02-10 | Change how memory operands are handled in ISA descriptions. | Steve Reinhardt |
| 2006-02-09 | Minor cleanup of include-handling code in isa_parser.py. | Steve Reinhardt |
| 2006-02-09 | Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5 | Steve Reinhardt |
| 2006-02-09 | Change how isa_parser.py generates C++ names for isa_desc operands. | Steve Reinhardt |
| 2006-01-24 | Some stuff aparently didn't get committed which was from before the new repos... | Gabe Black |
| 2005-10-20 | Minor tweak to isa_parser. | Steve Reinhardt |
| 2005-09-11 | Explicitly handle rounding on FP-to-integer conversions. | Steve Reinhardt |
| 2005-06-05 | Fix a few broken or inconsistently formatted copyrights | Steve Reinhardt |
| 2005-06-05 | Many files: | Steve Reinhardt |
| 2005-06-04 | shuffle files around for new directory structure | Nathan Binkert |
| 2005-06-04 | Remove the inorder CPU | Nathan Binkert |
| 2005-05-03 | Large update of several parts of my code. The most notable change is the inc... | Kevin Lim |
| 2005-02-25 | Initial light-weight OoO CPU checkin, along with gcc-3.4 fixes. | Kevin Lim |
| 2005-02-04 | Hand merge | Kevin Lim |
| 2005-02-03 | Add support for CPU models to execute the effective | Steve Reinhardt |
| 2005-01-11 | Merge changes. | Kevin Lim |
| 2004-11-03 | Add Inorder CPU model | Taeho Kgil |
| 2004-09-23 | Update to make multiple instruction issue and different latencies work. | Kevin Lim |
| 2004-08-20 | Check in of new CPU. This checkin works under non-Fullsystem mode, with no c... | Kevin Lim |
| 2004-05-31 | Renamed OpClass enum members: they all end in 'Op' now. | Steve Reinhardt |
| 2004-05-28 | Updated FastCPU model with all the recent changes. | Kevin Lim |
| 2004-05-18 | Add a level of indirection to the register accessors used in | Steve Reinhardt |
| 2004-05-17 | Significant changes to ISA description to completely factor | Steve Reinhardt |
| 2004-05-10 | Do a better job of factoring out CPU model in ISA description. | Steve Reinhardt |
| 2003-10-13 | Fix up decoder.cc generation... this got broken at the directory reorg. | Steve Reinhardt |
| 2003-10-07 | Fix attribution for decoder.cc. | Steve Reinhardt |
| 2003-10-07 | isa_parser.py: | Nathan Binkert |
| 2003-10-07 | Import changeset | Steve Raasch |
