| Age | Commit message (Collapse) | Author |
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MIPS option except isa_traits.*
which I need to update the misc. regfile accesses
arch/mips/faults.cc:
arch/mips/faults.hh:
alpha to mips
arch/mips/isa/base.isa:
add includes
arch/mips/isa/bitfields.isa:
more bitfields
arch/mips/isa/decoder.isa:
lots o' lots o' lots o' changes!!!!
arch/mips/isa/formats.isa:
include cop0.isa
arch/mips/isa/formats/basic.isa:
fix faults
arch/mips/isa/formats/branch.isa:
arch/mips/isa/formats/fp.isa:
arch/mips/isa/formats/int.isa:
arch/mips/isa/formats/mem.isa:
arch/mips/isa/formats/noop.isa:
arch/mips/isa/formats/trap.isa:
arch/mips/isa/formats/unimp.isa:
arch/mips/isa/formats/unknown.isa:
arch/mips/isa/formats/util.isa:
arch/mips/isa/operands.isa:
arch/mips/isa_traits.cc:
arch/mips/linux_process.cc:
merge MIPS-specific comilable/buidable files code into multiarch
arch/mips/isa_traits.hh:
merge MIPS-specific comilable/buidable files code into multiarch... the miscRegs file accesses i have
need to be recoded and everything should build then ...
arch/mips/stacktrace.hh:
file copied over
--HG--
extra : convert_revision : 4a72e14fc5fb0a0d1f8b205dadbbf69636b7fb1f
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arch/mips/faults.hh:
remove nonsense
arch/mips/isa/base.isa:
define R31
arch/mips/isa/bitfields.isa:
forgotten bitfields
arch/mips/isa/decoder.isa:
INT64 -> int64_t
arch/mips/isa/formats.isa:
fix comments
arch/mips/isa/formats/branch.isa:
Branch -> BranchLikely
RB -> RT
arch/mips/isa/formats/fp.isa:
Make FP ops generates
arch/mips/isa/formats/mem.isa:
RA,RB -> RS,RT
arch/mips/isa/formats/noop.isa:
Rc -> Rd
arch/mips/isa/formats/util.isa:
forgot brace and semicolon
arch/mips/isa/includes.isa:
remove unnecessary files
arch/mips/isa_traits.hh:
spacing
cpu/static_inst.hh:
add cond_delay_slot flag
--HG--
extra : convert_revision : 3bc7353b437f9a764e85cc462bed86c9d654eb37
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SConscript:
changed the alpha_memory.hh to memory.hh in SConscript
arch/isa_parser.py:
temporarily comment out o3 model
arch/mips/isa/base.isa:
arch/mips/isa_traits.cc:
arch/mips/isa_traits.hh:
Fix Up Base Class to mirror how Alpha generates StaticInsts
arch/mips/faults.cc:
MIPS fault.cc file
arch/mips/faults.hh:
MIPS fault.hh file
--HG--
rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux_process.cc
rename : arch/alpha/alpha_linux_process.hh => arch/alpha/linux_process.hh
rename : arch/alpha/alpha_memory.cc => arch/alpha/memory.cc
rename : arch/alpha/alpha_memory.hh => arch/alpha/memory.hh
rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64_process.cc
rename : arch/alpha/alpha_tru64_process.hh => arch/alpha/tru64_process.hh
extra : convert_revision : f92d6e765ca96a8b952aef79ed119fa29464563b
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--HG--
extra : convert_revision : c019fad60fbf1a316bc6201b8ce8acf5a9875989
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Edits to the CPU model may still need to be made to handle branch likely insts...
arch/isa_parser.py:
add a NNPC operand ...
arch/mips/isa/base.isa:
change SPARC to MIPS
arch/mips/isa/decoder.isa:
typo < to >=
arch/mips/isa/formats/basic.isa:
spacing
arch/mips/isa/formats/branch.isa:
add code for branch instructions (still need adjustments for the branch likely)
arch/mips/isa/operands.isa:
support for NNPC and R31
arch/mips/isa_traits.hh:
NNPC Addr variable
--HG--
extra : convert_revision : df03d2a71c36dbc00270c2e3d7882b4f09ed97ad
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arch/mips/isa/base.isa:
restoring base.isa file ...
arch/mips/isa/formats/basic.isa:
add c++ emacs header
arch/mips/isa/formats/branch.isa:
added branch likely format
arch/mips/isa/formats/int.isa:
small change to python code
--HG--
extra : convert_revision : defd592abb1a724f5f88b19c197b858420e92d17
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arch/mips/isa/base.isa:
restore base.isa
--HG--
extra : convert_revision : a551caae28f505b22bceae3297fc00b0fb6a0e23
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