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2006-03-28Make .isa-file ##include file paths relative to including file.Steve Reinhardt
Makes .isa files cleaner and simplifies scanner too. Simplified scanner to work under both old and new versions of scons. arch/SConscript: Simplify .isa scanner... seems to work with both scons 0.96.1 and 0.96.91 now. Assumes .isa ##include paths are relative to including file. arch/alpha/isa/main.isa: arch/mips/isa/formats/formats.isa: arch/mips/isa/main.isa: arch/sparc/isa/formats.isa: arch/sparc/isa/main.isa: Make ##include paths relative to including file. arch/isa_parser.py: Make ##include file paths relative to including file. Makes .isa files cleaner and simplifies scanner too. Partial rewrite of include-handling code to use cool re.sub() feature where you can specify a function to provide the replacement string. Minor cleanup of error-handling code. Also got rid of '#!' at top to make caller choose which python interpreter is used (since SPARC now requires 2.4 to build, we may need to do that via scons in the future). --HG-- rename : arch/mips/isa/formats.isa => arch/mips/isa/formats/formats.isa extra : convert_revision : 15a3920fa3aaf80cd94083eda853aa4e49425045
2006-03-19support for unaligned memory accessKorey Sewell
arch/mips/isa/base.isa: disassembly fixes arch/mips/isa/decoder.isa: support for unaligned loads/stores arch/mips/isa_traits.hh: edit Syscall Reg values arch/mips/linux_process.cc: call writevFunc on writev syscall --HG-- extra : convert_revision : 4aea6d069bd7ba0e83b23d2d85c50d68532f0454
2006-03-18steps toward making syscalls workKorey Sewell
arch/mips/isa/decoder.isa: arch/mips/isa_traits.hh: sim/syscall_emul.cc: make syscall instruction functional arch/mips/linux_process.cc: add all MIPS/Linux syscalls to descriptor list --HG-- extra : convert_revision : 5455a345e76be921e9f63b248aef874b6358e465
2006-03-16Found and fixed 3 decoder.isa bugs!!! Now the hello_world program runs for a ↵Korey Sewell
while before getting in a infinite loop. It actually "tries" to syscall too, but syscalls aren't implemented just yet arch/mips/faults.cc: more descriptive names for faults (will help future users as well as me!) arch/mips/isa/base.isa: make sure we are printing out "BasicOp" format disassembly instructions as dest,src,src instead of src,src,dest arch/mips/isa/decoder.isa: FIX LW/SW Bug!!!! I was actually loading a byte instead of a word FIX JALR Bug!!!! I was not saving the link address in R31 for this instruction FIX SLL/NOP Bug!!! We now recognize the varying flavors of sll,nop,ehb,& ssnop correctly base/loader/elf_object.cc: change back to original way base/loader/elf_object.hh: change back to original! --HG-- extra : convert_revision : 39b65fba31c1842ac6966346fe8a35816a4231fa
2006-03-15infinitesimal small baby steps toward MIPS actually workingKorey Sewell
arch/mips/isa/formats/branch.isa: let user know that we alter r31 in disassembly arch/mips/isa_traits.cc: add copyRegs function ... comment out serialize float code for now arch/mips/isa_traits.hh: make FloatRegFile a class ... change values of architectural regs arch/mips/process.cc: change MIPS to Mips base/loader/elf_object.cc: get global pointer initialized to a value base/loader/elf_object.hh: Add global_ptr to elf_object constructor base/loader/object_file.hh: MIPS to Mips base/traceflags.py: SimpleCPU trace flag cpu/simple/cpu.cc: DPRINTF flags for SimpleCPU cpu/static_inst.hh: Add Decoder functions to static_inst.hh --HG-- extra : convert_revision : 0544a8524d3fe4229428cb06822f7da208c72459
2006-03-14Minor Sconscript edit ... mips decoder changes ... initialize NNPC and ↵Korey Sewell
output fault name in simple cpu SConscript: Separate Alpha EIO from syscall building for other architectures arch/isa_specific.hh: change MIPS constant to 34k arch/mips/isa/decoder.isa: Allow sll,ssnop,nop, and ehb to be determined through decoder using the different types of default cases arch/mips/isa/formats/branch.isa: Delete debug code arch/mips/isa/formats/noop.isa: add a Nop format arch/mips/isa_traits.hh: use constants instead of enums arch/mips/process.cc: point to the correct header file cpu/simple/cpu.cc: Output the actual fault name sim/process.cc: Inititalize NNPC --HG-- extra : convert_revision : adb0026dfad25b14c98fb03c98bfe9c681bba6f8
2006-03-12MIPS is back to compiling and building now!Korey Sewell
arch/alpha/isa_traits.hh: used for SimpleCPU instead of explicitly calling the namespace we declare in isa_traits.hhs so other archs. can use SimpleCPU arch/mips/SConscript: dont include common_syscall or tru64 arch/mips/faults.cc: arch/mips/faults.hh: arch/mips/isa/formats/unimp.isa: arch/mips/isa/formats/unknown.isa: Change Faults to new format arch/mips/isa/decoder.isa: Fix readMiscReg access Made change so that you cant explicitly tell if a instruction nop,ehb,or ssnop... These are all variants of the sll instruction so I may need to make a separte class of instructions to handle thse better arch/mips/isa/includes.isa: add isa_traits.hh and MipsISA included into every auto-gen file arch/mips/isa_traits.cc: create copyMiscRegs function... delete useless code arch/mips/isa_traits.hh: clean up for build arch/mips/linux_process.cc: mem is now getMemPort(), linux process objects now take in a system argument arch/mips/linux_process.hh: new argument for linux process arch/mips/process.cc: add system arch/mips/process.hh: add system variable cpu/cpu_exec_context.cc: Change AlphaISA to TheISA cpu/exec_context.hh: add readNextNPC and setNextNPC functions cpu/simple/cpu.cc: include isa_traits for namespace declariation cpu/simple/cpu.hh: PC & NPC access/modify functions arch/mips/utility.hh: file needed for compile --HG-- extra : convert_revision : 29a327e79c51c6174a6e526aa68c7aab7e7eb535
2006-03-09minor comments to decoder.isaKorey Sewell
arch/mips/isa/decoder.isa: comments --HG-- extra : convert_revision : 8e4fdf36d7f7365cda062bc169a313bf860a4fe5
2006-03-08add explicit support for nop,ssnop, and ehb instructionsKorey Sewell
--HG-- extra : convert_revision : 41151d38cabb6ce0ea81e5d78e4474d8f2ffeb67
2006-03-08Update MiscReg enum and miscRegFile definitionKorey Sewell
update miscReg file access arch/mips/isa/decoder.isa: arch/mips/isa_traits.cc: update miscRegfile access arch/mips/isa_traits.hh: Update MiscReg enum and miscRegFile definition --HG-- extra : convert_revision : 9b6b9343d674e1e38e25bb9a4ffe4325142e7424
2006-03-08updated MIPS ISA files .... all files should be able to compile/build with ↵Korey Sewell
MIPS option except isa_traits.* which I need to update the misc. regfile accesses arch/mips/faults.cc: arch/mips/faults.hh: alpha to mips arch/mips/isa/base.isa: add includes arch/mips/isa/bitfields.isa: more bitfields arch/mips/isa/decoder.isa: lots o' lots o' lots o' changes!!!! arch/mips/isa/formats.isa: include cop0.isa arch/mips/isa/formats/basic.isa: fix faults arch/mips/isa/formats/branch.isa: arch/mips/isa/formats/fp.isa: arch/mips/isa/formats/int.isa: arch/mips/isa/formats/mem.isa: arch/mips/isa/formats/noop.isa: arch/mips/isa/formats/trap.isa: arch/mips/isa/formats/unimp.isa: arch/mips/isa/formats/unknown.isa: arch/mips/isa/formats/util.isa: arch/mips/isa/operands.isa: arch/mips/isa_traits.cc: arch/mips/linux_process.cc: merge MIPS-specific comilable/buidable files code into multiarch arch/mips/isa_traits.hh: merge MIPS-specific comilable/buidable files code into multiarch... the miscRegs file accesses i have need to be recoded and everything should build then ... arch/mips/stacktrace.hh: file copied over --HG-- extra : convert_revision : 4a72e14fc5fb0a0d1f8b205dadbbf69636b7fb1f
2006-02-22MIPS Compiles scons/MIPS_SE/arch/mips/decoder.do!!!!!!Korey Sewell
arch/mips/faults.hh: remove nonsense arch/mips/isa/base.isa: define R31 arch/mips/isa/bitfields.isa: forgotten bitfields arch/mips/isa/decoder.isa: INT64 -> int64_t arch/mips/isa/formats.isa: fix comments arch/mips/isa/formats/branch.isa: Branch -> BranchLikely RB -> RT arch/mips/isa/formats/fp.isa: Make FP ops generates arch/mips/isa/formats/mem.isa: RA,RB -> RS,RT arch/mips/isa/formats/noop.isa: Rc -> Rd arch/mips/isa/formats/util.isa: forgot brace and semicolon arch/mips/isa/includes.isa: remove unnecessary files arch/mips/isa_traits.hh: spacing cpu/static_inst.hh: add cond_delay_slot flag --HG-- extra : convert_revision : 3bc7353b437f9a764e85cc462bed86c9d654eb37
2006-02-21Merge zizzer:/bk/multiarchKorey Sewell
into zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/multiarch --HG-- rename : arch/alpha/alpha_memory.cc => arch/alpha/memory.cc rename : arch/alpha/alpha_memory.hh => arch/alpha/memory.hh extra : convert_revision : c641ba3c1009829b7276279b2dca441be1da5b30
2006-02-21Renaming alpha files and changing some MIPS stuff to be more like Alpha versionKorey Sewell
SConscript: changed the alpha_memory.hh to memory.hh in SConscript arch/isa_parser.py: temporarily comment out o3 model arch/mips/isa/base.isa: arch/mips/isa_traits.cc: arch/mips/isa_traits.hh: Fix Up Base Class to mirror how Alpha generates StaticInsts arch/mips/faults.cc: MIPS fault.cc file arch/mips/faults.hh: MIPS fault.hh file --HG-- rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux_process.cc rename : arch/alpha/alpha_linux_process.hh => arch/alpha/linux_process.hh rename : arch/alpha/alpha_memory.cc => arch/alpha/memory.cc rename : arch/alpha/alpha_memory.hh => arch/alpha/memory.hh rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64_process.cc rename : arch/alpha/alpha_tru64_process.hh => arch/alpha/tru64_process.hh extra : convert_revision : f92d6e765ca96a8b952aef79ed119fa29464563b
2006-02-21Changed Fault * to Fault, which is a typedef to FaultBase *, which is the ↵Gabe Black
old Fault class renamed. --HG-- extra : convert_revision : 5b2f457401f8ff94fe39fe071288eb117814b7bb
2006-02-20make MIPS specificKorey Sewell
--HG-- extra : convert_revision : c019fad60fbf1a316bc6201b8ce8acf5a9875989
2006-02-20load/store instruction format ... now generates load/store codeKorey Sewell
and breaks it into a separate EA and MemAccess templated from how the Alpha ARch. was coded to do the same thing. arch/mips/isa/bitfields.isa: comment change arch/mips/isa/decoder.isa: re-structuring of load/store instruction definitions arch/mips/isa/formats/mem.isa: Define LoadMemory & Store Memory formats Use style of formatting & base class similar to what was used for ALPHA arch/mips/isa/formats/util.isa: Insert LoadStoreBase function here from alpha/arch/isa/mem.isa arch/mips/isa/operands.isa: change shw->sh and uhw->uh --HG-- extra : convert_revision : 5d85f15f4a600dd4c473a3b4a170ba39cf07fc8a
2006-02-20Support for All Jump Instructions ...Korey Sewell
Redo format for Branches and Jumps ( Must update NNPC not NPC ) Now all branches and jumps look like they auto-generate correctly from isa_parser.py!!! arch/mips/isa/decoder.isa: Support for All Jump Instructions .. arch/mips/isa/formats/branch.isa: Redo format for Branches and Jumps ( Must update NNPC not NPC ) arch/mips/isa/formats/util.isa: define clear_exe_inst_hazards for later use --HG-- extra : convert_revision : 63618ed12ee6ed94c47d29619cc1cab2cbaf5cda
2006-02-18Support NNPC and branch instructions ... Outputs to decoder.cc correctlyKorey Sewell
Edits to the CPU model may still need to be made to handle branch likely insts... arch/isa_parser.py: add a NNPC operand ... arch/mips/isa/base.isa: change SPARC to MIPS arch/mips/isa/decoder.isa: typo < to >= arch/mips/isa/formats/basic.isa: spacing arch/mips/isa/formats/branch.isa: add code for branch instructions (still need adjustments for the branch likely) arch/mips/isa/operands.isa: support for NNPC and R31 arch/mips/isa_traits.hh: NNPC Addr variable --HG-- extra : convert_revision : df03d2a71c36dbc00270c2e3d7882b4f09ed97ad
2006-02-18changes from mergedmemKorey Sewell
arch/mips/isa/formats/branch.isa: add branch_likely member functions cpu/base.hh: cpu/exec_context.hh: cpu/static_inst.hh: change from mergedmem --HG-- extra : convert_revision : d6ad6943e2ef09eac91a466fc5c9bd8e66bf319a
2006-02-18use string name to figure out if we have a "AndLink" instructionKorey Sewell
arch/mips/isa/operands.isa: uq -> uw --HG-- extra : convert_revision : eeac6dba813de8174d080a5fa9b5a396b345113a
2006-02-18MIPS generates ISA code through scons '.../decoder.cc'!!!Korey Sewell
Now, must create g++ compilable code ... arch/mips/isa/decoder.isa: missing a '}' ... edited a few instruction decodings ... arch/mips/isa/formats.isa: rearranged #include arch/mips/isa/formats/branch.isa: add Branch Likely and Unconditional format arch/mips/isa/formats/int.isa: move OperateNopCheckDecode template to another file ... arch/mips/isa/formats/noop.isa: change Alpha to Mips in noop.isa --HG-- extra : convert_revision : 4bf955fa6dffbbc99fb95fee7878f691e3df5424
2006-02-16Get ISA parser to at least include all the ISA correctly ... crashes with ↵Korey Sewell
"None" error arch/mips/isa/decoder.isa: CondBranch format split up into Branch & BranchLikely formats arch/mips/isa/formats.isa: include util.isa arch/mips/isa/formats/branch.isa: erroneous 'e' at top of code arch/mips/isa/formats/util.isa: util.isa --HG-- extra : convert_revision : 4fc44a05e2838749e66cd70f210e8a718b34cbf3
2006-02-16file name changes ... minor ISA changesKorey Sewell
arch/mips/isa/base.isa: restoring base.isa file ... arch/mips/isa/formats/basic.isa: add c++ emacs header arch/mips/isa/formats/branch.isa: added branch likely format arch/mips/isa/formats/int.isa: small change to python code --HG-- extra : convert_revision : defd592abb1a724f5f88b19c197b858420e92d17
2006-02-15...Korey Sewell
arch/mips/isa/base.isa: restore base.isa --HG-- extra : convert_revision : a551caae28f505b22bceae3297fc00b0fb6a0e23
2006-02-14another big step to a parsable ISA ... no errors after I used a symbolic ↵Korey Sewell
link for arch/alpha/main.isa to test my files ... arch/mips/isa/operands.isa: use sd and ud instead of sdw and udw --HG-- extra : convert_revision : d66f3fd2c4a4d70e6015f0f1643c400cdfe73055
2006-02-14trying to get ISA to parse correctly ...Korey Sewell
arch/mips/isa/formats/unimp.isa: holds unimplemented formats arch/mips/isa/formats/unknown.isa: holds unknown formats --HG-- extra : convert_revision : 0f3a8ea7e3a1592322cce54527d6989152e57975
2006-02-14Merge zizzer:/bk/multiarchKorey Sewell
into zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/m5-multiarch --HG-- extra : convert_revision : 62d9346c44d5b7d455414fbebf0da3a8ef8d0754
2006-02-14make MIPS MT instructions decodable ...Korey Sewell
arch/mips/isa/bitfields.isa: extra bitfield for decoding --HG-- extra : convert_revision : 27f0afc3ee6ce00a94f44b2b1ac160ec26030866
2006-02-12Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5Gabe Black
into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch --HG-- extra : convert_revision : 427b5c957f91e66271444acebc01e1a861790363
2006-02-12Polishing of isa_parser.py internal operand handling, resulting inSteve Reinhardt
minor change to syntax of 'def operands' in ISA descriptions. arch/alpha/isa/main.isa: arch/mips/isa/operands.isa: arch/sparc/isa/operands.isa: Change 'def operands' statement to work with new isa_parser changes. arch/isa_parser.py: Merge OperandTraits and OperandDescriptor objects into a unified hierarchy of Operand objects. Required a change in the syntax of the 'def operands' statement in the ISA description. --HG-- extra : convert_revision : cb43f1607311497ead88ba13953d410ab5bc6a37
2006-02-10The first fully coded version of decoder.isa!!!!!Korey Sewell
================================================= -every MIPS32 ISA is represented with some type of code block. -any instruction that doesnt have a code block would be of format WarnUnimpl. Examples of the ones I am waiting on further info to implement are the TLB register insts, memory consistency instructions (ll,sc,etc.) and software debug insts. --HG-- extra : convert_revision : 4a26c72e4fa1f63b8689fe2631a7508daf660969
2006-02-09more code for instructions... Mainly for coprocessor0 and coprocessor1 move ↵Korey Sewell
instructions --HG-- extra : convert_revision : 34e017fd0a6f330f2ac17d34af216fc14f09dd42
2006-02-08Code for more "BasicOp" instructions ... formats for all instructions in ↵Korey Sewell
place ... Edits to Branch Format arch/mips/isa/decoder.isa: Code for di,ei,seb,seh,clz,and clo .... Every instruction has a format now (of course these are initial formats are still subject to change!) arch/mips/isa/formats/branch.isa: Format Branch in MIPS similar to Alpha Format --HG-- extra : convert_revision : 2118a1d9668610b1e9f1dea66d878b7b36c1ac7e
2006-02-08add at least BasicOp Format to most if not all instructionsKorey Sewell
and file name changes ... arch/mips/isa/decoder.isa: add at least BasicOp Format to most if not all instructions --HG-- rename : arch/mips/isa/formats/basic.format => arch/mips/isa/formats/basic.isa rename : arch/mips/isa/formats/branch.format => arch/mips/isa/formats/branch.isa rename : arch/mips/isa/formats/fp.format => arch/mips/isa/formats/fp.isa rename : arch/mips/isa/formats/int.format => arch/mips/isa/formats/int.isa rename : arch/mips/isa/formats/mem.format => arch/mips/isa/formats/mem.isa rename : arch/mips/isa/formats/noop.format => arch/mips/isa/formats/noop.isa rename : arch/mips/isa/formats/tlbop.format => arch/mips/isa/formats/tlbop.isa rename : arch/mips/isa/formats/trap.format => arch/mips/isa/formats/trap.isa rename : arch/mips/isa/mips.isa => arch/mips/isa/main.isa extra : convert_revision : 0b2f3aee13fee3e0e25c0c746af4216c4a596391
2006-02-07Actually we do need a separate class for Integer Ops with Immediates!!!Korey Sewell
The extra class is needed because of the necessisty of an immediate member variable. Also, added some 'very modest' python code to choose between the IntOp and the IntImmOp based on the instruction name ... --HG-- extra : convert_revision : f109c12418202a99b40e270360134e8335739836
2006-02-07name changes ... minor IntOP format changeKorey Sewell
arch/mips/isa/formats/int.format: Looks like Integer Ops with Immediates may not need their own separate class because all those instructions are distinct from their reg-reg counterparts --HG-- rename : arch/mips/isa/bitfields.def => arch/mips/isa/bitfields.isa rename : arch/mips/isa/decoder.def => arch/mips/isa/decoder.isa rename : arch/mips/isa/formats.def => arch/mips/isa/formats.isa rename : arch/mips/isa/includes.h => arch/mips/isa/includes.isa rename : arch/mips/isa/operands.def => arch/mips/isa/operands.isa extra : convert_revision : 8e354b4232b28c0264d98d333d55ef8b5a6589cc
2006-02-041st full draft switch statement actions for all integer arithmetic ↵Korey Sewell
operations and the majority of the load & store operations (not all of FP-Ops), Output,Format, & Template code needs to be adjusted to correctly take these "decoder.h" inputs ... --HG-- extra : convert_revision : 3dcde1f2f587e2766fd61231a93d34d1d7727356
2006-02-03mainly added minor support for the basic arithmetic operations (add, mult, ↵Korey Sewell
shift) arch/mips/isa/bitfields.def: Add comment, move definition up in file arch/mips/isa/decoder.def: add basic arithmetic operations arch/mips/isa/formats/fp.format: change Integer -> FP words arch/mips/isa/formats/int.format: Add derived IntImm class arch/mips/isa/operands.def: change to MIPS sytle operands --HG-- rename : arch/mips/isa/formats/fpop.format => arch/mips/isa/formats/fp.format rename : arch/mips/isa/formats/integerop.format => arch/mips/isa/formats/int.format extra : convert_revision : a95da47bc981e56a9898421da4eeb9c442d1dc15
2006-02-03.h -> .defKorey Sewell
--HG-- rename : arch/mips/isa/bitfields.h => arch/mips/isa/bitfields.def rename : arch/mips/isa/decoder.h => arch/mips/isa/decoder.def rename : arch/mips/isa/formats.h => arch/mips/isa/formats.def rename : arch/mips/isa/operands.h => arch/mips/isa/operands.def extra : convert_revision : 45cb5485311d51982ebcaf1c7eec34e8751c31f5
2006-02-03Rename: arch/mips/isa/formats/tlb.format -> arch/mips/isa/formats/tlbop.formatKorey Sewell
--HG-- rename : arch/mips/isa/formats/tlb.format => arch/mips/isa/formats/tlbop.format extra : convert_revision : 5b1cfba4a5b687c9a271e1a3f67f75e3fa6c2dde
2006-02-03Checkin (Merge?) files ... Added a few new format filesKorey Sewell
arch/mips/isa/formats/fpop.format: Floating Point Formats arch/mips/isa/formats/tlb.format: TLB Ops Format arch/mips/isa/mips.isa: Name change to mips.isa --HG-- rename : arch/mips/isa_desc/bitfields.h => arch/mips/isa/bitfields.h rename : arch/mips/isa_desc/decoder.h => arch/mips/isa/decoder.h rename : arch/mips/isa_desc/formats.h => arch/mips/isa/formats.h rename : arch/mips/isa_desc/formats/basic.format => arch/mips/isa/formats/basic.format rename : arch/mips/isa_desc/formats/branch.format => arch/mips/isa/formats/branch.format rename : arch/mips/isa_desc/formats/integerop.format => arch/mips/isa/formats/integerop.format rename : arch/mips/isa_desc/formats/mem.format => arch/mips/isa/formats/mem.format rename : arch/mips/isa_desc/formats/noop.format => arch/mips/isa/formats/noop.format rename : arch/mips/isa_desc/formats/trap.format => arch/mips/isa/formats/trap.format rename : arch/mips/isa_desc/includes.h => arch/mips/isa/includes.h rename : arch/mips/isa_desc/operands.h => arch/mips/isa/operands.h extra : convert_revision : 069a24da405b613f688e693fd038ac7a30a4faed
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-27 17:59:34 +0000