| Age | Commit message (Collapse) | Author |
|---|
|
arch/sparc/isa/base.isa:
Added a set of abbreviations for the different condition tests.
arch/sparc/isa/decoder.isa:
Fixes and additions to get syscall emulation closer to working.
arch/sparc/isa/formats/branch.isa:
Fixed branches so that the immediate version actually uses the immediate value
arch/sparc/isa/formats/integerop.isa:
Compute the condition codes -before- writing to the state of the machine.
arch/sparc/isa/formats/mem.isa:
An attempt to fix up the output of the disassembly of loads and stores.
arch/sparc/isa/formats/trap.isa:
Added code to disassemble a trap instruction. This probably needs to be fixed up so there are immediate and register versions.
arch/sparc/isa/operands.isa:
Added an R1 operand, and fixed up the numbering
arch/sparc/isa_traits.hh:
SyscallNumReg is no longer needed, the max number of sources and destinations are fixed up, and the syscall return uses xcc instead of icc.
arch/sparc/linux/process.cc:
arch/sparc/linux/process.hh:
Added a getresuidFunc syscall implementation. This isn't actually used, but I thought it was and will leave it in.
arch/sparc/process.cc:
arch/sparc/process.hh:
Fixed up how the initial stack frame is set up.
arch/sparc/regfile.hh:
Changed the number of windows from 6 to 32 so we don't have to worry about spill and fill traps for now, and commented out the register file setting itself up.
cpu/cpu_exec_context.hh:
cpu/exec_context.hh:
cpu/simple/cpu.hh:
sim/process.cc:
sim/process.hh:
Changed the syscall mechanism to pass down the syscall number directly.
--HG--
extra : convert_revision : 15723b949a0ddb3d24e68c079343b4dba2439f43
|
|
arch/alpha/isa_traits.hh:
arch/mips/isa_traits.cc:
Turned the integer register file into a class instead of a typedef to an array.
arch/alpha/regfile.hh:
Changed the integer register file into a class instead of a typedef to an array. Also put the parts of the register file, ie the int, float, and misc register files, pc, npc, and nnpc, behind accessor functions. Added a changeContext function, and ContextParam and ContextVal types, so that things like the register window can be changed through call backs.
arch/mips/isa_traits.hh:
Turned the integer register file into a class instead of a typedef to an array. Also moved a "using namespace" into the namespace definition.
arch/sparc/isa_traits.hh:
Turned the integer register file into a class instead of a typedef to an array. Also "fixed" the max number of src and dest regs. They may need to be even larger.
arch/sparc/regfile.hh:
Changed the integer register file into a class instead of a typedef to an array. Also put the parts of the register file, ie the int, float, and misc register files, pc, npc, and nnpc, behind accessor functions. Added a changeContext function, and ContextParam and ContextVal types, so that things like the register window can be changed through call backs. Created setCWP and setAltGlobals functions for the IntRegFile.
cpu/cpu_exec_context.hh:
Used the accessor functions for the register file, and added a changeRegFileContext function to call back into the RegFile. Used the RegFile clear function rather than memsetting it to 0.
cpu/exec_context.hh:
Added the changeRegFileContext function.
cpu/exetrace.cc:
Use the TheISA::NumIntRegs constant, and use readReg now that the integer register file is a class instead of an array.
cpu/exetrace.hh:
Get the address of the regs object, now that it isn't an array.
--HG--
extra : convert_revision : ea2dd81be1c2e66b3c684af319eb58f8a77fd49c
|
|
--HG--
extra : convert_revision : 9ad2bde341a9efb2826159229427b719ff2142f4
|
|
arch/sparc/isa/decoder.isa:
Replaced register number munging with RdLow and RdHigh operands.
arch/sparc/isa/formats/mem.isa:
Fixed how the address calculation code is dealt with.
arch/sparc/isa/operands.isa:
Changed the tabbing so that the whole oeprands block was consistent, and added RdLow and RdHigh operands. These registers are used when Rd is meant to refer to a pair of registers, rather than just one.
arch/sparc/isa_traits.hh:
Moved some functions to the new (to SPARC) utility.hh file. Also, dummy Fpcr_DepTag and Uniq_DepTag DepTags were added to pacify Tru64. These need to be removed, and Tru64 needs to not be compiled in if it isn't appropriate.
arch/sparc/regfile.hh:
Changed regSpace to have the correct size.
arch/sparc/utility.hh:
A new file for sparc to match the one for alpha.
--HG--
extra : convert_revision : ff6b529093d15f327ec11f067ad533bacdba9932
|
|
--HG--
extra : convert_revision : c4e66cd678313f7fe169787cb1bf3e45f114c4fd
|
|
into ewok.(none):/home/gblack/m5/newmem
arch/sparc/isa/decoder.isa:
SCCS merged
--HG--
extra : convert_revision : 460843b49bc96b3fbc5897828c23f9cf9b010ae0
|
|
arch/alpha/types.hh:
Moved the DependenceTags enum from types to constants.
arch/sparc/faults.cc:
arch/sparc/faults.hh:
Corrected a misspelling of PriviledgeOpcode and PrivilegedAction.
arch/sparc/isa/formats.isa:
Fixups towards compiling. Added a few additional instruction formats.
--HG--
extra : convert_revision : 4c5506877b71b8a5c8c45db41192cf759cdac374
|
|
arch/sparc/isa/bitfields.isa:
the trap field is 7:0
arch/sparc/isa/decoder.isa:
add code to in the Tcc instruction to call a syscall
arch/sparc/isa_traits.hh:
We need the syscall num register
--HG--
extra : convert_revision : 0861ec1dd8c7cac57765b22bc408fdffbe63fe2a
|
|
is changed
Add a default machine width parameter
Arch based live processes
arch/alpha/linux/process.cc:
arch/alpha/linux/process.hh:
arch/alpha/process.cc:
arch/alpha/process.hh:
arch/alpha/tru64/process.cc:
arch/alpha/tru64/process.hh:
arch/mips/linux_process.cc:
arch/mips/process.cc:
arch/mips/process.hh:
arch/sparc/linux/process.cc:
arch/sparc/linux/process.hh:
arch/sparc/process.cc:
arch/sparc/process.hh:
configs/test/test.py:
python/m5/objects/Process.py:
sim/process.cc:
sim/process.hh:
Architecture based live processes
arch/mips/isa_traits.hh:
arch/sparc/isa_traits.hh:
Add a default machine width parameter
mem/port.hh:
gcc 4 really wants a virtual destructor
sim/byteswap.hh:
remove the comment around long and unsigned long even though uint32_t
and int32_t are defined. Seems to work with gcc 4 and 3.4.3.
sim/syscall_emul.cc:
sim/syscall_emul.hh:
add translations for new sections that are mmapped or when the brk
is changed
--HG--
extra : convert_revision : e2f9f228113c7127c87ef2358209a399c30ed5c6
|
|
--HG--
extra : convert_revision : 156670995fa61599e763b002cd70f31f19b108d1
|
|
into zeep.eecs.umich.edu:/z/saidi/work/m5.ma2
arch/alpha/isa_traits.hh:
arch/alpha/linux/process.cc:
arch/sparc/isa_traits.hh:
arch/sparc/linux/process.cc:
sim/process.cc:
merge
--HG--
rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh
extra : convert_revision : fea0155c8e23abbd0d5d5251abbd0f4d223fe935
|
|
check abi-tag note section of elf binary for OS
add pseudo functions (moved from alpha and made to be generic)
move setsyscallreturn into isa traits
arch/alpha/SConscript:
no more common syscall emulation, now common for everyone
arch/alpha/isa_traits.hh:
move setsyscallreturn into isa description
arch/alpha/linux/process.cc:
arch/alpha/tru64/process.cc:
use generic functions rather than alpha specific ones
arch/sparc/isa_traits.hh:
have consts for generic pseudo syscalls
arch/sparc/linux/process.cc:
use generic functions
base/loader/elf_object.cc:
check abi-tag note section of elf binary for OS
cpu/exec_context.hh:
move syssyscallreturn into isa traits
sim/process.cc:
find call num with a more generic
sim/syscall_emul.cc:
sim/syscall_emul.hh:
add pseudo functions (moved from alpha and made to be generic)
--HG--
extra : convert_revision : 5a31024ecde7e39b830365ddd84593ea501a34d2
|
|
arch/alpha/isa_traits.hh:
arch/sparc/isa_traits.hh:
add nnpc for compiling purposes in exec_context setNextNPC function
cpu/exec_context.hh:
set NNPC function
cpu/simple/cpu.cc:
use NNPC in determining what PC we are using
--HG--
extra : convert_revision : e810cfbc5dc31879b20d2cc40bf9871613203532
|
|
arch/alpha/isa_traits.hh:
Changed the enums to const ints, and got rid of a few unnecessary constants.
arch/sparc/isa_traits.hh:
Got rid of the enums, and added in some missing constants.
--HG--
extra : convert_revision : ee47890af9d8c67300b31d8e0dda1d580bd21479
|
|
arch/SConscript:
ev5 should now be contained within alpha specific code.
arch/alpha/ev5.cc:
arch/alpha/isa_traits.hh:
Added getInstAsid and getDataAsid functions. These should be removed when the SimpleScalar cpu model is removed.
arch/sparc/isa_traits.hh:
Added getInstAsid and getDataAsid functions. These should be removed when the SimpleScalar cpu model is removed. Also made some small fixes.
cpu/o3/alpha_cpu.hh:
Added typedefs which are required now that there isn't a using namespace EV5.
cpu/o3/alpha_cpu_impl.hh:
Some small changes so that ev5.hh isn't needed directly.
cpu/o3/cpu.hh:
Removed including ev5.hh, and pushed retrieving the Asid into the MiscRegFile.
cpu/o3/regfile.hh:
Removed the include of ev5.hh, using namespace EV5, and the now redundant ipr array.
--HG--
extra : convert_revision : 5ef8f69435a3a888a3f06d0095d89326dafb33fd
|
|
--HG--
extra : convert_revision : a70d9cdbe26f44fa9d94e1cbadd92f8c909596ec
|
|
--HG--
extra : convert_revision : 7b22a4a4af5bcb13e2d9322ef93d3f582e8efa92
|
|
the isa_desc files, movement of byte_swap.hh into sim, and the creation of arch/isa_traits.hh
SConscript:
Moved some files out of targetarch. The either no longer need to be there, never needed to be there, or should be referred to directly in arch/alpha due to there strictly alpha content.
arch/alpha/isa_traits.hh:
Added alpha's endianness to it's isa_traits.hh
arch/mips/isa_traits.hh:
Added MIPS endianness to it's isa_traits.hh
arch/sparc/isa_traits.hh:
Added SPARCs endianess to it's isa_traits.hh
build/SConstruct:
Added MIPS as a valid architecture
cpu/exec_context.hh:
Included arch/isa_traits.hh to bring in the endianness of the system.
cpu/o3/alpha_cpu.hh:
Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding of little endianness
cpu/o3/fetch_impl.hh:
kern/freebsd/freebsd_system.cc:
Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding to little endianness.
sim/system.cc:
Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding to little endian.
--HG--
extra : convert_revision : b1ab34b7569db531cd1c74f273b24222e63f9007
|
|
--HG--
extra : convert_revision : f285a442b64eee183f7d0f6c203f0b0aa7ea8586
|
|
arch/mips/isa_desc/bitfields.h:
arch/mips/isa_desc/formats.h:
arch/mips/isa_desc/formats/basic.format:
arch/mips/isa_desc/formats/branch.format:
arch/mips/isa_desc/formats/integerop.format:
arch/mips/isa_desc/formats/mem.format:
arch/mips/isa_desc/formats/noop.format:
arch/mips/isa_desc/formats/trap.format:
arch/mips/isa_desc/includes.h:
arch/mips/isa_desc/operands.h:
arch/mips/isa_traits.cc:
arch/mips/isa_traits.hh:
copied from sparc ISA directory
arch/mips/isa_desc/decoder.h:
decoder I started to work on...
--HG--
rename : arch/sparc/isa_desc/bitfields.h => arch/mips/isa_desc/bitfields.h
rename : arch/sparc/isa_desc/decoder.h => arch/mips/isa_desc/decoder.h
rename : arch/sparc/isa_desc/formats.h => arch/mips/isa_desc/formats.h
rename : arch/sparc/isa_desc/formats/basic.format => arch/mips/isa_desc/formats/basic.format
rename : arch/sparc/isa_desc/formats/branch.format => arch/mips/isa_desc/formats/branch.format
rename : arch/sparc/isa_desc/formats/integerop.format => arch/mips/isa_desc/formats/integerop.format
rename : arch/sparc/isa_desc/formats/mem.format => arch/mips/isa_desc/formats/mem.format
rename : arch/sparc/isa_desc/formats/noop.format => arch/mips/isa_desc/formats/noop.format
rename : arch/sparc/isa_desc/formats/trap.format => arch/mips/isa_desc/formats/trap.format
rename : arch/sparc/isa_desc/includes.h => arch/mips/isa_desc/includes.h
rename : arch/sparc/isa_desc/operands.h => arch/mips/isa_desc/operands.h
rename : arch/sparc/isa_traits.cc => arch/mips/isa_traits.cc
rename : arch/sparc/isa_traits.hh => arch/mips/isa_traits.hh
extra : convert_revision : d4f281960ecf2dce479fb665469c6f2c5dd3063e
|
|
repository was created.
SConscript:
There is a new SConscript in the arch/alpha directory which has the alpha specific files. To add files for an arch, a similar file should be created.
arch/isa_parser.py:
The isa parser now supports include directives. These are done with ##include
build/SConstruct:
The target directory is passed on so that the architecture specific SConscript can have it. Also, sparc was added as a valid architecture type.
arch/alpha/SConscript:
This SConscript adds the alpha specific source
arch/sparc/isa_desc/operands.h:
This sets up the operand types that the sparc isa uses
arch/sparc/isa_traits.cc:
Implementation of sparc specific things, like a register file with windows
build/build_options/default/SPARC_SE:
The default options for a sparc syscall emulation build.
--HG--
extra : convert_revision : 1afedae61dc8cae0d59d3bf1d41420d929be2efd
|
