| Age | Commit message (Collapse) | Author |
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arch/alpha/arguments.cc:
There will not be a phys mem ptr in the XC in the newmem. This read will have to go through something else.
arch/alpha/ev5.cc:
Remove instantiations of these functions for the FastCPU, as the FastCPU is not really used. Also this messed up the ability to specify which CPU models are being built.
cpu/exec_context.hh:
Remove getPhysMemPtr() function.
cpu/exetrace.cc:
Include sim/system.hh, and sort the includes.
cpu/simple/cpu.cc:
Fixes for full system compilation.
kern/system_events.cc:
Remove include of encumbered FullCPU. The branch prediction will need to be fixed up in a more generic way in the future.
--HG--
extra : convert_revision : a8bbf562a277aa80e8f40112570c0a825298a05c
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fix tlbs for newmem
SConscript:
page_table.cc is a syscall only kinda thing
arch/alpha/tlb.cc:
arch/alpha/tlb.hh:
fix tlbs for newmem
--HG--
extra : convert_revision : 0aafcb9698b993a807be883bde1696ee4d33b408
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into zeep.eecs.umich.edu:/z/saidi/work/m5.newmem
--HG--
extra : convert_revision : 5ab4ce9f6ec7af326d8906060ae3558cfd67ca08
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don't ever include a file while in a namespace
start of making alpha console new memsystem happy
Make a BasePioDevice which is what all the simple Pio devices will inherit from
add a description of when the data pointer will have memory
arch/alpha/isa_traits.hh:
don't ever include a file while in a namespace
dev/alpha_console.cc:
dev/alpha_console.hh:
start of making alpha console new memsystem happy
dev/io_device.cc:
dev/io_device.hh:
Make a BasePioDevice which is what all the simple Pio devices will inherit from
mem/packet.hh:
add a description of when the data pointer will have memory
--HG--
extra : convert_revision : 495c0915541f9cad3eb42891e60b4ecbee7952bf
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--HG--
extra : convert_revision : c580bc6bd308fd502fb5a14ea84b5214e1d2718e
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The latter causes multiple variable definitions if the same operand
is used as both a src and a dest.
arch/alpha/isa/mem.isa:
arch/mips/isa/formats/mem.isa:
Use op_decl instead of op_src_decl + op_dest_decl.
The latter causes multiple variable definitions if the same operand
is used as both a src and a dest.
--HG--
extra : convert_revision : c14d91b293d3afef45c8728d3d8784f372c0b7f4
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(which wasn't working since panic() isn't declared yet here).
arch/alpha/faults.hh:
Make ItbFault methods abstract instead of calling panic()
(which wasn't working since panic() isn't declared yet here).
--HG--
extra : convert_revision : b15242baa370777f265a3f6b7d5f5c05702b016f
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Makes .isa files cleaner and simplifies scanner too.
Simplified scanner to work under both old and new versions of scons.
arch/SConscript:
Simplify .isa scanner... seems to work with both scons 0.96.1 and 0.96.91 now.
Assumes .isa ##include paths are relative to including file.
arch/alpha/isa/main.isa:
arch/mips/isa/formats/formats.isa:
arch/mips/isa/main.isa:
arch/sparc/isa/formats.isa:
arch/sparc/isa/main.isa:
Make ##include paths relative to including file.
arch/isa_parser.py:
Make ##include file paths relative to including file.
Makes .isa files cleaner and simplifies scanner too.
Partial rewrite of include-handling code to use cool re.sub() feature
where you can specify a function to provide the replacement string.
Minor cleanup of error-handling code.
Also got rid of '#!' at top to make caller choose which python interpreter
is used (since SPARC now requires 2.4 to build, we may need to do that via
scons in the future).
--HG--
rename : arch/mips/isa/formats.isa => arch/mips/isa/formats/formats.isa
extra : convert_revision : 15a3920fa3aaf80cd94083eda853aa4e49425045
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into ewok.(none):/home/gblack/m5/newmem
--HG--
extra : convert_revision : 7effd744f9061d4aa8e9c3fa769115dfa73cbb79
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arch/sparc/isa/decoder.isa:
Replaced register number munging with RdLow and RdHigh operands.
arch/sparc/isa/formats/mem.isa:
Fixed how the address calculation code is dealt with.
arch/sparc/isa/operands.isa:
Changed the tabbing so that the whole oeprands block was consistent, and added RdLow and RdHigh operands. These registers are used when Rd is meant to refer to a pair of registers, rather than just one.
arch/sparc/isa_traits.hh:
Moved some functions to the new (to SPARC) utility.hh file. Also, dummy Fpcr_DepTag and Uniq_DepTag DepTags were added to pacify Tru64. These need to be removed, and Tru64 needs to not be compiled in if it isn't appropriate.
arch/sparc/regfile.hh:
Changed regSpace to have the correct size.
arch/sparc/utility.hh:
A new file for sparc to match the one for alpha.
--HG--
extra : convert_revision : ff6b529093d15f327ec11f067ad533bacdba9932
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through its own fault() method; this is handled by the fault's invoke() methods.
arch/alpha/faults.cc:
Move TLB fault code into the normal fault invoke() method.
arch/alpha/faults.hh:
Move DTB/ITB fault handling code into their own class with a specific invoke() method. Have DTB/ITB faults derive from these classes.
Unfortunately the DtbAlignmentFault is somewhat odd; it's a normal alignment fault, but it must also set some specific IPRs.
arch/alpha/tlb.cc:
arch/alpha/tlb.hh:
Setting IPRs is now handled through the fault itself.
--HG--
extra : convert_revision : 5cb92ce2186ff79f632bfcbc9ba62a8a04400eae
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into ewok.(none):/home/gblack/m5/newmem
--HG--
extra : convert_revision : 762df7bf15e8e22a8fab8bbcd933047d1c8cdfa9
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arch/sparc/isa/decoder.isa:
Fixed comments so they don't comment out the ending braces of the format specifier.
--HG--
extra : convert_revision : 3f037c0a17abd0dff71d22fdcd95959c3670e88a
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arch/mips/isa/base.isa:
disassembly fixes
arch/mips/isa/decoder.isa:
support for unaligned loads/stores
arch/mips/isa_traits.hh:
edit Syscall Reg values
arch/mips/linux_process.cc:
call writevFunc on writev syscall
--HG--
extra : convert_revision : 4aea6d069bd7ba0e83b23d2d85c50d68532f0454
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arch/mips/isa_traits.hh:
use syscall return function from alpha
arch/mips/linux_process.cc:
fix some syntax errors, map some functions to the desc. table
--HG--
extra : convert_revision : 75e8e8893b7d96bb4fc8e8eced53bd16c0a727d1
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into zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-mips
--HG--
extra : convert_revision : 1646b4fb065e3ed9d8de22e3f5c3aa05a2ef01b6
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arch/mips/isa/decoder.isa:
arch/mips/isa_traits.hh:
sim/syscall_emul.cc:
make syscall instruction functional
arch/mips/linux_process.cc:
add all MIPS/Linux syscalls to descriptor list
--HG--
extra : convert_revision : 5455a345e76be921e9f63b248aef874b6358e465
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--HG--
extra : convert_revision : 2ffbfc4755e46a119c9709d6a5e9ddc41fde45e0
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into ewok.(none):/home/gblack/m5/newmem
arch/sparc/isa/decoder.isa:
Hand merged
--HG--
extra : convert_revision : 5d5338602c48be48978972a091c5e93f9dd775aa
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--HG--
extra : convert_revision : c4e66cd678313f7fe169787cb1bf3e45f114c4fd
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put back in Tcc code that was deleted in last merge
arch/sparc/isa/bitfields.isa:
clean up condition codes a little bit
--HG--
extra : convert_revision : c554fd5c3ee8cfd6643f69f8351124a7a4b5d9fa
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--HG--
extra : convert_revision : fe4b7dc5b7d583e1d890648ba98bb0daf722a704
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into zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-mips
--HG--
extra : convert_revision : 02fe0b0170348dc6f6a985c15123806088a8c23e
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while
before getting in a infinite loop. It actually "tries" to syscall too, but syscalls
aren't implemented just yet
arch/mips/faults.cc:
more descriptive names for faults (will help future users as well as me!)
arch/mips/isa/base.isa:
make sure we are printing out "BasicOp" format disassembly instructions as dest,src,src instead of src,src,dest
arch/mips/isa/decoder.isa:
FIX LW/SW Bug!!!! I was actually loading a byte instead of a word
FIX JALR Bug!!!! I was not saving the link address in R31 for this instruction
FIX SLL/NOP Bug!!! We now recognize the varying flavors of sll,nop,ehb,& ssnop correctly
base/loader/elf_object.cc:
change back to original way
base/loader/elf_object.hh:
change back to original!
--HG--
extra : convert_revision : 39b65fba31c1842ac6966346fe8a35816a4231fa
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into ewok.(none):/home/gblack/m5/newmem
arch/sparc/isa/decoder.isa:
SCCS merged
--HG--
extra : convert_revision : 460843b49bc96b3fbc5897828c23f9cf9b010ae0
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arch/alpha/types.hh:
Moved the DependenceTags enum from types to constants.
arch/sparc/faults.cc:
arch/sparc/faults.hh:
Corrected a misspelling of PriviledgeOpcode and PrivilegedAction.
arch/sparc/isa/formats.isa:
Fixups towards compiling. Added a few additional instruction formats.
--HG--
extra : convert_revision : 4c5506877b71b8a5c8c45db41192cf759cdac374
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into zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-mips
--HG--
extra : convert_revision : 9bdde9b5bd3049744451eda1134f080b7c4b1b59
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arch/sparc/isa/bitfields.isa:
the trap field is 7:0
arch/sparc/isa/decoder.isa:
add code to in the Tcc instruction to call a syscall
arch/sparc/isa_traits.hh:
We need the syscall num register
--HG--
extra : convert_revision : 0861ec1dd8c7cac57765b22bc408fdffbe63fe2a
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is changed
Add a default machine width parameter
Arch based live processes
arch/alpha/linux/process.cc:
arch/alpha/linux/process.hh:
arch/alpha/process.cc:
arch/alpha/process.hh:
arch/alpha/tru64/process.cc:
arch/alpha/tru64/process.hh:
arch/mips/linux_process.cc:
arch/mips/process.cc:
arch/mips/process.hh:
arch/sparc/linux/process.cc:
arch/sparc/linux/process.hh:
arch/sparc/process.cc:
arch/sparc/process.hh:
configs/test/test.py:
python/m5/objects/Process.py:
sim/process.cc:
sim/process.hh:
Architecture based live processes
arch/mips/isa_traits.hh:
arch/sparc/isa_traits.hh:
Add a default machine width parameter
mem/port.hh:
gcc 4 really wants a virtual destructor
sim/byteswap.hh:
remove the comment around long and unsigned long even though uint32_t
and int32_t are defined. Seems to work with gcc 4 and 3.4.3.
sim/syscall_emul.cc:
sim/syscall_emul.hh:
add translations for new sections that are mmapped or when the brk
is changed
--HG--
extra : convert_revision : e2f9f228113c7127c87ef2358209a399c30ed5c6
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arch/mips/isa/formats/branch.isa:
let user know that we alter r31 in disassembly
arch/mips/isa_traits.cc:
add copyRegs function ...
comment out serialize float code for now
arch/mips/isa_traits.hh:
make FloatRegFile a class ... change values of architectural regs
arch/mips/process.cc:
change MIPS to Mips
base/loader/elf_object.cc:
get global pointer initialized to a value
base/loader/elf_object.hh:
Add global_ptr to elf_object constructor
base/loader/object_file.hh:
MIPS to Mips
base/traceflags.py:
SimpleCPU trace flag
cpu/simple/cpu.cc:
DPRINTF flags for SimpleCPU
cpu/static_inst.hh:
Add Decoder functions to static_inst.hh
--HG--
extra : convert_revision : 0544a8524d3fe4229428cb06822f7da208c72459
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into zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem
--HG--
extra : convert_revision : 054833d2f7019b9a1247efc4451ccb143242059d
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output fault name in simple cpu
SConscript:
Separate Alpha EIO from syscall building for other architectures
arch/isa_specific.hh:
change MIPS constant to 34k
arch/mips/isa/decoder.isa:
Allow sll,ssnop,nop, and ehb to be determined through decoder using
the different types of default cases
arch/mips/isa/formats/branch.isa:
Delete debug code
arch/mips/isa/formats/noop.isa:
add a Nop format
arch/mips/isa_traits.hh:
use constants instead of enums
arch/mips/process.cc:
point to the correct header file
cpu/simple/cpu.cc:
Output the actual fault name
sim/process.cc:
Inititalize NNPC
--HG--
extra : convert_revision : adb0026dfad25b14c98fb03c98bfe9c681bba6f8
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arch/alpha/utility.hh:
Got rid of unnecessary extern and static qualifiers, and fixed up the hand merge.
arch/sparc/regfile.hh:
Fixed up SPARC after a hand merge.
--HG--
extra : convert_revision : 56e2d90ddd144f3386dbea50fa96cfc461d46b81
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into ewok.(none):/home/gblack/m5/newmem
cpu/cpu_exec_context.cc:
Hand merge
--HG--
rename : arch/alpha/registerfile.hh => arch/alpha/regfile.hh
extra : convert_revision : bd18966f7c37c67c2bc7ca2633b58f70ce64409c
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--HG--
rename : arch/alpha/registerfile.hh => arch/alpha/regfile.hh
extra : convert_revision : 27df93cd2259dab85057f966c801c0db2cb6f022
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--HG--
extra : convert_revision : 7bc8ca989a4f0225ad5644980c8dbc34b0c0e35f
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--HG--
extra : convert_revision : 156670995fa61599e763b002cd70f31f19b108d1
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accessor functions. The width of the floating point register to access can be specified, and if not, it will be accessed at its "natural" width. That is, the width of each individual register. Also, the functions which access the bit representation of floating point registers can use the blahblahBits functions now instead of blahblahInt.
arch/alpha/arguments.cc:
Renamed readFloatRegInt to readFloatRegBits
arch/alpha/ev5.cc:
Removed the Double from setFloatRegDouble
arch/alpha/registerfile.hh:
Changed the floating point register file from a union of arrays to a class with appropriate accessor functions. The interface is necessary for SPARC.
arch/alpha/types.hh:
Changed the FloatReg type from a union of uint64_t and double to a double, and defined a new type FloatRegBits which is a uint64_t and is used to return the bits which compose a floating point register rather than the value of the register.
arch/isa_parser.py:
Adjusted the makeRead and makeWrite functions to generate the new versions of readFloatReg and setFloatReg.
base/remote_gdb.cc:
kern/tru64/tru64.hh:
Replaced setFloatRegInt with setFloatRegBits
cpu/cpu_exec_context.cc:
Removed the duplicated code for setting the floating point registers, and renamed the function to setFloatRegBits and readFloatRegBits.
cpu/cpu_exec_context.hh:
cpu/exec_context.hh:
cpu/o3/alpha_cpu_impl.hh:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
cpu/o3/regfile.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.hh:
Implemented the new versions of the floating point read and set functions.
cpu/simple/cpu.cc:
Replaced setFloatRegDouble with setFloatReg
--HG--
extra : convert_revision : 3dad06224723137f6033c335fb8f6395636767f2
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ExecContext to another ExecContext. This makes it easier for anything that needs to copy architected registers to do so in an ISA independent fashion.
arch/alpha/ev5.cc:
copyIprs now copies from a source ExecContext to a destination ExecContext.
arch/alpha/registerfile.hh:
Have ISA specific functions to copy all architected registers from one ExecContext to another.
cpu/cpu_exec_context.cc:
Call the ISA in order to copy any architected registers.
--HG--
extra : convert_revision : 056cc3b3a9f345535d5a57c6524b114bbd5ae3c8
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arch/alpha/process.cc:
arch/mips/process.cc:
arch/sparc/process.cc:
You really do need the headers in the .cc file.
arch/alpha/process.hh:
Don't include unnecessary headers in another header.
Replace with forward class declarations.
arch/mips/process.hh:
arch/sparc/process.hh:
Don't include unnecessary headers in another header.
Replace with forward class declarations.
Also fix std namespace... no "using" in header files!
--HG--
extra : convert_revision : f2cd953d0f4a212bb8148cc54c329aa3c18deb89
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arch/alpha/isa_traits.hh:
No unprotected "using" in header files.
cpu/simple/cpu.cc:
Fix ISA namespace "using" statement.
--HG--
extra : convert_revision : 317ea40f8de00748d7613a0116edab05770bdc72
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into zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem
--HG--
extra : convert_revision : b101fa550567d5a9f5de6c2d8c3f67829ae050c1
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arch/alpha/isa_traits.hh:
used for SimpleCPU instead of explicitly calling the namespace we declare in isa_traits.hhs
so other archs. can use SimpleCPU
arch/mips/SConscript:
dont include common_syscall or tru64
arch/mips/faults.cc:
arch/mips/faults.hh:
arch/mips/isa/formats/unimp.isa:
arch/mips/isa/formats/unknown.isa:
Change Faults to new format
arch/mips/isa/decoder.isa:
Fix readMiscReg access
Made change so that you cant explicitly tell if a instruction nop,ehb,or ssnop... These are all variants
of the sll instruction so I may need to make a separte class of instructions to handle thse better
arch/mips/isa/includes.isa:
add isa_traits.hh and MipsISA included into every auto-gen file
arch/mips/isa_traits.cc:
create copyMiscRegs function...
delete useless code
arch/mips/isa_traits.hh:
clean up for build
arch/mips/linux_process.cc:
mem is now getMemPort(), linux process objects now take in a system argument
arch/mips/linux_process.hh:
new argument for linux process
arch/mips/process.cc:
add system
arch/mips/process.hh:
add system variable
cpu/cpu_exec_context.cc:
Change AlphaISA to TheISA
cpu/exec_context.hh:
add readNextNPC and setNextNPC functions
cpu/simple/cpu.cc:
include isa_traits for namespace declariation
cpu/simple/cpu.hh:
PC & NPC access/modify functions
arch/mips/utility.hh:
file needed for compile
--HG--
extra : convert_revision : 29a327e79c51c6174a6e526aa68c7aab7e7eb535
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into zizzer.eecs.umich.edu:/z/stever/bk/newmem-head
--HG--
extra : convert_revision : a784e60b7f79d70b09052fc4a8ae35a821d307dc
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an obsolete function that doesn't exist.
arch/alpha/tru64/process.cc:
sim/process.cc:
Don't include useless header.
--HG--
extra : convert_revision : 1dd5edeb0703e2190b89ea5ff563df4c95b7cf59
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--HG--
extra : convert_revision : f825fcf53e716efc62e541692cb4ed26366abc26
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arch/SConscript:
Sorted the switch headers, and added registerfile.hh, constants.hh, types.hh, and utility.hh.
arch/alpha/isa_traits.hh:
Moved the register file types to registerfile.hh, small functions to utility.hh, and cleaned out alot of stuff that isn't necessary anymore.
base/loader/ecoff_object.cc:
base/loader/elf_object.cc:
cpu/pc_event.hh:
cpu/static_inst.hh:
mem/port.hh:
sim/faults.cc:
sim/system.hh:
base/misc.hh isn't included through isa_traits.hh anymore.
cpu/simple/cpu.cc:
Added include for arch/utility.hh
--HG--
extra : convert_revision : 24f65f330f87e3c909c939596cfcf48336022eaf
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--HG--
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here any more.
--HG--
extra : convert_revision : 443ae3fe4d7ac99ef5cbd1366266604bb13761c3
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included within isa_traits.hh
--HG--
extra : convert_revision : e49935da238a299e681f9137ad3c0b7dc0e226a3
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