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AgeCommit message (Expand)Author
2006-02-28Add quiesceNs, quiesceTime, quiesceCycles, and m5panic pseudo ops.Ali Saidi
2006-02-25Make sure cpu/static_inst_exec_sigs.hh get rebuilt whenSteve Reinhardt
2006-02-23Enable building only selected CPU models via new sconsSteve Reinhardt
2006-02-23ev5.cc:Ali Saidi
2006-02-23Merge zizzer:/bk/m5Ali Saidi
2006-02-23Get rid of the xc from the alphaAccess/alphaConsole backdoor device.Ali Saidi
2006-02-23Create a Builder object for .isa files in arch/SConscript.Steve Reinhardt
2006-02-23Add pipe() syscall to Alpha Linux emulation.Steve Reinhardt
2006-02-22Auto-generate arch/foo.hh "switch headers" in scons.Steve Reinhardt
2006-02-22Clean excess comments out of SConscripts.Steve Reinhardt
2006-02-21Changed Fault * to Fault, which is a typedef to FaultBase *, which is the old...Gabe Black
2006-02-21Made Addr a global typeGabe Black
2006-02-20make MIPS specificKorey Sewell
2006-02-20load/store instruction format ... now generates load/store codeKorey Sewell
2006-02-20Support for All Jump Instructions ...Korey Sewell
2006-02-19Reapplied changes which were undone by a pullGabe Black
2006-02-19Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5Gabe Black
2006-02-19Merge gblack@m5.eecs.umich.edu:/bk/multiarchGabe Black
2006-02-19Changes to untemplate StaticInst and StaticInstPtr, change the isa to a names...Gabe Black
2006-02-19Merge zizzer:/bk/m5Ali Saidi
2006-02-19forgot a negative signAli Saidi
2006-02-18Move Linux/Tru64 architecture independent code into kern/*Ali Saidi
2006-02-18Support NNPC and branch instructions ... Outputs to decoder.cc correctlyKorey Sewell
2006-02-18Merge gblack@m5.eecs.umich.edu:/bk/multiarchGabe Black
2006-02-18Changed the isa from a class to a namespace, untemplated StaticInst and Stati...Gabe Black
2006-02-18changes from mergedmemKorey Sewell
2006-02-18use string name to figure out if we have a "AndLink" instructionKorey Sewell
2006-02-18MIPS generates ISA code through scons '.../decoder.cc'!!!Korey Sewell
2006-02-16Remove fake fault.Kevin Lim
2006-02-16Merge ktlim@zizzer:/bk/m5Kevin Lim
2006-02-16Fixes to handle generating the initiateAcc and completeAcc functions a little...Kevin Lim
2006-02-16Get ISA parser to at least include all the ISA correctly ... crashes with "No...Korey Sewell
2006-02-16Merge zizzer:/bk/multiarchKorey Sewell
2006-02-16file name changes ... minor ISA changesKorey Sewell
2006-02-16Some changes which weren't needed before doing a bk pull were needed afterwar...Gabe Black
2006-02-16Merge gblack@m5.eecs.umich.edu:/bk/multiarchGabe Black
2006-02-16Changed the fault enum into a class, and fixed everything up to work with it....Gabe Black
2006-02-15Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5Gabe Black
2006-02-15...Korey Sewell
2006-02-15Gives separate methods for initiating and completing a memory access, which w...Kevin Lim
2006-02-15Merge zizzer:/bk/m5Ali Saidi
2006-02-15endian fixes and compiles on mac os xAli Saidi
2006-02-14Merge zizzer:/bk/multiarchKorey Sewell
2006-02-14another big step to a parsable ISA ... no errors after I used a symbolic link...Korey Sewell
2006-02-14trying to get ISA to parse correctly ...Korey Sewell
2006-02-14New files to fix building the SPARC_SE and MIPS_SE isa_parser.py generated fi...Gabe Black
2006-02-14Fixed a path in the alpha isa description.Gabe Black
2006-02-14Merge zizzer:/bk/multiarchKorey Sewell
2006-02-14make MIPS MT instructions decodable ...Korey Sewell
2006-02-12Pseudo instructions are now passed whatever instructions they need by the dec...Gabe Black
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