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2005-09-24Clean up indentation in isa_desc.Steve Reinhardt
arch/alpha/isa_desc: Little bit of re-ordering and indentation clean-up. --HG-- extra : convert_revision : e538ff89d8b507c3e1aa68a032578fcaa645d7ee
2005-09-11Explicitly handle rounding on FP-to-integer conversions.Steve Reinhardt
Seems to avoid the significant problems on platforms w/o fenv.h. arch/alpha/isa_desc: Explicitly handle rounding on FP-to-integer conversions. Seems to avoid the significant problems on platforms w/o fenv.h. Get rid of FP "Fast" vs "General" distinction... more headache than it's worth. arch/isa_parser.py: Fix bug with "%s" in C++ templates (must escape properly to pass through Python string interpolation). --HG-- extra : convert_revision : de964d764e67e0934ac0ef535f53c974640731fb
2005-09-02Bug fix: can't increment an iterator after you eraseSteve Reinhardt
the thing it points to. Somehow Linux doesn't care, but Cygwin sure does. --HG-- extra : convert_revision : 1209a75831f080f17a95433e546d7074f9f07332
2005-08-30Build options are set via a build_options file in theSteve Reinhardt
build directory instead of being inferred from the name of the build directory. Options are passed to C++ via config/*.hh files instead of via the command line. Build option flags are now always defined to 0 or 1, so checks must use '#if' rather than '#ifdef'. SConscript: MySQL detection moved to SConstruct. Add config/*.hh files (via ConfigFile builder). arch/alpha/alpha_memory.cc: arch/alpha/ev5.cc: arch/alpha/ev5.hh: arch/alpha/isa_traits.hh: base/fast_alloc.hh: base/statistics.cc: base/statistics.hh: base/stats/events.cc: base/stats/events.hh: cpu/base.cc: cpu/base.hh: cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: cpu/exec_context.cc: cpu/exec_context.hh: cpu/o3/alpha_cpu.hh: cpu/o3/alpha_cpu_builder.cc: cpu/o3/alpha_cpu_impl.hh: cpu/o3/alpha_dyn_inst.hh: cpu/o3/alpha_dyn_inst_impl.hh: cpu/o3/alpha_params.hh: cpu/o3/commit_impl.hh: cpu/o3/cpu.cc: cpu/o3/cpu.hh: cpu/o3/fetch_impl.hh: cpu/o3/iew.hh: cpu/o3/iew_impl.hh: cpu/o3/regfile.hh: cpu/o3/rename_impl.hh: cpu/o3/rob_impl.hh: cpu/ozone/cpu.hh: cpu/pc_event.cc: cpu/simple/cpu.cc: cpu/simple/cpu.hh: sim/process.cc: sim/process.hh: Convert compile flags from def/undef to 0/1. Set via #include config/*.hh instead of command line. arch/alpha/isa_desc: Convert compile flags from def/undef to 0/1. Set via #include config/*.hh instead of command line. Revamp fenv.h support... most of the ugliness is hidden in base/fenv.hh now. base/mysql.hh: Fix typo in #ifndef guard. build/SConstruct: Build options are set via a build_options file in the build directory instead of being inferred from the name of the build directory. Options are passed to C++ via config/*.hh files instead of via the command line. python/SConscript: Generate m5_build_env directly from scons options instead of indirectly via CPPDEFINES. python/m5/convert.py: Allow '0' and '1' for booleans. Rewrite toBool to use dict. base/fenv.hh: Revamp <fenv.h> support to make it a compile option (so we can test w/o it even if it's present) and to make isa_desc cleaner. --HG-- extra : convert_revision : 8f97dc11185bef5e1865b3269c7341df8525c9ad
2005-06-28Merge m5read@m5.eecs.umich.edu:/bk/m5Benjamin Nash
into zed.eecs.umich.edu:/z/benash/bk/m5 --HG-- extra : convert_revision : 453615c8194ae9ca96330b7493c6b19fc89c3a72
2005-06-28Don't hard code the location of m5AlphaAccess. Instead, move theNathan Binkert
code into a function that can be called by the AlphaConsole class. AlphaConsole will pass in its address. arch/alpha/ev5.hh: Move Phys2K0Seg to ev5.hh and fixup the TSUNAMI uncacheable bits so that they will be converted correctly. dev/alpha_access.h: Do not hard code the location of the AlphaConsole dev/alpha_console.cc: fixup #includes tell the system where the alpha console is sim/system.hh: Provide a function that will tell the system where the AlphaAccess structure (device) lives --HG-- extra : convert_revision : 92d70ca926151a32eebe9925de597459ac58013e
2005-06-17I/O changes and SkipFuncEvents to increase FreeBSD compatibility.Benjamin Nash
SConscript: Added kern/freebsd/freebsd_events.cc. arch/alpha/isa_traits.hh: Added Argument to support replacement of calibrate_clocks function in FreeBSD. dev/ns_gige.hh: Fixed NIC model number typo. dev/tsunami_io.cc: Added support for RTC writes and PIC 2 mask reads. Made RTC static member. dev/tsunami_io.hh: Made RTC static member. kern/freebsd/freebsd_system.cc: Added events to skip functions in FreeBSD. kern/freebsd/freebsd_system.hh: Added events to skip certain functions. --HG-- extra : convert_revision : 8aaca51d3f9b1bb601722a5bae240aae77b445db
2005-06-05Many files:Steve Reinhardt
Update copyright dates and author list SConscript: arch/alpha/alpha_linux_process.cc: arch/alpha/alpha_linux_process.hh: arch/alpha/alpha_memory.cc: arch/alpha/alpha_memory.hh: arch/alpha/alpha_tru64_process.cc: arch/alpha/alpha_tru64_process.hh: arch/alpha/aout_machdep.h: arch/alpha/arguments.cc: arch/alpha/arguments.hh: arch/alpha/ev5.cc: arch/alpha/ev5.hh: arch/alpha/faults.cc: arch/alpha/faults.hh: arch/alpha/isa_desc: arch/alpha/isa_traits.hh: arch/alpha/osfpal.cc: arch/alpha/osfpal.hh: arch/alpha/pseudo_inst.cc: arch/alpha/pseudo_inst.hh: arch/alpha/vptr.hh: arch/alpha/vtophys.cc: arch/alpha/vtophys.hh: base/bitfield.hh: base/callback.hh: base/circlebuf.cc: base/circlebuf.hh: base/cprintf.cc: base/cprintf.hh: base/cprintf_formats.hh: base/crc.hh: base/date.cc: base/dbl_list.hh: base/endian.hh: base/fast_alloc.cc: base/fast_alloc.hh: base/fifo_buffer.cc: base/fifo_buffer.hh: base/hashmap.hh: base/hostinfo.cc: base/hostinfo.hh: base/hybrid_pred.cc: base/hybrid_pred.hh: base/inet.cc: base/inet.hh: base/inifile.cc: base/inifile.hh: base/intmath.cc: base/intmath.hh: base/match.cc: base/match.hh: base/misc.cc: base/misc.hh: base/mod_num.hh: base/mysql.cc: base/mysql.hh: base/output.cc: base/output.hh: base/pollevent.cc: base/pollevent.hh: base/predictor.hh: base/random.cc: base/random.hh: base/range.cc: base/range.hh: base/refcnt.hh: base/remote_gdb.cc: base/remote_gdb.hh: base/res_list.hh: base/sat_counter.cc: base/sat_counter.hh: base/sched_list.hh: base/socket.cc: base/socket.hh: base/statistics.cc: base/statistics.hh: base/compression/lzss_compression.cc: base/compression/lzss_compression.hh: base/compression/null_compression.hh: base/loader/aout_object.cc: base/loader/aout_object.hh: base/loader/ecoff_object.cc: base/loader/ecoff_object.hh: base/loader/elf_object.cc: base/loader/elf_object.hh: base/loader/object_file.cc: base/loader/object_file.hh: base/loader/symtab.cc: base/loader/symtab.hh: base/stats/events.cc: base/stats/events.hh: base/stats/flags.hh: base/stats/mysql.cc: base/stats/mysql.hh: base/stats/mysql_run.hh: base/stats/output.hh: base/stats/statdb.cc: base/stats/statdb.hh: base/stats/text.cc: base/stats/text.hh: base/stats/types.hh: base/stats/visit.cc: base/stats/visit.hh: base/str.cc: base/str.hh: base/time.cc: base/time.hh: base/timebuf.hh: base/trace.cc: base/trace.hh: base/userinfo.cc: base/userinfo.hh: build/SConstruct: cpu/base.cc: cpu/base.hh: cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: cpu/exec_context.cc: cpu/exec_context.hh: cpu/exetrace.cc: cpu/exetrace.hh: cpu/inst_seq.hh: cpu/intr_control.cc: cpu/intr_control.hh: cpu/memtest/memtest.cc: cpu/pc_event.cc: cpu/pc_event.hh: cpu/smt.hh: cpu/static_inst.cc: cpu/static_inst.hh: cpu/memtest/memtest.hh: cpu/o3/sat_counter.cc: cpu/o3/sat_counter.hh: cpu/ozone/cpu.hh: cpu/simple/cpu.cc: cpu/simple/cpu.hh: cpu/trace/opt_cpu.cc: cpu/trace/opt_cpu.hh: cpu/trace/reader/ibm_reader.cc: cpu/trace/reader/ibm_reader.hh: cpu/trace/reader/itx_reader.cc: cpu/trace/reader/itx_reader.hh: cpu/trace/reader/m5_reader.cc: cpu/trace/reader/m5_reader.hh: cpu/trace/reader/mem_trace_reader.cc: cpu/trace/reader/mem_trace_reader.hh: cpu/trace/trace_cpu.cc: cpu/trace/trace_cpu.hh: dev/alpha_access.h: dev/alpha_console.cc: dev/alpha_console.hh: dev/baddev.cc: dev/baddev.hh: dev/disk_image.cc: dev/disk_image.hh: dev/etherbus.cc: dev/etherbus.hh: dev/etherdump.cc: dev/etherdump.hh: dev/etherint.cc: dev/etherint.hh: dev/etherlink.cc: dev/etherlink.hh: dev/etherpkt.cc: dev/etherpkt.hh: dev/ethertap.cc: dev/ethertap.hh: dev/ide_ctrl.cc: dev/ide_ctrl.hh: dev/ide_disk.cc: dev/ide_disk.hh: dev/io_device.cc: dev/io_device.hh: dev/ns_gige.cc: dev/ns_gige.hh: dev/ns_gige_reg.h: dev/pciconfigall.cc: dev/pciconfigall.hh: dev/pcidev.cc: dev/pcidev.hh: dev/pcireg.h: dev/pktfifo.cc: dev/pktfifo.hh: dev/platform.cc: dev/platform.hh: dev/simconsole.cc: dev/simconsole.hh: dev/simple_disk.cc: dev/simple_disk.hh: dev/sinic.cc: dev/sinic.hh: dev/sinicreg.hh: dev/tsunami.cc: dev/tsunami.hh: dev/tsunami_cchip.cc: dev/tsunami_cchip.hh: dev/tsunami_io.cc: dev/tsunami_io.hh: dev/tsunami_pchip.cc: dev/tsunami_pchip.hh: dev/tsunamireg.h: dev/uart.cc: dev/uart.hh: dev/uart8250.cc: dev/uart8250.hh: docs/stl.hh: encumbered/cpu/full/op_class.hh: kern/kernel_stats.cc: kern/kernel_stats.hh: kern/linux/linux.hh: kern/linux/linux_syscalls.cc: kern/linux/linux_syscalls.hh: kern/linux/linux_system.cc: kern/linux/linux_system.hh: kern/linux/linux_threadinfo.hh: kern/linux/printk.cc: kern/linux/printk.hh: kern/system_events.cc: kern/system_events.hh: kern/tru64/dump_mbuf.cc: kern/tru64/dump_mbuf.hh: kern/tru64/mbuf.hh: kern/tru64/printf.cc: kern/tru64/printf.hh: kern/tru64/tru64.hh: kern/tru64/tru64_events.cc: kern/tru64/tru64_events.hh: kern/tru64/tru64_syscalls.cc: kern/tru64/tru64_syscalls.hh: kern/tru64/tru64_system.cc: kern/tru64/tru64_system.hh: python/SConscript: python/m5/__init__.py: python/m5/config.py: python/m5/convert.py: python/m5/multidict.py: python/m5/smartdict.py: sim/async.hh: sim/builder.cc: sim/builder.hh: sim/debug.cc: sim/debug.hh: sim/eventq.cc: sim/eventq.hh: sim/host.hh: sim/main.cc: sim/param.cc: sim/param.hh: sim/process.cc: sim/process.hh: sim/root.cc: sim/serialize.cc: sim/serialize.hh: sim/sim_events.cc: sim/sim_events.hh: sim/sim_exit.hh: sim/sim_object.cc: sim/sim_object.hh: sim/startup.cc: sim/startup.hh: sim/stat_control.cc: sim/stat_control.hh: sim/stats.hh: sim/syscall_emul.cc: sim/syscall_emul.hh: sim/system.cc: sim/system.hh: test/bitvectest.cc: test/circletest.cc: test/cprintftest.cc: test/genini.py: test/initest.cc: test/lru_test.cc: test/nmtest.cc: test/offtest.cc: test/paramtest.cc: test/rangetest.cc: test/sized_test.cc: test/stattest.cc: test/strnumtest.cc: test/symtest.cc: test/tokentest.cc: test/tracetest.cc: util/ccdrv/devtime.c: util/m5/m5.c: util/oprofile-top.py: util/rundiff: util/m5/m5op.h: util/m5/m5op.s: util/stats/db.py: util/stats/dbinit.py: util/stats/display.py: util/stats/info.py: util/stats/print.py: util/stats/stats.py: util/tap/tap.cc: Update copyright dates and author list --HG-- extra : convert_revision : 0faba08fc0fc0146f1efb7f61e4b043c020ff9e4
2005-06-05Fix a few broken or inconsistently formatted copyrightsSteve Reinhardt
that the script doesn't deal with. Don't bother with copyright notices in generated files. LICENSE: Fix author list. arch/alpha/ev5.cc: arch/alpha/ev5.hh: Fix inconsistently formatted copyright. arch/isa_parser.py: base/traceflags.py: Fix copyright & author list. Don't bother with copyrights in generated files. dev/rtcreg.h: Fix broken copyright. --HG-- extra : convert_revision : d628e63c495960e2b129cef0aa8fddbdd4dabd45
2005-06-05Many files:Steve Reinhardt
Remove RCS Id string arch/alpha/alpha_linux_process.cc: arch/alpha/alpha_memory.cc: arch/alpha/alpha_memory.hh: arch/alpha/alpha_tru64_process.cc: arch/alpha/aout_machdep.h: arch/alpha/arguments.cc: arch/alpha/arguments.hh: arch/alpha/ecoff_machdep.h: arch/isa_parser.py: arch/alpha/ev5.cc: arch/alpha/ev5.hh: arch/alpha/faults.cc: arch/alpha/faults.hh: arch/alpha/isa_traits.hh: arch/alpha/osfpal.cc: arch/alpha/osfpal.hh: arch/alpha/pseudo_inst.cc: arch/alpha/pseudo_inst.hh: arch/alpha/vptr.hh: arch/alpha/vtophys.cc: arch/alpha/vtophys.hh: base/bitfield.hh: base/callback.hh: base/circlebuf.cc: base/circlebuf.hh: base/cprintf.cc: base/cprintf.hh: base/cprintf_formats.hh: base/crc.cc: base/crc.hh: base/date.cc: base/dbl_list.hh: base/endian.hh: base/fast_alloc.cc: base/fast_alloc.hh: base/fifo_buffer.cc: base/fifo_buffer.hh: base/hashmap.hh: base/hostinfo.cc: base/hostinfo.hh: base/hybrid_pred.cc: base/hybrid_pred.hh: base/inet.cc: base/inet.hh: base/inifile.cc: base/inifile.hh: base/intmath.cc: base/intmath.hh: base/kgdb.h: base/match.cc: base/match.hh: base/misc.cc: base/misc.hh: base/mod_num.hh: base/mysql.cc: base/mysql.hh: base/output.cc: base/output.hh: base/pollevent.cc: base/pollevent.hh: base/predictor.hh: base/random.cc: base/random.hh: base/range.cc: base/range.hh: base/refcnt.hh: base/remote_gdb.cc: base/remote_gdb.hh: base/res_list.hh: base/sat_counter.cc: base/sat_counter.hh: base/sched_list.hh: base/socket.cc: base/socket.hh: base/statistics.cc: base/statistics.hh: base/compression/lzss_compression.cc: base/compression/lzss_compression.hh: base/compression/null_compression.hh: base/loader/aout_object.cc: base/loader/aout_object.hh: base/loader/coff_sym.h: base/loader/coff_symconst.h: base/loader/ecoff_object.cc: base/loader/ecoff_object.hh: base/loader/elf_object.cc: base/loader/elf_object.hh: base/loader/exec_aout.h: base/loader/exec_ecoff.h: base/loader/symtab.cc: base/loader/symtab.hh: base/stats/events.cc: base/stats/events.hh: base/stats/flags.hh: base/stats/mysql.cc: base/stats/mysql.hh: base/stats/mysql_run.hh: base/stats/output.hh: base/stats/statdb.cc: base/stats/statdb.hh: base/stats/text.cc: base/stats/text.hh: base/stats/types.hh: base/stats/visit.cc: base/stats/visit.hh: base/str.cc: base/str.hh: base/time.cc: base/time.hh: base/timebuf.hh: base/trace.cc: base/trace.hh: base/traceflags.py: base/userinfo.cc: base/userinfo.hh: cpu/base.cc: cpu/base.hh: cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: cpu/exec_context.cc: cpu/exec_context.hh: cpu/exetrace.cc: cpu/exetrace.hh: cpu/inst_seq.hh: cpu/intr_control.cc: cpu/intr_control.hh: cpu/pc_event.cc: cpu/pc_event.hh: cpu/memtest/memtest.cc: cpu/memtest/memtest.hh: cpu/o3/2bit_local_pred.cc: cpu/o3/2bit_local_pred.hh: cpu/o3/alpha_cpu.cc: cpu/o3/alpha_cpu.hh: cpu/o3/alpha_cpu_builder.cc: cpu/o3/alpha_dyn_inst.cc: cpu/o3/alpha_dyn_inst.hh: cpu/o3/alpha_dyn_inst_impl.hh: cpu/o3/alpha_impl.hh: cpu/o3/alpha_params.hh: cpu/o3/bpred_unit.cc: cpu/o3/bpred_unit.hh: cpu/o3/bpred_unit_impl.hh: cpu/o3/btb.cc: cpu/o3/btb.hh: cpu/o3/comm.hh: cpu/o3/commit.cc: cpu/o3/commit.hh: cpu/o3/commit_impl.hh: cpu/o3/cpu.cc: cpu/o3/cpu.hh: cpu/o3/cpu_policy.hh: cpu/o3/decode.cc: cpu/o3/decode.hh: cpu/o3/decode_impl.hh: cpu/o3/fetch.cc: cpu/o3/fetch.hh: cpu/o3/fetch_impl.hh: cpu/o3/free_list.cc: cpu/o3/free_list.hh: cpu/o3/iew.cc: cpu/o3/iew.hh: cpu/o3/iew_impl.hh: cpu/o3/inst_queue.cc: cpu/o3/inst_queue.hh: cpu/o3/inst_queue_impl.hh: cpu/o3/mem_dep_unit.cc: cpu/o3/mem_dep_unit.hh: cpu/o3/mem_dep_unit_impl.hh: cpu/o3/ras.cc: cpu/o3/ras.hh: cpu/o3/regfile.hh: cpu/o3/rename.cc: cpu/o3/rename.hh: cpu/o3/rename_impl.hh: cpu/o3/rename_map.cc: cpu/o3/rename_map.hh: cpu/o3/rob.hh: cpu/o3/rob_impl.hh: cpu/o3/sat_counter.cc: cpu/o3/sat_counter.hh: cpu/o3/store_set.cc: cpu/o3/store_set.hh: cpu/o3/tournament_pred.cc: cpu/o3/tournament_pred.hh: cpu/ozone/cpu.hh: cpu/simple/cpu.cc: cpu/simple/cpu.hh: cpu/smt.hh: cpu/static_inst.cc: cpu/static_inst.hh: cpu/trace/opt_cpu.hh: cpu/trace/reader/ibm_reader.cc: cpu/trace/reader/ibm_reader.hh: cpu/trace/reader/itx_reader.cc: cpu/trace/reader/itx_reader.hh: cpu/trace/reader/m5_reader.cc: cpu/trace/reader/m5_reader.hh: cpu/trace/reader/mem_trace_reader.cc: cpu/trace/reader/mem_trace_reader.hh: cpu/trace/trace_cpu.cc: cpu/trace/trace_cpu.hh: dev/alpha_access.h: dev/alpha_console.cc: dev/alpha_console.hh: dev/baddev.cc: dev/baddev.hh: dev/disk_image.cc: dev/disk_image.hh: dev/etherbus.cc: dev/etherbus.hh: dev/etherdump.cc: dev/etherdump.hh: dev/etherint.cc: dev/etherint.hh: dev/etherlink.cc: dev/etherlink.hh: dev/etherpkt.cc: dev/etherpkt.hh: dev/ethertap.cc: dev/ethertap.hh: dev/ide_ctrl.cc: dev/ide_ctrl.hh: dev/ide_disk.cc: dev/ide_disk.hh: dev/io_device.cc: dev/io_device.hh: dev/ns_gige.cc: dev/ns_gige.hh: dev/ns_gige_reg.h: dev/pciconfigall.cc: dev/pciconfigall.hh: dev/pcidev.cc: dev/pcidev.hh: dev/pcireg.h: dev/pktfifo.cc: dev/pktfifo.hh: dev/platform.cc: dev/platform.hh: dev/simconsole.cc: dev/simconsole.hh: dev/simple_disk.cc: dev/simple_disk.hh: dev/sinic.cc: dev/sinic.hh: dev/sinicreg.hh: dev/tsunami.cc: dev/tsunami.hh: dev/tsunami_cchip.cc: dev/tsunami_cchip.hh: dev/tsunami_io.cc: dev/tsunami_io.hh: dev/tsunami_pchip.cc: dev/tsunami_pchip.hh: dev/uart.cc: dev/uart.hh: dev/uart8250.cc: dev/uart8250.hh: docs/stl.hh: encumbered/cpu/full/op_class.hh: kern/kernel_stats.cc: kern/kernel_stats.hh: kern/linux/linux.hh: kern/system_events.cc: kern/system_events.hh: kern/linux/linux_syscalls.cc: kern/linux/linux_syscalls.hh: kern/linux/linux_system.cc: kern/linux/linux_system.hh: kern/linux/printk.cc: kern/linux/printk.hh: kern/tru64/dump_mbuf.cc: kern/tru64/dump_mbuf.hh: kern/tru64/mbuf.hh: kern/tru64/printf.cc: kern/tru64/printf.hh: kern/tru64/tru64.hh: kern/tru64/tru64_events.cc: kern/tru64/tru64_events.hh: kern/tru64/tru64_syscalls.cc: kern/tru64/tru64_syscalls.hh: kern/tru64/tru64_system.cc: kern/tru64/tru64_system.hh: sim/async.hh: sim/builder.cc: sim/builder.hh: sim/debug.cc: sim/debug.hh: sim/eventq.cc: sim/eventq.hh: sim/host.hh: sim/main.cc: sim/param.cc: sim/param.hh: sim/root.cc: sim/serialize.cc: sim/serialize.hh: sim/sim_events.cc: sim/sim_events.hh: sim/sim_exit.hh: sim/sim_object.cc: sim/sim_object.hh: sim/startup.cc: sim/startup.hh: sim/stat_control.cc: sim/stat_control.hh: sim/stats.hh: sim/syscall_emul.cc: sim/syscall_emul.hh: sim/system.cc: sim/system.hh: test/Makefile: test/bitvectest.cc: test/circletest.cc: test/cprintftest.cc: test/initest.cc: test/lru_test.cc: test/nmtest.cc: test/offtest.cc: test/paramtest.cc: test/rangetest.cc: test/sized_test.cc: test/stattest.cc: test/strnumtest.cc: test/symtest.cc: test/tokentest.cc: test/tracetest.cc: util/m5/m5.c: util/m5/m5op.h: util/m5/m5op.s: util/tap/Makefile: util/tap/tap.cc: util/term/Makefile: util/term/term.c: Remove RCS Id string --HG-- extra : convert_revision : fc5b0a6ee2a213785bd58c51ce82eb2f769d6b88
2005-06-05added copyrightAli Saidi
kern/linux/sched.hh: kern/linux/thread_info.hh: got rid of everything but exactly what we needed util/categories.py: newest version from one of my repositories --HG-- extra : convert_revision : c4328e5938d421d60493c0da07022bfa9e92c404
2005-06-05Change SamplingCPU to Sampler.Steve Reinhardt
--HG-- extra : convert_revision : ddba327a572804954adcebfff1182b97d474c020
2005-06-04shuffle files around for new directory structureNathan Binkert
--HG-- rename : cpu/base_cpu.cc => cpu/base.cc rename : cpu/base_cpu.hh => cpu/base.hh rename : cpu/beta_cpu/2bit_local_pred.cc => cpu/o3/2bit_local_pred.cc rename : cpu/beta_cpu/2bit_local_pred.hh => cpu/o3/2bit_local_pred.hh rename : cpu/beta_cpu/alpha_full_cpu.cc => cpu/o3/alpha_cpu.cc rename : cpu/beta_cpu/alpha_full_cpu.hh => cpu/o3/alpha_cpu.hh rename : cpu/beta_cpu/alpha_full_cpu_builder.cc => cpu/o3/alpha_cpu_builder.cc rename : cpu/beta_cpu/alpha_full_cpu_impl.hh => cpu/o3/alpha_cpu_impl.hh rename : cpu/beta_cpu/alpha_dyn_inst.cc => cpu/o3/alpha_dyn_inst.cc rename : cpu/beta_cpu/alpha_dyn_inst.hh => cpu/o3/alpha_dyn_inst.hh rename : cpu/beta_cpu/alpha_dyn_inst_impl.hh => cpu/o3/alpha_dyn_inst_impl.hh rename : cpu/beta_cpu/alpha_impl.hh => cpu/o3/alpha_impl.hh rename : cpu/beta_cpu/alpha_params.hh => cpu/o3/alpha_params.hh rename : cpu/beta_cpu/bpred_unit.cc => cpu/o3/bpred_unit.cc rename : cpu/beta_cpu/bpred_unit.hh => cpu/o3/bpred_unit.hh rename : cpu/beta_cpu/bpred_unit_impl.hh => cpu/o3/bpred_unit_impl.hh rename : cpu/beta_cpu/btb.cc => cpu/o3/btb.cc rename : cpu/beta_cpu/btb.hh => cpu/o3/btb.hh rename : cpu/beta_cpu/comm.hh => cpu/o3/comm.hh rename : cpu/beta_cpu/commit.cc => cpu/o3/commit.cc rename : cpu/beta_cpu/commit.hh => cpu/o3/commit.hh rename : cpu/beta_cpu/commit_impl.hh => cpu/o3/commit_impl.hh rename : cpu/beta_cpu/full_cpu.cc => cpu/o3/cpu.cc rename : cpu/beta_cpu/full_cpu.hh => cpu/o3/cpu.hh rename : cpu/beta_cpu/cpu_policy.hh => cpu/o3/cpu_policy.hh rename : cpu/beta_cpu/decode.cc => cpu/o3/decode.cc rename : cpu/beta_cpu/decode.hh => cpu/o3/decode.hh rename : cpu/beta_cpu/decode_impl.hh => cpu/o3/decode_impl.hh rename : cpu/beta_cpu/fetch.cc => cpu/o3/fetch.cc rename : cpu/beta_cpu/fetch.hh => cpu/o3/fetch.hh rename : cpu/beta_cpu/fetch_impl.hh => cpu/o3/fetch_impl.hh rename : cpu/beta_cpu/free_list.cc => cpu/o3/free_list.cc rename : cpu/beta_cpu/free_list.hh => cpu/o3/free_list.hh rename : cpu/beta_cpu/iew.cc => cpu/o3/iew.cc rename : cpu/beta_cpu/iew.hh => cpu/o3/iew.hh rename : cpu/beta_cpu/iew_impl.hh => cpu/o3/iew_impl.hh rename : cpu/beta_cpu/inst_queue.cc => cpu/o3/inst_queue.cc rename : cpu/beta_cpu/inst_queue.hh => cpu/o3/inst_queue.hh rename : cpu/beta_cpu/inst_queue_impl.hh => cpu/o3/inst_queue_impl.hh rename : cpu/beta_cpu/mem_dep_unit.cc => cpu/o3/mem_dep_unit.cc rename : cpu/beta_cpu/mem_dep_unit.hh => cpu/o3/mem_dep_unit.hh rename : cpu/beta_cpu/mem_dep_unit_impl.hh => cpu/o3/mem_dep_unit_impl.hh rename : cpu/beta_cpu/ras.cc => cpu/o3/ras.cc rename : cpu/beta_cpu/ras.hh => cpu/o3/ras.hh rename : cpu/beta_cpu/regfile.hh => cpu/o3/regfile.hh rename : cpu/beta_cpu/rename.cc => cpu/o3/rename.cc rename : cpu/beta_cpu/rename.hh => cpu/o3/rename.hh rename : cpu/beta_cpu/rename_impl.hh => cpu/o3/rename_impl.hh rename : cpu/beta_cpu/rename_map.cc => cpu/o3/rename_map.cc rename : cpu/beta_cpu/rename_map.hh => cpu/o3/rename_map.hh rename : cpu/beta_cpu/rob.cc => cpu/o3/rob.cc rename : cpu/beta_cpu/rob.hh => cpu/o3/rob.hh rename : cpu/beta_cpu/rob_impl.hh => cpu/o3/rob_impl.hh rename : cpu/beta_cpu/sat_counter.cc => cpu/o3/sat_counter.cc rename : cpu/beta_cpu/sat_counter.hh => cpu/o3/sat_counter.hh rename : cpu/beta_cpu/store_set.cc => cpu/o3/store_set.cc rename : cpu/beta_cpu/store_set.hh => cpu/o3/store_set.hh rename : cpu/beta_cpu/tournament_pred.cc => cpu/o3/tournament_pred.cc rename : cpu/beta_cpu/tournament_pred.hh => cpu/o3/tournament_pred.hh rename : cpu/ooo_cpu/ooo_cpu.cc => cpu/ozone/cpu.cc rename : cpu/ooo_cpu/ooo_cpu.hh => cpu/ozone/cpu.hh rename : cpu/ooo_cpu/ooo_impl.hh => cpu/ozone/cpu_impl.hh rename : cpu/ooo_cpu/ea_list.cc => cpu/ozone/ea_list.cc rename : cpu/ooo_cpu/ea_list.hh => cpu/ozone/ea_list.hh rename : cpu/simple_cpu/simple_cpu.cc => cpu/simple/cpu.cc rename : cpu/simple_cpu/simple_cpu.hh => cpu/simple/cpu.hh rename : cpu/full_cpu/smt.hh => cpu/smt.hh rename : cpu/full_cpu/op_class.hh => encumbered/cpu/full/op_class.hh extra : convert_revision : c4a891d8d6d3e0e9e5ea56be47d851da44d8c032
2005-06-04Remove the inorder CPUNathan Binkert
--HG-- extra : convert_revision : 626aad449df9370383becb8e14f4cbf406b5b376
2005-06-04more portableNathan Binkert
arch/alpha/alpha_tru64_process.cc: Sort #includes Make code more portable. g++ doesn't seem to always like struct ::stat (and others). So, we typedef stat outside of the namespace as something else and use the typedef base/hostinfo.cc: use snprintf to quell warning base/inifile.cc: use strncpy to quell warning base/stats/events.cc: don't use strcpy cpu/beta_cpu/btb.cc: use FloorLog2 instead of log2 cpu/beta_cpu/comm.hh: cpu/beta_cpu/inst_queue.hh: cpu/beta_cpu/sat_counter.hh: use sim/host.hh instead of stdint.h --HG-- extra : convert_revision : 59bd9235dda74e72a8b6a70b3f3a981840384f3f
2005-06-03Additions/fixes for Tru64 syscall emulation.Steve Reinhardt
We can now run the SimpleScalar wupwise binary to completion on the test input. Didn't have time to do more testing, but I fixed a major problem w/getdirentries that should help a lot more programs run. arch/alpha/alpha_tru64_process.cc: Add truncate, ftruncate, statfs, and fstatfs. Add v4.x (pre-F64) stat, fstat, and lstat. Add setsysinfo (though all it does is provide more specific warning messages). Fix subtle but major bug in getdirentries. sim/syscall_emul.cc: sim/syscall_emul.hh: Add truncate, ftruncate, statfs, and fstatfs. --HG-- extra : convert_revision : 9037393d00dc49b0074a41603ea647587f5a9ec7
2005-06-01Rename sim/universe.{cc,hh} to root.{cc,hh} (since theSteve Reinhardt
object defined there was renamed Root long ago). SConscript: arch/alpha/alpha_linux_process.cc: arch/alpha/alpha_tru64_process.cc: base/misc.cc: base/pollevent.cc: base/pollevent.hh: base/stats/events.cc: base/trace.hh: cpu/beta_cpu/fetch_impl.hh: cpu/beta_cpu/full_cpu.cc: cpu/beta_cpu/inst_queue_impl.hh: cpu/pc_event.cc: cpu/static_inst.cc: dev/etherbus.cc: dev/etherdump.cc: dev/etherlink.cc: dev/ide_disk.cc: dev/pcidev.cc: sim/builder.cc: sim/eventq.cc: sim/main.cc: sim/root.cc: sim/stat_control.cc: Rename sim/universe.{cc,hh} to root.{cc,hh}. --HG-- rename : sim/universe.cc => sim/root.cc extra : convert_revision : b8699e81e285253d66da75412e7bb2c251c0389a
2005-05-03Large update of several parts of my code. The most notable change is the ↵Kevin Lim
inclusion of a full-fledged load/store queue. At the moment it still has some issues running, but most of the code is hopefully close to the final version. SConscript: arch/isa_parser.py: cpu/base_dyn_inst.cc: Remove OOO CPU stuff. arch/alpha/faults.hh: Add fake memory fault. This will be removed eventually. arch/alpha/isa_desc: Change EA comp and Mem accessor to be const StaticInstPtrs. cpu/base_dyn_inst.hh: Update read/write calls to use load queue and store queue indices. cpu/beta_cpu/alpha_dyn_inst.hh: Change to const StaticInst in the register accessors. cpu/beta_cpu/alpha_dyn_inst_impl.hh: Update syscall code with thread numbers. cpu/beta_cpu/alpha_full_cpu.hh: Alter some of the full system code so it will compile without errors. cpu/beta_cpu/alpha_full_cpu_builder.cc: Created a DerivAlphaFullCPU class so I can instantiate different CPUs that have different template parameters. cpu/beta_cpu/alpha_full_cpu_impl.hh: Update some of the full system code so it compiles. cpu/beta_cpu/alpha_params.hh: cpu/beta_cpu/fetch_impl.hh: Remove asid. cpu/beta_cpu/comm.hh: Remove global history field. cpu/beta_cpu/commit.hh: Comment out rename map. cpu/beta_cpu/commit_impl.hh: Update some of the full system code so it compiles. Also change it so that it handles memory instructions properly. cpu/beta_cpu/cpu_policy.hh: Removed IQ from the IEW template parameter to make it more uniform. cpu/beta_cpu/decode.hh: Add debug function. cpu/beta_cpu/decode_impl.hh: Slight updates for decode in the case where it causes a squash. cpu/beta_cpu/fetch.hh: cpu/beta_cpu/rob.hh: Comment out unneccessary code. cpu/beta_cpu/full_cpu.cc: Changed some of the full system code so it compiles. Updated exec contexts and so forth to hopefully make multithreading easier. cpu/beta_cpu/full_cpu.hh: Updated some of the full system code to make it compile. cpu/beta_cpu/iew.cc: Removed IQ from template parameter to IEW. cpu/beta_cpu/iew.hh: Removed IQ from template parameter to IEW. Updated IEW to recognize the Load/Store queue. cpu/beta_cpu/iew_impl.hh: New handling of memory instructions through the Load/Store queue. cpu/beta_cpu/inst_queue.hh: Updated comment. cpu/beta_cpu/inst_queue_impl.hh: Slightly different handling of memory instructions due to Load/Store queue. cpu/beta_cpu/regfile.hh: Updated full system code so it compiles. cpu/beta_cpu/rob_impl.hh: Moved some code around; no major functional changes. cpu/ooo_cpu/ooo_cpu.hh: Slight updates to OOO CPU; still does not work. cpu/static_inst.hh: Remove OOO CPU stuff. Change ea comp and mem acc to return const StaticInst. kern/kernel_stats.hh: Extra forward declares added due to compile error. --HG-- extra : convert_revision : 594a7cdbe57f6c2bda7d08856fcd864604a6238e
2005-05-02Merge ktlim@zizzer.eecs.umich.edu:/bk/m5Kevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/m5 --HG-- extra : convert_revision : ac0788599c365b2d7fe0870f0fea4b62c3b3ef22
2005-04-22Make code more portable and port to cygwinNathan Binkert
arch/alpha/alpha_tru64_process.cc: getdirent isn't implemented by cygwin. panic if this function is executed. (It shouldn't be too much to emulate it using opendir, readdir, etc.) arch/alpha/pseudo_inst.cc: Use lseek once and read instead pread. base/intmath.hh: we want int, long, and long long variations of FloorLog2 instead of int32_t, int64_t. Otherwise, we leave one out. base/socket.cc: Fix define that seems to be for apple sim/serialize.cc: don't use the intXX_t stuff, instead, use the real types so we're sure that we cover all of them. --HG-- extra : convert_revision : 9fccaff583100b06bbaafd95a162c4e19beed59e
2005-04-14Merge ktlim@zizzer.eecs.umich.edu:/bk/m5Kevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/m5 --HG-- extra : convert_revision : 0baadd8d68bfa6f8e96307eb2d4426b0d9e0b8b4
2005-04-11Make the notion of a global event tick independent of the actualNathan Binkert
CPU cycle ticks. This allows the user to have CPUs of different frequencies, and also allows frequencies and latencies that are not evenly divisible by the CPU frequency. For now, the CPU frequency is still set to the global frequency, but soon, we'll hopefully make the global frequency fixed at something like 1THz and set all other frequencies independently. arch/alpha/ev5.cc: The cycles counter is based on the current cpu cycle. cpu/base_cpu.cc: frequency isn't the cpu parameter anymore, cycleTime is. cpu/base_cpu.hh: frequency isn't the cpu parameter anymore, cycleTime is. create several public functions for getting the cpu frequency and the numbers of ticks for a given number of cycles, etc. cpu/memtest/memtest.cc: cpu/simple_cpu/simple_cpu.cc: cpu/simple_cpu/simple_cpu.hh: cpu/trace/trace_cpu.cc: Now that ticks aren't cpu cycles, fixup code to advance by the proper number of ticks. cpu/memtest/memtest.hh: cpu/trace/trace_cpu.hh: Provide a function to get the number of ticks for a given number of cycles. dev/alpha_console.cc: Update for changes in the way that frequencies and latencies are accessed. Move some stuff to init() dev/alpha_console.hh: Need a pointer to the system and the cpu to get the frequency so we can pass the info to the console code. dev/etherbus.cc: dev/etherbus.hh: dev/etherlink.cc: dev/etherlink.hh: dev/ethertap.cc: dev/ide_disk.hh: dev/ns_gige.cc: dev/ns_gige.hh: update for changes in the way bandwidths are passed from python to C++ to accomidate the new way that ticks works. dev/ide_disk.cc: update for changes in the way bandwidths are passed from python to C++ to accomidate the new way that ticks works. Add some extra debugging printfs dev/platform.cc: dev/sinic.cc: dev/sinic.hh: outline the constructor and destructor dev/platform.hh: outline the constructor and destructor. don't keep track of the interrupt frequency. Only provide the accessor function. dev/tsunami.cc: dev/tsunami.hh: outline the constructor and destructor Don't set the interrupt frequency here. Get it from the actual device that does the interrupting. dev/tsunami_io.cc: dev/tsunami_io.hh: Make the interrupt interval a configuration parameter. (And convert the interval to the new latency/frequency stuff in the python) kern/linux/linux_system.cc: update for changes in the way bandwidths are passed from python to C++ to accomidate the new way that ticks works. For now, we must get the boot cpu's frequency as a parameter since allowing the system to have a pointer to the boot cpu would cause a cycle. kern/tru64/tru64_system.cc: For now, we must get the boot cpu's frequency as a parameter since allowing the system to have a pointer to the boot cpu would cause a cycle. python/m5/config.py: Fix support for cycle_time relative latencies and frequencies. Add support for getting a NetworkBandwidth or a MemoryBandwidth. python/m5/objects/BaseCPU.mpy: All CPUs now have a cycle_time. The default is the global frequency, but it is now possible to set the global frequency to some large value (like 1THz) and set each CPU frequency independently. python/m5/objects/BaseCache.mpy: python/m5/objects/Ide.mpy: Make this a Latency parameter python/m5/objects/BaseSystem.mpy: We need to pass the boot CPU's frequency to the system python/m5/objects/Ethernet.mpy: Update parameter types to use latency and bandwidth types python/m5/objects/Platform.mpy: this frequency isn't needed. We get it from the clock interrupt. python/m5/objects/Tsunami.mpy: The clock generator should hold the frequency sim/eventq.hh: Need to remove this assertion because the writeback event queue is different from the CPU's event queue which can cause this assertion to fail. sim/process.cc: Fix comment. sim/system.hh: Struct member to hold the boot CPU's frequency. sim/universe.cc: remove unneeded variable. --HG-- extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
2005-04-07Hand mergeKevin Lim
base/traceflags.py: Include new flags --HG-- extra : convert_revision : 8017cbe256860dce8b1efc1b4e1e81e883895b90
2005-03-29expose variables for number of global events per simulated second,Nathan Binkert
millisecond, microsecond, etc. so that the user can explicitly convert between system ticks and time and know what sorts of expensive operations are being used for that conversion. arch/alpha/alpha_tru64_process.cc: arch/alpha/pseudo_inst.cc: dev/etherdump.cc: dev/etherlink.cc: dev/ns_gige.cc: dev/sinic.cc: dev/tsunami_io.cc: dev/uart.cc: sim/stat_control.cc: sim/syscall_emul.hh: Use the new variables for getting the event clock dev/etherdump.hh: delete variables that are no longer needed. --HG-- extra : convert_revision : d95fc7d44909443e1b7952a24ef822ef051c7cf2
2005-03-18Merge ktlim@zizzer.eecs.umich.edu:/bk/m5Kevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/m5 --HG-- extra : convert_revision : cbf8da2fe5c4155d9ed8318597d543ff105449d3
2005-03-16Merge zizzer:/z/m5/Bitkeeper/m5Ron Dreslinski
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/timing_L1 --HG-- extra : convert_revision : 848757d0f18cfb33620cfa4b084a9b102b2744c0
2005-03-16Fix the bad addr check to check for allowable addresses in the nxm address spaceRon Dreslinski
arch/alpha/alpha_tru64_process.cc: sim/process.cc: sim/process.hh: Add an address range for the nxm sim/syscall_emul.hh: Check to make sure that if we have an nxm config space that the mmap hasn't grown into it --HG-- extra : convert_revision : e479e5240080ae488080d228bafea488835d6e77
2005-03-14Merge ktlim@zizzer.eecs.umich.edu:/bk/m5Kevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/m5 --HG-- extra : convert_revision : ba27a3ba99b567f5a8a41d9cd3a09d38c820ed89
2005-03-14g++ 3.4 fixes.Kevin Lim
arch/alpha/alpha_tru64_process.cc: g++ 3.4 fixes. Must cast to an int prior to returning value. --HG-- extra : convert_revision : d8ccfd7aa7ca00d9bc2d76cff014b9f142d10640
2005-03-10Merge ktlim@zizzer.eecs.umich.edu:/bk/m5Kevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/m5 --HG-- extra : convert_revision : a58535776cf5a3d17f8d9f65144cdf8db54289aa
2005-03-10Removed unecessary constructor call at each return.Ali Saidi
arch/alpha/isa_traits.hh: updated copyright date --HG-- extra : convert_revision : 30c5fc0eb94138ebd4ee047ebdbff5121f95e5f1
2005-03-10fix typo in SyscallReturn ObjectAli Saidi
--HG-- extra : convert_revision : 97d34a02a29a9ac3e2256d92194e3a46b9e8021e
2005-03-09Changed all syscalls to use syscall return object.Ali Saidi
arch/alpha/alpha_linux_process.cc: arch/alpha/alpha_tru64_process.cc: cpu/exec_context.hh: sim/process.hh: sim/syscall_emul.cc: sim/syscall_emul.hh: Changed all syscalls to use syscall return object arch/alpha/isa_traits.hh: Added syscall return object that packages return value and return status into an object. sim/process.cc: renamed variable name to nm so base class function name() can be called --HG-- extra : convert_revision : 6609c5ffecc9e3519d7a0cd160879fd21d54abfc
2005-03-08Hand-merge static_inst.hh. These execute functions are within an external ↵Kevin Lim
file in the new CPU case. cpu/static_inst.hh: Hand-merge. These execute functions are within an external file in the new CPU case. --HG-- extra : convert_revision : a34112f471fa31bdd5bb53552ddd704b9571c110
2005-03-01Two fixes to try and get TLB miss cost more in line with real platform:Steve Reinhardt
1) Add fault_handler_delay param to FullCPU to wait N cycles after committing faulting instruction before fetching fault handler. 2) Make hw_rei a serializing instruction (flushes pipe, basically). arch/alpha/isa_desc: Make hw_rei a serializing instruction (guarantees previous insts complete before hw_rei will issue). --HG-- extra : convert_revision : 704cef65b3869be9eee724055cedb22114a78359
2005-03-01Add a new operation class for IPR accesses, and have IPR-accessingSteve Reinhardt
instructions use it (instead of IntALU, as before). Default config has a single non-pipelined 3-cycle unit. A bit conservative for the ev6 (some are 1, some are 3). arch/alpha/isa_desc: Make hw_mfpr and hw_mtpr use IprAccessOp op class. cpu/full_cpu/op_class.hh: Add IprAccess. --HG-- extra : convert_revision : d4103da3343a586936839e29981fd15d6930d442
2005-02-25Make all StaticInst methods const. StaticInst objects represent aSteve Reinhardt
particular binary machine instruction and should be immutable after they are constructed. cpu/simple_cpu/simple_cpu.hh: Make StaticInst parameters const. --HG-- extra : convert_revision : e535fa10c842ce173336323f39d9108c1847f8ba
2005-02-25Merge ktlim@zizzer.eecs.umich.edu:/bk/m5Kevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/m5 --HG-- extra : convert_revision : ba556bbc93275fcd920a0529383fd480bb7218de
2005-02-25Initial light-weight OoO CPU checkin, along with gcc-3.4 fixes.Kevin Lim
SConscript: Include new files. arch/alpha/isa_desc: Make the eaCompPtr and memAccPtr non-const so that execute() can be called on them. arch/alpha/isa_traits.hh: Add enum for total number of data registers. arch/isa_parser.py: base/traceflags.py: Include new light-weight OoO CPU model. cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: Changes to abstract more away from the base dyn inst class. cpu/beta_cpu/2bit_local_pred.cc: cpu/beta_cpu/2bit_local_pred.hh: cpu/beta_cpu/tournament_pred.cc: cpu/beta_cpu/tournament_pred.hh: Remove redundant SatCounter class. cpu/beta_cpu/alpha_dyn_inst.cc: cpu/beta_cpu/alpha_full_cpu.cc: cpu/beta_cpu/alpha_full_cpu.hh: cpu/beta_cpu/bpred_unit.cc: cpu/beta_cpu/inst_queue.cc: cpu/beta_cpu/mem_dep_unit.cc: cpu/beta_cpu/ras.cc: cpu/beta_cpu/rename_map.cc: cpu/beta_cpu/rename_map.hh: cpu/beta_cpu/rob.cc: Fix for gcc-3.4 cpu/beta_cpu/alpha_dyn_inst.hh: cpu/beta_cpu/alpha_dyn_inst_impl.hh: Fixes for gcc-3.4. Include more variables and functions that are specific to AlphaDynInst which were once in BaseDynInst. cpu/beta_cpu/alpha_full_cpu_builder.cc: Make params match the current params inherited from BaseCPU. cpu/beta_cpu/alpha_full_cpu_impl.hh: Fixes for gcc-3.4 cpu/beta_cpu/full_cpu.cc: Use new params pointer in BaseCPU. Fix for gcc-3.4. cpu/beta_cpu/full_cpu.hh: Use new params class from BaseCPU. cpu/beta_cpu/iew_impl.hh: Remove unused function. cpu/simple_cpu/simple_cpu.cc: Remove unused global variable. cpu/static_inst.hh: Include OoODynInst for new lightweight OoO CPU --HG-- extra : convert_revision : 34d9f2e64ca0313377391e0d059bf09c040286fa
2005-02-25Fix timing modeling of faults: functionally the very next instruction afterSteve Reinhardt
a faulting instruction is the fault handler, which appears as an independent instruction to the timing model. New code will stall fetch and not fetch the fault handler as long as there's a faulting instruction in the pipeline (i.e., the faulting inst has to commit first). Also fix Ali's bad-address assertion that doesn't apply to full system. Added some more debugging support in the process. Hopefully we'll move to the new cpu model soon and we won't need it anymore. arch/alpha/alpha_memory.cc: Reorganize lookup() so we can trace the result of the lookup as well. arch/alpha/isa_traits.hh: Add NoopMachInst (so we can insert them in the pipeline on ifetch faults). base/traceflags.py: Replace "Dispatch" flag with "Pipeline" (since I added similar DPRINTFs in other pipe stages). cpu/exetrace.cc: Change default for printing mis-speculated instructions to true (since that's often what we want, and right now you can't change it from the command line...). --HG-- extra : convert_revision : a29a98a373076d62bbbb1d6f40ba51ecae436dbc
2005-02-22Merge ktlim@zizzer.eecs.umich.edu:/bk/m5Kevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/m5 --HG-- extra : convert_revision : 8a558785c64b7c33e64523d3d887ea6e760c3d2b
2005-02-13build mysql version if libraries existAli Saidi
add dprintf on alignment faults fix RR benchmark rcS script name Add Dual test without rcS script Update Monet to be closer to the real thing Fix p4/monet configs Add a way to read the DRIR register with at 32bit access for validation SConscript: build/SConstruct: always use mysql if the libraries are installed arch/alpha/alpha_memory.cc: Add a DPRINTF to print alignment faults when they happen dev/tsunami_cchip.cc: Add a way to read the DRIR for validation. --HG-- extra : convert_revision : 8c112c958f36b785390c46e70a889a79c6bea015
2005-02-04Hand mergeKevin Lim
--HG-- extra : convert_revision : 86c7399b79c17558041a73056745227f70fe8b3b
2005-02-03Add support for CPU models to execute the effectiveSteve Reinhardt
address calculation and memory access portions separately. Not currently used by any CPU models, but Kevin says he needs this. Also clean up handling of execution tracing for memory accesses (move it all into isa_desc and out of CPU models). Got rid of some ancient unused code too. arch/alpha/isa_desc: Add execute() methods to EAComp and MemAcc portions of memory access instructions, to allow CPU models to execute the effective address calculation and memory access portions separately. Requires the execution context to remember the effective address across the two invocations. Added setEA() and getEA() methods to execution context to support this. A model that does not use the split execution model can panic if these methods are called. Also added hook to call traceData->setAddr() after EA computation on any load or store operation. arch/isa_parser.py: Call traceData->setData() on memory writes (stores). cpu/simple_cpu/simple_cpu.cc: Get rid of unused code. cpu/simple_cpu/simple_cpu.hh: Add (non-functional) setEA() and getEA() methods for new split memory access execution support. --HG-- extra : convert_revision : bc2d2c758c4ca753812b9fa81f21038e55929ff0
2005-01-21Merge zizzer.eecs.umich.edu:/bk/m5Kevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/m5-patched/m5-new --HG-- extra : convert_revision : e802c800a478c297d3aa780a9ea3c6701453d91d
2005-01-21Add a couple statistics contexts.Nathan Binkert
arch/alpha/pseudo_inst.cc: rename the context for consistency. sim/pyconfig/m5config.py: Add a ParamContext class so that param contexts work with the new config stuff. --HG-- extra : convert_revision : 3a6b583a25c86237baca7a2b4eccc9d12f86a384
2005-01-14Fixes so m5 compiles on gcc 3.4, which has much stricter syntax. Most ↵Kevin Lim
changes come from templated code, which is evaluated slightly differently than in previous versions of gcc. arch/alpha/alpha_linux_process.cc: Alphabetize includes. arch/alpha/vptr.hh: Change the constants that are being used for alpha pagebytes to come from the ISA. base/random.hh: cpu/static_inst.cc: sim/param.cc: Fix up template syntax. base/range.hh: Include iostream for << operator. base/res_list.hh: base/statistics.hh: cpu/simple_cpu/simple_cpu.hh: cpu/static_inst.hh: sim/eventq.hh: sim/param.hh: Fixup for templated code to resolve different scope lookup in gcc 3.4. This defers the lookup of the function/variable until actual instantiation time by making it dependent on the templated class/function. base/trace.cc: Fix call to new. base/trace.hh: Fix up #define to have full path. cpu/base_cpu.cc: Fix up call to new. dev/etherlink.hh: dev/ns_gige.hh: dev/sinic.hh: Fixup for friend class/function declaration. g++ 3.4 no longer allows typedefs to be declared as a friend class. dev/pcidev.hh: Fix up re-definition of access level to params. kern/linux/linux_syscalls.hh: kern/tru64/tru64_syscalls.hh: Fix up header. Fix up template syntax. sim/serialize.cc: Include errno.h. sim/startup.cc: Change startupq. queue was getting destructed before all things had called ~StartupCallback(), which lead to a segfault. This puts startupq in global space, and we allocate it ourselves. Other code may be similar to this and may need changing in the future. sim/syscall_emul.hh: Include cpu/exec_context.hh and sim/process.hh, as forward declarations are no longer sufficient. sim/universe.cc: Include errno.h --HG-- extra : convert_revision : e49d08ee89eb06a28351f02bafc028ca6652d5af
2005-01-11Merge changes.Kevin Lim
base/traceflags.py: Merge extra new CPU flags cpu/static_inst.hh: Include all the execute functions in static_inst_impl.hh --HG-- extra : convert_revision : 78eb753bf709d37400e7c2418bb35d842d7c3f63
2004-11-13Macros are nasty, so let's get rid of them. Convert allNathan Binkert
all macros in ev5.hh to inline functions or constant typed variables and make them follow our style while we're at it. All of the stuff in this file actually belongs in the ISA traits code, but this is a first step at getting things done in the right manner. arch/alpha/alpha_memory.cc: arch/alpha/alpha_memory.hh: arch/alpha/ev5.cc: arch/alpha/isa_desc: dev/ns_gige.cc: kern/tru64/tru64_events.cc: deal with changes in ev5.hh arch/alpha/ev5.hh: Macros are nasty, so let's get rid of them. Convert all all macros to inline functions or constant typed variables. Make them follow our style while we're at it. All of the stuff in this file actually belongs in the ISA traits code, but this is a first step at getting things done in the right manner. arch/alpha/isa_traits.hh: move some of the ev5 specific code into the isa arch/alpha/vtophys.cc: base/remote_gdb.cc: deal with isa addition cpu/exec_context.hh: be less isa specific and use the isa traits to figure out what we can. dev/alpha_console.cc: dev/pciconfigall.cc: dev/tsunami_cchip.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: dev/uart.cc: deal with changes in ev5.hh I don't believe this masking is actually necessary. We should look at removing it later. dev/ide_ctrl.cc: sort #includes deal with changes in ev5.hh --HG-- extra : convert_revision : c8a3adf0a4b1d198aefe38fc38b295abf289b08a
2004-11-13defining SYSTEM_EV5 isn't all that necessaryNathan Binkert
--HG-- extra : convert_revision : 2ed4866db9483820d550bad00fdbc8dd027f95ba