summaryrefslogtreecommitdiff
path: root/arch
AgeCommit message (Collapse)Author
2006-03-03Merge zizzer:/bk/m5Ali Saidi
into zeep.eecs.umich.edu:/z/saidi/work/m5.head --HG-- extra : convert_revision : 8f463682e32a457cd9171c63dcec5209cb850b56
2006-03-03First cut at moving alpha specefic stuff out of /sim/system* intoAli Saidi
arch/alpha/system*. SConscript: dev/alpha_console.cc: dev/alpha_console.hh: kern/freebsd/freebsd_system.cc: kern/freebsd/freebsd_system.hh: kern/kernel_stats.cc: kern/linux/linux_system.cc: kern/linux/linux_system.hh: kern/tru64/tru64_system.cc: kern/tru64/tru64_system.hh: sim/pseudo_inst.cc: sim/system.cc: sim/system.hh: First cut at moving alpha specefic stuff out of /sim/system* --HG-- extra : convert_revision : eba58f537fc04e605af4fc216e184b074a44c8a0
2006-03-01Merge zizzer:/bk/m5Ali Saidi
into zeep.eecs.umich.edu:/z/saidi/work/m5.q --HG-- extra : convert_revision : 4855ecfb3de652456a8be413c9e538c91709dcb6
2006-02-28Add quiesceNs, quiesceTime, quiesceCycles, and m5panic pseudo ops.Ali Saidi
This changeset removes a check that prevents quiescing when an interrupt is pending. *** You should only call quiesce if that isn't a problem. *** arch/alpha/isa/decoder.isa: sim/pseudo_inst.cc: sim/pseudo_inst.hh: Add quiesceNs, quiesceCycles, quisceTime and m5panic pseudo ops. These quiesce for a number of ns, cycles, report how long we were quiesced for, and panic the simulator respectively. The latter is added to the panic() function in the console and linux kernel instead of executing an infinite loop until someone notices. cpu/exec_context.cc: cpu/exec_context.hh: Add a quiesce end event to the execution contexted which upon executing wakes up a CPU for quiesceCycles/quiesceNs. util/m5/Makefile: Make the makefile more reasonable util/m5/m5.c: update the m5op executable to use the files from the linux tree util/m5/m5op.S: update m5op.S from linux tree util/m5/m5op.h: update m5op.h from linux tree --HG-- rename : util/m5/m5op.s => util/m5/m5op.S extra : convert_revision : 3be18525e811405b112e33f24a8c4e772d15462d
2006-02-28Merge ktlim@zizzer:/bk/m5Kevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/m5-clean arch/alpha/ev5.cc: cpu/o3/regfile.hh: Hand merge. --HG-- rename : arch/alpha/alpha_memory.cc => arch/alpha/tlb.cc extra : convert_revision : c941dd2198851398820b38a66471372ed8454891
2006-02-28Merge gblack@m5.eecs.umich.edu:/bk/multiarchGabe Black
into ewok.(none):/home/gblack/m5/multiarch --HG-- extra : convert_revision : 0b3ffc0605c9043d7f5bf6c15f4a3c68846a732a
2006-02-28Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5Gabe Black
into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch --HG-- extra : convert_revision : 3a3ff8fcf472db385219a00ae434d1f3fea43b18
2006-02-28Cleaned up and slightly reorganized the Fault class heirarchy.Gabe Black
arch/alpha/ev5.cc: Changed c style casts of Faults to dynamic_casts arch/alpha/faults.cc: AlphaFault is now an abstract class. arch/alpha/faults.hh: AlphaFault is now an abstract class. Also, AlphaMachineCheckFault and AlphaAlignmentFault multiply inherit from both AlphaFault and from MachineCheckFault and AlignmentFault respectively. These classes get their name from the generic classes. cpu/o3/alpha_cpu_impl.hh: Changed a c style cast to a dynamic_cast for a Fault sim/faults.hh: All generic Fault classes are now abstract. Also, MachineCheckFault and AlignmentFault inherit FaultBase as a virtual base class to help resolve ambiguities when they are multiply inherited in ISA specific classes. The override the isMachineCheckFault and isAlignmentFault functions appropriately, and provide a standard name for these faults. --HG-- extra : convert_revision : 2cb906708e3eaec4a12587484c09e50ed6ef88fc
2006-02-27Changed ev5_trap from a function of the execution context to a function of ↵Gabe Black
the fault. The actual function still resides in the execution context. --HG-- extra : convert_revision : 56e33536cdd9079ace03896b85ea3c84b6eb4e57
2006-02-27Moved the _stat for MachineCheckFault and AlignmentFault into the isa ↵Gabe Black
specific classes to prevent instantiation of the generic classes. --HG-- extra : convert_revision : 0378261342df008c2bf6d260295ef21b15f119a8
2006-02-27Got rid of the fault_addr function.Gabe Black
--HG-- extra : convert_revision : deb54cd82db47abb6d9bac76e072f2a4b1c883b2
2006-02-27Merge ktlim@zizzer:/bk/m5Kevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/m5-clean --HG-- extra : convert_revision : 97c345f0715a347ce34f9cabd994485f30f2e171
2006-02-27Changes to put all the misc regs within the misc reg file. This includes ↵Kevin Lim
the FPCR, Uniq, lock flag, lock addr, and IPRs. They are now accessed by calling readMiscReg()/setMiscReg() on the XC. Old IPR accesses are supported by using readMiscRegWithEffect() and setMiscRegWithEffect() (names may change in the future). arch/alpha/alpha_memory.cc: Change accesses to IPR to go through the XC. arch/alpha/ev5.cc: Change accesses for IPRs to go through the misc regs. arch/alpha/isa/decoder.isa: Change accesses to IPRs to go through the misc regs. readIpr() and setIpr() are now changed to calls to readMiscRegWithEffect() and setMiscRegWithEffect(). arch/alpha/isa/fp.isa: Change accesses to IPRs and Fpcr to go through the misc regs. arch/alpha/isa/main.isa: Add support for all misc regs being accessed through readMiscReg() and setMiscReg(). Instead of readUniq and readFpcr, they are replaced by calls with Uniq_DepTag and Fpcr_DepTag passed in as the register index. arch/alpha/isa_traits.hh: Change the MiscRegFile to a class that handles all accesses to MiscRegs, which in Alpha include the FPCR, Uniq, Lock Addr, Lock Flag, and IPRs. Two flavors of accesses are supported: normal register reads/writes, and reads/writes with effect. The latter are basically the original read/write IPR functions, while the former are normal reads/writes. The lock flag and lock addr registers are added to the dependence tags in order to support being accessed through the misc regs. arch/alpha/stacktrace.cc: cpu/simple/cpu.cc: dev/sinic.cc: Change accesses to the IPRs to go through the XC. arch/alpha/vtophys.cc: Change access to the IPR to go through the XC. arch/isa_parser.py: Change generation of code for control registers to use the readMiscReg and setMiscReg functions. base/remote_gdb.cc: Change accesses to the IPR to go through the XC. cpu/exec_context.hh: Use the miscRegs to access the lock addr, lock flag, and other misc registers. cpu/o3/alpha_cpu.hh: cpu/simple/cpu.hh: Support interface for reading and writing misc registers, which replaces readUniq, readFpcr, readIpr, and their set functions. cpu/o3/alpha_cpu_impl.hh: Change accesses to the IPRs to go through the miscRegs. For now comment out some of the accesses to the misc regs until the proxy exec context is completed. cpu/o3/alpha_dyn_inst.hh: Change accesses to misc regs to use readMiscReg and setMiscReg. cpu/o3/alpha_dyn_inst_impl.hh: Remove old misc reg accessors. cpu/o3/cpu.cc: Comment out old misc reg accesses until the proxy exec context is completed. cpu/o3/cpu.hh: Change accesses to the misc regs. cpu/o3/regfile.hh: Remove old access methods for the misc regs, replace them with readMiscReg and setMiscReg. They are dummy functions for now until the proxy exec context is completed. kern/kernel_stats.cc: kern/system_events.cc: Have accesses to the IPRs go through the XC. kern/tru64/tru64.hh: Have accesses to the misc regs use the new access methods. --HG-- extra : convert_revision : e32e0a3fe99522e17294bbe106ff5591cb1a9d76
2006-02-27Renamed arch files to remove alpha prefix, and changed alpha_memory.hh and ↵Gabe Black
cc to a more accurate tlb.hh and cc --HG-- rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux_process.cc rename : arch/alpha/alpha_linux_process.hh => arch/alpha/linux_process.hh rename : arch/alpha/alpha_memory.cc => arch/alpha/tlb.cc rename : arch/alpha/alpha_memory.hh => arch/alpha/tlb.hh rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64_process.cc rename : arch/alpha/alpha_tru64_process.hh => arch/alpha/tru64_process.hh extra : convert_revision : 9fe6863cc37347d2a6bd716c529b0a4a50b36ea7
2006-02-27Changed targetarch to just arch.Gabe Black
SConscript: Changed all of the "targetarch" files to be "arch" files arch/SConscript: Added all of the remaining targetarch files to isa_switch_hdrs --HG-- extra : convert_revision : a37d18349e27cf92dce12814f21944daa7fe9480
2006-02-27Added isMachineCheckFault and isAlignmentFault virtual functions to the ↵Gabe Black
fault base class, and replaced the isA templated function with them where appropriate. arch/alpha/ev5.cc: cpu/simple/cpu.cc: Changed from the isA templated function to isMachineCheckFault and isAlignmentFault sim/faults.hh: Added isMachineCheckFault and isAlignmentFault virtual functions to the fault base class. --HG-- extra : convert_revision : 3bf3a4369bc24a039648ee4f2a9c1663362ff2e2
2006-02-27Put the Alpha faults into the AlphaISA namespaceGabe Black
--HG-- extra : convert_revision : d9586bb8ffaab74673aa0b3d17bb676b949ff212
2006-02-27MachineCheckFaults and AlignmentFaults are now generated by the ISA, rather ↵Gabe Black
than being created directly. arch/alpha/alpha_memory.cc: cpu/base_dyn_inst.cc: dev/alpha_console.cc: dev/pcidev.hh: dev/sinic.cc: MachineCheckFaults are now generated by the ISA, rather than being created directly. --HG-- extra : convert_revision : 34a7da41639e93be21ed70dac681b27480008d19
2006-02-25Make sure cpu/static_inst_exec_sigs.hh get rebuilt whenSteve Reinhardt
CPU_MODELS parameter changes. arch/SConscript: Fix typo in comment. cpu/SConscript: Convert exec signature generator to Action so we can add dependency on CPU_MODELS environment var. Print nicer string while we're at it. Also add some comments. --HG-- extra : convert_revision : bcb38a7941943cf071dac34cdbb2ece5456b8620
2006-02-24Merge gblack@m5.eecs.umich.edu:/bk/multiarchGabe Black
into ewok.(none):/home/gblack/m5/multiarch SConscript: arch/alpha/ev5.cc: dev/alpha_console.cc: Hand merged --HG-- extra : convert_revision : 318a671e6803400d3ed086a90e70d6790e4f6b19
2006-02-24Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5Steve Reinhardt
into zizzer.eecs.umich.edu:/z/stever/bk/multiarch arch/isa_parser.py: SCCS merged --HG-- extra : convert_revision : 080cca7616b37db3bf18976b63b3dbcb47d8b918
2006-02-24Changed Fault from a FaultBase * to a RefCountingPtr, added "new"s where ↵Gabe Black
appropriate, and took away the constant examples of each fault which where for comparing to a fault to determine its type. arch/alpha/alpha_memory.cc: arch/alpha/isa/decoder.isa: Added news where faults are created. arch/alpha/ev5.cc: Changed places where a fault was compared to a fault type to use isA rather than == arch/alpha/faults.cc: arch/alpha/faults.hh: Changed Fault to be a RefCountingPtr arch/alpha/isa/fp.isa: Added a new where a FloatEnableFault was created. arch/alpha/isa/unimp.isa: arch/alpha/isa/unknown.isa: Added a new where an UnimplementedFault is created. base/refcnt.hh: Added include of stddef.h for the NULL macro cpu/base_dyn_inst.cc: Added a new where an UnimplementedOpcodeFault is created. cpu/o3/alpha_cpu_impl.hh: Changed places where a fault was compared to a fault type to use isA rather than ==. Also changed fault->name to fault->name() cpu/o3/regfile.hh: Added new where UnimplementedOpcodeFaults are created. cpu/simple/cpu.cc: Changed places where a fault was compared to a fault type to use isA rather than ==. Also added a new where an Interrupt fault is created. dev/alpha_console.cc: Added news where MachineCheckFaults are created. dev/pcidev.hh: Added news where MachineCheckFaults are generated. dev/sinic.cc: Changed places where a fault was compared to a fault type to use isA rather than ==. Added news where MachineCheckFaults are created. Fixed a problem where m5.fast had unused variables. kern/kernel_stats.cc: Commented out where _faults is initialized. This statistic will probably be moved elsewhere in the future. kern/kernel_stats.hh: Commented out the declaration of _fault. when fault() is called, the fault increments its own stat. sim/faults.cc: sim/faults.hh: Changed Fault from a FaultBase * to a RefCountingPtr. --HG-- extra : convert_revision : b40ccfc42482d5a115e111dd897fa378d23c6c7d
2006-02-23name changes ...Korey Sewell
SConscript: change to alpha_memory.hh --HG-- rename : arch/alpha/memory.cc => arch/alpha/alpha_memory.cc rename : arch/alpha/memory.hh => arch/alpha/alpha_memory.hh extra : convert_revision : 62b1a41de22701160f04cb7a78242746cfcde819
2006-02-23Enable building only selected CPU models via new sconsSteve Reinhardt
CPU_MODELS parameter. For example: scons CPU_MODELS="SimpleCPU,FullCPU" ALPHA_SE/m5.debug Unfortunately the option is not sticky due to a scons bug with saving & restoring ListOption parameters. SConscript: Separate out cpu-model-specific files so they can be conditionally included based on value of new CPU_MODELS parameter. Most of these are now handled in cpu/SConscript, except for FullCPU which is still in this file. arch/SConscript: The set of CPU-model-specific execute files must now be determined from the CPU_MODELS parameter, via the new cpu_models.py file. Also pass the list of configured CPU models to isa_parser.py. arch/isa_parser.py: Move CpuModel definition and objects out to a separate file so they can be shared with scons. Global list of CPU models to generate code for is now controlled by command-line parameters (so we can do only a subset of the available ones). build/SConstruct: Define new CPU_MODELS ListOption. cpu/static_inst.hh: Rename static_inst_impl.hh to static_inst_exec_sigs.hh. --HG-- extra : convert_revision : 163df32a76d4c05900490b2bce4c7962a5e3f614
2006-02-23ev5.cc:Ali Saidi
SCCS merged arch/alpha/ev5.cc: SCCS merged --HG-- extra : convert_revision : 9d70c1d461dab0ec016fd0616d74a49942aac659
2006-02-23Merge zizzer:/bk/m5Ali Saidi
into zeep.eecs.umich.edu:/z/saidi/work/m5.head cpu/simple/cpu.cc: remove initCPU from constructor dev/alpha_console.cc: we are panicing, so no need to return a fault --HG-- extra : convert_revision : 72389ea0c96e91a55f35b884200325224bfb6ed9
2006-02-23Get rid of the xc from the alphaAccess/alphaConsole backdoor device.Ali Saidi
Now allocate an array of stacks indexed by cpu number which specify cpu stacks and are initialized by cpu 0. Othe cpus spin waiting for their stacks before continuing. This change *REQUIRES* a the new console code to operate correctly. arch/alpha/ev5.cc: Add cpuId to initCPU/initIPR functions cpu/o3/cpu.cc: cpu/simple/cpu.cc: cpu/simple/cpu.hh: Move the cpu initilization into an init() function since it now needs the CPU id which isn't known at construction dev/alpha_access.h: dev/alpha_console.cc: dev/alpha_console.hh: instead of the bootstrap variables, add space for 64 cpu stacks in the alpha access structure. sim/system.cc: start all cpus immediately rather than just the first one --HG-- extra : convert_revision : 28c218af49d885a0f203ada419f16f25d5a3f37b
2006-02-23Create a Builder object for .isa files in arch/SConscript.Steve Reinhardt
Start using SCons File objects to avoid fixed paths in subordinate SConscripts. SConscript: Push isa_parser stuff (including .isa scanner) down into arch/SConscript. arch/SConscript: Create a Builder object for .isa files, including existing scanner. Return file objects generated by isa-specific SConscript back up to parent. arch/alpha/SConscript: arch/mips/SConscript: arch/sparc/SConscript: Convert sources to scons File objects, so file names can be specified relative to the current directory. Invoke new builder for isa description, and get generated sources from there (instead of listing them explicitly). arch/isa_parser.py: Get rid of third argument ("include_path"). It was a pain to generate this from scons, and it turned out it's not needed anyway, since the only included file (decoder.hh) will be in the same directory as the sources. --HG-- extra : convert_revision : 36861bcef36763f229704d8cb7a642b4486a3581
2006-02-23Add pipe() syscall to Alpha Linux emulation.Steve Reinhardt
arch/alpha/alpha_linux_process.cc: Add pipeFunc. --HG-- extra : convert_revision : c094d2dff993d5e60bc43b7cd4b9586c15c634a3
2006-02-23Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5Gabe Black
into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch --HG-- extra : convert_revision : 850077a56aead260aa4bbd3df60b672a931d57ed
2006-02-22Auto-generate arch/foo.hh "switch headers" in scons.Steve Reinhardt
SConscript: Include new arch/SConscript file. arch/isa_specific.hh: Get rid of unnecessary ISA_INCLUDE() macro and other things that were used only for that purpose. build/SConstruct: Move list of ISAs to env var ALL_ISA_LIST. --HG-- extra : convert_revision : 612c7ee4279d57209662be88dc577d80fdbd692c
2006-02-22Clean excess comments out of SConscripts.Steve Reinhardt
SConscript: arch/alpha/SConscript: Clean out excess comments. --HG-- extra : convert_revision : 7aae68d36f9fce5f236d117d803b5e3cd4a3769d
2006-02-22make sure alpha still compiles , rename files back to original naming ...Korey Sewell
Now that we have decoder.do, add new files so we can start compiling other files needed for MIPS syscall emulation mode arch/mips/linux_process.cc: arch/mips/linux_process.hh: New MIPS-specific file --HG-- rename : arch/alpha/linux_process.cc => arch/alpha/alpha_linux_process.cc rename : arch/alpha/linux_process.hh => arch/alpha/alpha_linux_process.hh rename : arch/alpha/tru64_process.cc => arch/alpha/alpha_tru64_process.cc rename : arch/alpha/tru64_process.hh => arch/alpha/alpha_tru64_process.hh extra : convert_revision : 2bfc27e8772523cbeb95f40684f9a32fe5554f87
2006-02-22Still builds "../MIPS_SE/arch/mips/decoder.do with no errors!Korey Sewell
----- uncomment out detailed model ... just commented to supress some compile errors arch/isa_parser.py: uncomment out detailed model ... just commented to supress some compile errors --HG-- extra : convert_revision : e884b9bd47794409f74043ad1aca6dadd1323185
2006-02-22MIPS Compiles scons/MIPS_SE/arch/mips/decoder.do!!!!!!Korey Sewell
arch/mips/faults.hh: remove nonsense arch/mips/isa/base.isa: define R31 arch/mips/isa/bitfields.isa: forgotten bitfields arch/mips/isa/decoder.isa: INT64 -> int64_t arch/mips/isa/formats.isa: fix comments arch/mips/isa/formats/branch.isa: Branch -> BranchLikely RB -> RT arch/mips/isa/formats/fp.isa: Make FP ops generates arch/mips/isa/formats/mem.isa: RA,RB -> RS,RT arch/mips/isa/formats/noop.isa: Rc -> Rd arch/mips/isa/formats/util.isa: forgot brace and semicolon arch/mips/isa/includes.isa: remove unnecessary files arch/mips/isa_traits.hh: spacing cpu/static_inst.hh: add cond_delay_slot flag --HG-- extra : convert_revision : 3bc7353b437f9a764e85cc462bed86c9d654eb37
2006-02-21Merge zizzer:/bk/multiarchKorey Sewell
into zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/multiarch --HG-- rename : arch/alpha/alpha_memory.cc => arch/alpha/memory.cc rename : arch/alpha/alpha_memory.hh => arch/alpha/memory.hh extra : convert_revision : c641ba3c1009829b7276279b2dca441be1da5b30
2006-02-21Renaming alpha files and changing some MIPS stuff to be more like Alpha versionKorey Sewell
SConscript: changed the alpha_memory.hh to memory.hh in SConscript arch/isa_parser.py: temporarily comment out o3 model arch/mips/isa/base.isa: arch/mips/isa_traits.cc: arch/mips/isa_traits.hh: Fix Up Base Class to mirror how Alpha generates StaticInsts arch/mips/faults.cc: MIPS fault.cc file arch/mips/faults.hh: MIPS fault.hh file --HG-- rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux_process.cc rename : arch/alpha/alpha_linux_process.hh => arch/alpha/linux_process.hh rename : arch/alpha/alpha_memory.cc => arch/alpha/memory.cc rename : arch/alpha/alpha_memory.hh => arch/alpha/memory.hh rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64_process.cc rename : arch/alpha/alpha_tru64_process.hh => arch/alpha/tru64_process.hh extra : convert_revision : f92d6e765ca96a8b952aef79ed119fa29464563b
2006-02-21Changed Fault * to Fault, which is a typedef to FaultBase *, which is the ↵Gabe Black
old Fault class renamed. --HG-- extra : convert_revision : 5b2f457401f8ff94fe39fe071288eb117814b7bb
2006-02-21Made Addr a global typeGabe Black
--HG-- extra : convert_revision : 869bd9fa5d8591115ac9b4a7401eb2490986b835
2006-02-20make MIPS specificKorey Sewell
--HG-- extra : convert_revision : c019fad60fbf1a316bc6201b8ce8acf5a9875989
2006-02-20load/store instruction format ... now generates load/store codeKorey Sewell
and breaks it into a separate EA and MemAccess templated from how the Alpha ARch. was coded to do the same thing. arch/mips/isa/bitfields.isa: comment change arch/mips/isa/decoder.isa: re-structuring of load/store instruction definitions arch/mips/isa/formats/mem.isa: Define LoadMemory & Store Memory formats Use style of formatting & base class similar to what was used for ALPHA arch/mips/isa/formats/util.isa: Insert LoadStoreBase function here from alpha/arch/isa/mem.isa arch/mips/isa/operands.isa: change shw->sh and uhw->uh --HG-- extra : convert_revision : 5d85f15f4a600dd4c473a3b4a170ba39cf07fc8a
2006-02-20Support for All Jump Instructions ...Korey Sewell
Redo format for Branches and Jumps ( Must update NNPC not NPC ) Now all branches and jumps look like they auto-generate correctly from isa_parser.py!!! arch/mips/isa/decoder.isa: Support for All Jump Instructions .. arch/mips/isa/formats/branch.isa: Redo format for Branches and Jumps ( Must update NNPC not NPC ) arch/mips/isa/formats/util.isa: define clear_exe_inst_hazards for later use --HG-- extra : convert_revision : 63618ed12ee6ed94c47d29619cc1cab2cbaf5cda
2006-02-19Reapplied changes which were undone by a pullGabe Black
arch/alpha/faults.hh: kern/linux/linux.hh: Added typedef for Addr kern/tru64/tru64.hh: Fixed up namespaces --HG-- extra : convert_revision : bf968e615bc0acc96abeb0eec0872f5b02b5a065
2006-02-19Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5Gabe Black
into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch arch/alpha/faults.hh: ur Using cleaned up fault class deiffinitions --HG-- extra : convert_revision : a600950d539be2be73358f072aa5426456bf3d2d
2006-02-19Merge gblack@m5.eecs.umich.edu:/bk/multiarchGabe Black
into ewok.(none):/home/gblack/m5/multiarch --HG-- extra : convert_revision : 090b30a7f70294e1aeb13ba0bc15da4061bdf348
2006-02-19Changes to untemplate StaticInst and StaticInstPtr, change the isa to a ↵Gabe Black
namespace instead of a class, an improvement to the architecture specific header file selection system, and fixed up a few include paths. arch/alpha/alpha_linux_process.cc: Added using directive for AlphaISA namespace arch/alpha/alpha_memory.hh: arch/alpha/isa/branch.isa: cpu/pc_event.hh: Added typedefs for Addr arch/alpha/alpha_tru64_process.cc: arch/alpha/arguments.cc: Added using directive for AlphaISA arch/alpha/ev5.hh: Added an include of arch/alpha/isa_traits.hh, and a using directive for the AlphaISA namespace. arch/alpha/faults.hh: Added a typedef for the Addr type, and changed the formatting of the faults slightly. arch/alpha/isa/main.isa: Untemplatized StaticInst, added a using for namespace AlphaISA to show up in decoder.cc and the exec.ccs, relocated makeNop to decoder.hh arch/alpha/isa/mem.isa: Untemplatized StaticInst and StaticInstPtr arch/alpha/isa/pal.isa: cpu/base_dyn_inst.cc: Untemplatized StaticInstPtr arch/alpha/isa_traits.hh: Changed variables to be externs instead of static since they are part of a namespace and not a class. arch/alpha/stacktrace.cc: Untemplatized StaticInstPtr, and added a using directive for AlphaISA. arch/alpha/stacktrace.hh: Added some typedefs for Addr and MachInst, and untemplatized StaticInstPtr arch/alpha/vtophys.cc: Added a using directive for AlphaISA arch/alpha/vtophys.hh: Added the AlphaISA namespace specifier where needed arch/isa_parser.py: Changed the placement of the definition of the decodeInst function to be outside the namespaceInst namespace. base/loader/object_file.hh: cpu/o3/bpred_unit.hh: Added a typedef for Addr base/loader/symtab.hh: Added a typedef for Addr, and added a TheISA to Addr in another typedef base/remote_gdb.cc: Added a using namespace TheISA, and untemplatized StaticInstPtr base/remote_gdb.hh: Added typedefs for Addr and MachInst cpu/base.cc: Added TheISA specifier to some variables exported from the isa. cpu/base.hh: Added a typedef for Addr, and TheISA to some variables from the ISA cpu/base_dyn_inst.hh: Untemplatized StaticInstPtr, and added TheISA specifier to some variables from the ISA. cpu/exec_context.hh: Added some typedefs for types from the isa, and added TheISA specifier to some variables from the isa cpu/exetrace.hh: Added typedefs for some types from the ISA, and untemplatized StaticInstPtr cpu/memtest/memtest.cc: cpu/o3/btb.cc: dev/baddev.cc: dev/ide_ctrl.cc: dev/ide_disk.cc: dev/isa_fake.cc: dev/ns_gige.cc: dev/pciconfigall.cc: dev/platform.cc: dev/sinic.cc: dev/uart8250.cc: kern/freebsd/freebsd_system.cc: kern/linux/linux_system.cc: kern/system_events.cc: kern/tru64/dump_mbuf.cc: kern/tru64/tru64_events.cc: sim/process.cc: sim/pseudo_inst.cc: sim/system.cc: Added using namespace TheISA cpu/memtest/memtest.hh: cpu/trace/opt_cpu.hh: cpu/trace/reader/itx_reader.hh: dev/ide_disk.hh: dev/pcidev.hh: dev/platform.hh: dev/tsunami.hh: sim/system.hh: sim/vptr.hh: Added typedef for Addr cpu/o3/2bit_local_pred.hh: Changed the include to use arch/isa_traits.hh instead of arch/alpha/isa_traits.hh. Added typedef for Addr cpu/o3/alpha_cpu.hh: Added typedefs for Addr and IntReg cpu/o3/alpha_cpu_impl.hh: Added this-> to setNextPC to fix a problem since it didn't depend on template parameters any more. Removed "typename" where it was no longer needed. cpu/o3/alpha_dyn_inst.hh: Cleaned up some typedefs, and untemplatized StaticInst cpu/o3/alpha_dyn_inst_impl.hh: untemplatized StaticInstPtr cpu/o3/alpha_impl.hh: Fixed up a typedef of MachInst cpu/o3/bpred_unit_impl.hh: Added a using TheISA::MachInst to a function cpu/o3/btb.hh: Changed an include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr cpu/o3/commit.hh: Removed a typedef of Impl::ISA as ISA, since TheISA takes care of this now. cpu/o3/cpu.cc: Cleaned up namespace issues cpu/o3/cpu.hh: Cleaned up namespace usage cpu/o3/decode.hh: Removed typedef of ISA, and changed it to TheISA cpu/o3/fetch.hh: Fized up typedefs, and changed ISA to TheISA cpu/o3/free_list.hh: Changed include of arch/alpha/isa_traits.hh to arch/isa_traits.hh cpu/o3/iew.hh: Removed typedef of ISA cpu/o3/iew_impl.hh: Added TheISA namespace specifier to MachInst cpu/o3/ras.hh: Changed include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr. cpu/o3/regfile.hh: Changed ISA to TheISA, and added some typedefs for Addr, IntReg, FloatReg, and MiscRegFile cpu/o3/rename.hh: Changed ISA to TheISA, and added a typedef for RegIndex cpu/o3/rename_map.hh: Added an include for arch/isa_traits.hh, and a typedef for RegIndex cpu/o3/rob.hh: Added a typedef for RegIndex cpu/o3/store_set.hh: cpu/o3/tournament_pred.hh: Changed an include of arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef of Addr cpu/ozone/cpu.hh: Changed ISA into TheISA, and untemplatized StaticInst cpu/pc_event.cc: Added namespace specifier TheISA to Addr types cpu/profile.hh: kern/kernel_stats.hh: Added typedef for Addr, and untemplatized StaticInstPtr cpu/simple/cpu.cc: Changed using directive from LittleEndianGuest to AlphaISA, which will contain both namespaces. Added TheISA where needed, and untemplatized StaticInst cpu/simple/cpu.hh: Added a typedef for MachInst, and untemplatized StaticInst cpu/static_inst.cc: Untemplatized StaticInst cpu/static_inst.hh: Untemplatized StaticInst by using the TheISA namespace dev/alpha_console.cc: Added using namespace AlphaISA dev/simple_disk.hh: Added typedef for Addr and fixed up some formatting dev/sinicreg.hh: Added TheISA namespace specifier where needed dev/tsunami.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: Added using namespace TheISA. It might be better for it to be AlphaISA dev/tsunami_cchip.cc: Added typedef for TheISA. It might be better for it to be AlphaISA kern/linux/aligned.hh: sim/pseudo_inst.hh: Added TheISA namespace specifier to Addr kern/linux/linux_threadinfo.hh: Added typedef for Addr, and TheISA namespace specifier to StackPointerReg kern/tru64/mbuf.hh: Added TheISA to Addr type in structs sim/process.hh: Added typedefs of Addr, RegFile, and MachInst sim/syscall_emul.cc: Added using namespace TheISA, and a cast of VMPageSize to the int type sim/syscall_emul.hh: Added typecast for Addr, and TheISA namespace specifier for where needed --HG-- extra : convert_revision : 91d4f6ca33a73b21c1f1771d74bfdea3b80eff45
2006-02-19Merge zizzer:/bk/m5Ali Saidi
into pb15.local:/Users/ali/work/m5.head --HG-- extra : convert_revision : 774e4afbb0f9c3ae62843138b6d7195ea184ff92
2006-02-19forgot a negative signAli Saidi
--HG-- extra : convert_revision : 9cdb00198979fca831d3e6840f9c534671ccead3
2006-02-18Move Linux/Tru64 architecture independent code into kern/*Ali Saidi
leaving dependent code making way for solaris linux syscall emu. SConscript: Add two new files for syscall emulation Add getDesc() function arch/alpha/alpha_linux_process.cc: arch/alpha/alpha_tru64_process.cc: move architecture independent code into kern/linux/linux.(hh|cc) arch/alpha/alpha_linux_process.hh: arch/alpha/alpha_tru64_process.hh: Add getDesc function kern/linux/linux.hh: move generi linux syscall emulation code into kern/linux kern/tru64/tru64.hh: move generi tru64 syscall emulation code into kern/tru64 sim/process.cc: sim/process.hh: Push the function determination and calling stuff down to LiveProcess and out of the Linux/Tru64 classes respectively sim/syscall_emul.cc: sim/syscall_emul.hh: fnctl implementation was identical in tru64 and linux so moved to generic --HG-- extra : convert_revision : 103293dbe6fe2f7892de4929d17dc085def77026
2006-02-18Support NNPC and branch instructions ... Outputs to decoder.cc correctlyKorey Sewell
Edits to the CPU model may still need to be made to handle branch likely insts... arch/isa_parser.py: add a NNPC operand ... arch/mips/isa/base.isa: change SPARC to MIPS arch/mips/isa/decoder.isa: typo < to >= arch/mips/isa/formats/basic.isa: spacing arch/mips/isa/formats/branch.isa: add code for branch instructions (still need adjustments for the branch likely) arch/mips/isa/operands.isa: support for NNPC and R31 arch/mips/isa_traits.hh: NNPC Addr variable --HG-- extra : convert_revision : df03d2a71c36dbc00270c2e3d7882b4f09ed97ad
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-30 21:02:11 +0000