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2006-04-06Merge m5.eecs.umich.edu:/bk/newmemGabe Black
into ewok.(none):/home/gblack/m5/newmem --HG-- extra : convert_revision : bd6352647798275a12d52d55a129cdddd8e25423
2006-04-06Fixed up the isa description. Also added some capability to the isa_parser ↵Gabe Black
in the InstObjParams constructor. arch/isa_parser.py: Expanded the capability of the InstObjParams constructor to allow adding in extra keys for use in templates. These are added as key, value tuples as optional arguements. arch/sparc/isa/base.isa: arch/sparc/isa/formats/mem.isa: arch/sparc/isa/formats/priv.isa: The genCompositeIop function is no longer needed, as this functionality is now in the InstObjParams constructor. arch/sparc/isa/decoder.isa: Fixed up alot of instructions, and fixed indentation. arch/sparc/isa/formats/integerop.isa: The genCompositeIop function is no longer needed, as this functionality is now in the InstObjParams constructor. Also changed the immediate values to be signed. base/traceflags.py: Added SPARC traceflag configs/test/hello_sparc: Recompiled without -mflat cpu/cpu_exec_context.cc: Used the regfile clear function rather than memsetting to 0. --HG-- extra : convert_revision : b9da6f264f3ebc4ce1815008dfff7f476b247ee9
2006-04-06fixes for new memory systemAli Saidi
SConscript: comment out most devices add vport.cc arch/alpha/arguments.cc: arch/alpha/arguments.hh: push in alpha name space fix for new memory system arch/alpha/faults.cc: arch/alpha/faults.hh: Added an unimplemented fault that can be returned if a certain function isn't implemented arch/alpha/freebsd/system.cc: arch/alpha/linux/system.cc: arch/alpha/stacktrace.cc: arch/alpha/system.cc: arch/alpha/tlb.hh: arch/alpha/tru64/system.cc: fixed for new memory system arch/alpha/tlb.cc: fixed for new memory system removed code that seems to have no purpose arch/alpha/vtophys.cc: arch/alpha/vtophys.hh: fixed for new memory system put in namespace AlphaISA base/remote_gdb.cc: fix for new memory system cpu/cpu_exec_context.cc: cpu/cpu_exec_context.hh: cpu/exec_context.hh: create two ports one of physical accesses and one for superpage accesses Add functions getVirtPort() getPhysPort() delVirtPort(). To get statically allocated physical or virtual ports or if an execcontext is passed in get a dynamically allocated virtual port dev/alpha_console.cc: dev/alpha_console.hh: Redo for new memory system dev/io_device.cc: dev/io_device.hh: new I/O devices for new memory system kern/linux/events.cc: kern/linux/printk.cc: kern/linux/printk.hh: kern/tru64/dump_mbuf.hh: kern/tru64/printf.cc: kern/tru64/printf.hh: Arguments now in namespaces kern/tru64/tru64_events.cc: mem/bus.cc: fix for new memory syste mem/physical.hh: new addressranges function getPort should be public mem/port.hh: Add write/read methods to functional port update getDeviceAddrRanges to have a list of both snoops and response lists sim/pseudo_inst.cc: sim/system.cc: sim/system.hh: Update for new mem system sim/vptr.hh: comment out code and replace with panics This will need to be fixed at some point, but it's not easy. --HG-- extra : convert_revision : 41f41f422cfbab3751284d55cccb6ea64a7956e2
2006-03-31Merge m5.eecs.umich.edu:/bk/newmemGabe Black
into ewok.(none):/home/gblack/m5/newmem --HG-- extra : convert_revision : 08ae5e999d9b313e3e40cb6d58863905b70ca781
2006-03-31Fixes to SPARC for syscall emulation mode.Gabe Black
arch/sparc/isa/base.isa: arch/sparc/isa/decoder.isa: arch/sparc/isa/formats.isa: arch/sparc/isa/formats/branch.isa: arch/sparc/isa/formats/integerop.isa: arch/sparc/isa/formats/mem.isa: arch/sparc/isa/formats/nop.isa: arch/sparc/isa/formats/trap.isa: arch/sparc/isa/formats/unknown.isa: arch/sparc/isa/includes.isa: arch/sparc/isa/operands.isa: Fixes towards running in syscall emulation mode. arch/sparc/linux/process.cc: Fixed the assert and comment to check that the Num_Syscall_Descs is less than or equal to 284. Why does this assert need to exist anyway? base/loader/elf_object.cc: Cleared out comments about resolved issues. cpu/simple/cpu.cc: Use NNPC for both SPARC and MIPS, instead of just MIPS configs/test/hello_sparc: A test program for SPARC which prints "Hello World!" --HG-- rename : arch/sparc/isa/formats/noop.isa => arch/sparc/isa/formats/nop.isa extra : convert_revision : 10b3e3b9f21c215d809cffa930448007102ba698
2006-03-30Add a functional port that is used to load the original binaries in FSAli Saidi
SE mode now has a port that goes to whatever toplevel mem object the CPU sees that does the appropriate translation for syscall emulation SConscript: translating port is a syscall emu only source arch/alpha/system.cc: base/loader/object_file.cc: base/loader/object_file.hh: Use the new functional port to write the binaries into memory cpu/cpu_exec_context.cc: cpu/cpu_exec_context.hh: cpu/simple/cpu.cc: We aren't always going to be writing straight to memory with syscalls support writing to a cache mem/port.hh: Add a simple unidirectional functional port that panics on any incoming requests mem/translating_port.hh: make translating port inherit from the simple port sim/system.cc: sim/system.hh: Add a functional port that is used to load the original binaries --HG-- extra : convert_revision : 9096866d0b23e3aceea68394abb76e63c0f8fd8d
2006-03-30Make TranslatingPort be a type of Port rather than something specialAli Saidi
arch/alpha/arguments.cc: rather than returning 0, put a panic in... it will actually make us fix this rather than scratching our respective heads base/loader/object_file.cc: base/loader/object_file.hh: Object loader now takes a port rather than a translating port cpu/cpu_exec_context.cc: cpu/cpu_exec_context.hh: sim/process.cc: Make translating port a type of port rather than anything special cpu/simple/cpu.cc: no need to grab a port from the cpu anymore mem/physical.cc: add an additional type of port to physicalmemory called "functional" Only used for functional accesses (loading binaries/syscall emu) mem/port.hh: make readBlok/writeBlob virtual so translating port can do the translation first mem/translating_port.cc: mem/translating_port.hh: Make TranslatingPort inherit from Port sim/system.cc: header file that doesn't exit removed --HG-- extra : convert_revision : 89b08f6146bba61f5605678d736055feab2fe6f7
2006-03-29Remove "using namespace std" from global declarations.Kevin Lim
--HG-- extra : convert_revision : c580bc6bd308fd502fb5a14ea84b5214e1d2718e
2006-03-16Merge zizzer:/bk/newmemKorey Sewell
into zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-mips --HG-- extra : convert_revision : 02fe0b0170348dc6f6a985c15123806088a8c23e
2006-03-16Found and fixed 3 decoder.isa bugs!!! Now the hello_world program runs for a ↵Korey Sewell
while before getting in a infinite loop. It actually "tries" to syscall too, but syscalls aren't implemented just yet arch/mips/faults.cc: more descriptive names for faults (will help future users as well as me!) arch/mips/isa/base.isa: make sure we are printing out "BasicOp" format disassembly instructions as dest,src,src instead of src,src,dest arch/mips/isa/decoder.isa: FIX LW/SW Bug!!!! I was actually loading a byte instead of a word FIX JALR Bug!!!! I was not saving the link address in R31 for this instruction FIX SLL/NOP Bug!!! We now recognize the varying flavors of sll,nop,ehb,& ssnop correctly base/loader/elf_object.cc: change back to original way base/loader/elf_object.hh: change back to original! --HG-- extra : convert_revision : 39b65fba31c1842ac6966346fe8a35816a4231fa
2006-03-16Add warning for ignored loadable ELF segments.Steve Reinhardt
base/loader/elf_object.cc: Print warning if there are more than two loadable segments. We currently assume there are at most two (text & data), and that's held so far, but it would be nice not to silently ignore others. --HG-- extra : convert_revision : 1b3e693e95ba1210b09528b97819a7fa86426edc
2006-03-15infinitesimal small baby steps toward MIPS actually workingKorey Sewell
arch/mips/isa/formats/branch.isa: let user know that we alter r31 in disassembly arch/mips/isa_traits.cc: add copyRegs function ... comment out serialize float code for now arch/mips/isa_traits.hh: make FloatRegFile a class ... change values of architectural regs arch/mips/process.cc: change MIPS to Mips base/loader/elf_object.cc: get global pointer initialized to a value base/loader/elf_object.hh: Add global_ptr to elf_object constructor base/loader/object_file.hh: MIPS to Mips base/traceflags.py: SimpleCPU trace flag cpu/simple/cpu.cc: DPRINTF flags for SimpleCPU cpu/static_inst.hh: Add Decoder functions to static_inst.hh --HG-- extra : convert_revision : 0544a8524d3fe4229428cb06822f7da208c72459
2006-03-14Merge m5.eecs.umich.edu:/bk/newmemGabe Black
into ewok.(none):/home/gblack/m5/newmem cpu/cpu_exec_context.cc: Hand merge --HG-- rename : arch/alpha/registerfile.hh => arch/alpha/regfile.hh extra : convert_revision : bd18966f7c37c67c2bc7ca2633b58f70ce64409c
2006-03-14Changed the floating point register file into a class with appropriate ↵Gabe Black
accessor functions. The width of the floating point register to access can be specified, and if not, it will be accessed at its "natural" width. That is, the width of each individual register. Also, the functions which access the bit representation of floating point registers can use the blahblahBits functions now instead of blahblahInt. arch/alpha/arguments.cc: Renamed readFloatRegInt to readFloatRegBits arch/alpha/ev5.cc: Removed the Double from setFloatRegDouble arch/alpha/registerfile.hh: Changed the floating point register file from a union of arrays to a class with appropriate accessor functions. The interface is necessary for SPARC. arch/alpha/types.hh: Changed the FloatReg type from a union of uint64_t and double to a double, and defined a new type FloatRegBits which is a uint64_t and is used to return the bits which compose a floating point register rather than the value of the register. arch/isa_parser.py: Adjusted the makeRead and makeWrite functions to generate the new versions of readFloatReg and setFloatReg. base/remote_gdb.cc: kern/tru64/tru64.hh: Replaced setFloatRegInt with setFloatRegBits cpu/cpu_exec_context.cc: Removed the duplicated code for setting the floating point registers, and renamed the function to setFloatRegBits and readFloatRegBits. cpu/cpu_exec_context.hh: cpu/exec_context.hh: cpu/o3/alpha_cpu_impl.hh: cpu/o3/alpha_dyn_inst.hh: cpu/o3/cpu.cc: cpu/o3/cpu.hh: cpu/o3/regfile.hh: cpu/ozone/cpu.hh: cpu/simple/cpu.hh: Implemented the new versions of the floating point read and set functions. cpu/simple/cpu.cc: Replaced setFloatRegDouble with setFloatReg --HG-- extra : convert_revision : 3dad06224723137f6033c335fb8f6395636767f2
2006-03-12Get rid of "Functional" suffix from (read|write)(Blob|String) functions.Steve Reinhardt
--HG-- extra : convert_revision : 1456308af0fd686dff53ec1baddd7747354e1c0a
2006-03-10Work towards factoring isa_traits.hh into smaller, more specialized files.Gabe Black
arch/SConscript: Sorted the switch headers, and added registerfile.hh, constants.hh, types.hh, and utility.hh. arch/alpha/isa_traits.hh: Moved the register file types to registerfile.hh, small functions to utility.hh, and cleaned out alot of stuff that isn't necessary anymore. base/loader/ecoff_object.cc: base/loader/elf_object.cc: cpu/pc_event.hh: cpu/static_inst.hh: mem/port.hh: sim/faults.cc: sim/system.hh: base/misc.hh isn't included through isa_traits.hh anymore. cpu/simple/cpu.cc: Added include for arch/utility.hh --HG-- extra : convert_revision : 24f65f330f87e3c909c939596cfcf48336022eaf
2006-03-09SimpleCPU compiles with merge.Gabe Black
arch/alpha/isa_traits.hh: arch/alpha/linux/process.cc: arch/alpha/process.cc: arch/alpha/process.hh: arch/alpha/tru64/process.cc: base/chunk_generator.hh: base/loader/elf_object.cc: cpu/cpu_exec_context.cc: cpu/cpu_exec_context.hh: cpu/exec_context.hh: cpu/simple/cpu.cc: kern/linux/linux.hh: kern/tru64/tru64.hh: mem/packet.hh: mem/page_table.cc: mem/page_table.hh: mem/physical.cc: mem/request.hh: mem/translating_port.cc: sim/process.hh: sim/system.cc: Fixing merged changes. --HG-- extra : convert_revision : 2e94f21009395db654880fcb94ec806b6f5772c3
2006-03-09Hand merge. Stuff probably doesn't compile.Gabe Black
--HG-- rename : arch/alpha/isa_desc => arch/alpha/isa/main.isa rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux/process.cc rename : arch/alpha/alpha_linux_process.hh => arch/alpha/linux/process.hh rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64/process.cc rename : arch/alpha/alpha_tru64_process.hh => arch/alpha/tru64/process.hh rename : cpu/exec_context.cc => cpu/cpu_exec_context.cc rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh extra : convert_revision : 7d1efcedd708815d985a951f6f010fbd83dc27e8
2006-03-09Merge zizzer:/bk/multiarchAli Saidi
into zeep.eecs.umich.edu:/z/saidi/work/m5.ma2 arch/alpha/isa_traits.hh: arch/alpha/linux/process.cc: arch/sparc/isa_traits.hh: arch/sparc/linux/process.cc: sim/process.cc: merge --HG-- rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh extra : convert_revision : fea0155c8e23abbd0d5d5251abbd0f4d223fe935
2006-03-09no more common syscall emulation, now common for everyoneAli Saidi
check abi-tag note section of elf binary for OS add pseudo functions (moved from alpha and made to be generic) move setsyscallreturn into isa traits arch/alpha/SConscript: no more common syscall emulation, now common for everyone arch/alpha/isa_traits.hh: move setsyscallreturn into isa description arch/alpha/linux/process.cc: arch/alpha/tru64/process.cc: use generic functions rather than alpha specific ones arch/sparc/isa_traits.hh: have consts for generic pseudo syscalls arch/sparc/linux/process.cc: use generic functions base/loader/elf_object.cc: check abi-tag note section of elf binary for OS cpu/exec_context.hh: move syssyscallreturn into isa traits sim/process.cc: find call num with a more generic sim/syscall_emul.cc: sim/syscall_emul.hh: add pseudo functions (moved from alpha and made to be generic) --HG-- extra : convert_revision : 5a31024ecde7e39b830365ddd84593ea501a34d2
2006-03-08Merge ktlim@zizzer:/bk/m5Kevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/m5-proxyxc arch/alpha/ev5.cc: cpu/o3/cpu.hh: SCCS merged --HG-- extra : convert_revision : 38889011ea02005c8fd3a7f3b0be3395223f6166
2006-03-07The a.out and ecoff object file formats will only be supported on Alpha for now.Gabe Black
arch/SConscript: aout_machdep.h and ecoff_machdep.h are no longer bridging headers, since support of these formats is limitted to alpha. base/loader/exec_aout.h: Include the alpha specific version of aout_machdep.h, since only the alpha version of aout will be supported for now. base/loader/exec_ecoff.h: Include the alpha specific version of ecoff_machdep.h, since only the alpha version of ecoff will be supported for now. --HG-- extra : convert_revision : 15328aae54538c26d2c10d7476501e0daa3d22d0
2006-03-05Merge ktlim@zizzer:/bk/m5Kevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/m5-proxyxc Further changes still need to be made to the XC code. arch/alpha/ev5.cc: arch/alpha/freebsd/system.cc: arch/alpha/linux/system.cc: base/remote_gdb.cc: cpu/cpu_exec_context.cc: cpu/cpu_exec_context.hh: cpu/simple/cpu.cc: cpu/simple/cpu.hh: kern/kernel_stats.cc: sim/pseudo_inst.cc: Hand merge. --HG-- rename : kern/freebsd/freebsd_system.cc => arch/alpha/freebsd/system.cc rename : kern/linux/linux_system.cc => arch/alpha/linux/system.cc rename : kern/linux/linux_threadinfo.hh => arch/alpha/linux/threadinfo.hh rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux_process.cc rename : arch/alpha/alpha_memory.cc => arch/alpha/tlb.cc rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64_process.cc rename : cpu/exec_context.cc => cpu/cpu_exec_context.cc rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh extra : convert_revision : c1fe71fdd87d1fcd376f4feec69fc3fa29152e3e
2006-03-04Steps towards setting up the infrastructure to allow the new CPU model to ↵Kevin Lim
work in full system mode. The major change is renaming the old ExecContext to CPUExecContext, and creating two new classes, ExecContext (an abstract class), and ProxyExecContext (a templated class that derives from ExecContext). Code outside of the CPU continues to use ExecContext as normal (other than not being able to access variables within the XC). The CPU uses the CPUExecContext, or however else it stores its own state. It then creates a ProxyExecContext, templated on the class used to hold its state. This proxy is passed to any code outside of the CPU that needs to access the XC. This allows code outside of the CPU to use the ExecContext interface to access any state needed, without knowledge of how that state is laid out. Note that these changes will not compile without the accompanying revision to automatically rename the shadow registers. SConscript: Include new file, cpu_exec_context.cc. arch/alpha/alpha_linux_process.cc: arch/alpha/alpha_memory.cc: arch/alpha/alpha_tru64_process.cc: arch/alpha/arguments.cc: arch/alpha/isa/decoder.isa: arch/alpha/stacktrace.cc: arch/alpha/vtophys.cc: base/remote_gdb.cc: cpu/intr_control.cc: Avoid directly accessing objects within the XC. arch/alpha/ev5.cc: Avoid directly accessing objects within the XC. KernelStats have been moved to the BaseCPU instead of the XC. arch/alpha/isa_traits.hh: Remove clearIprs(). It wasn't used very often and it did not work well with the proxy ExecContext. cpu/base.cc: Place kernel stats within the BaseCPU instead of the ExecContext. For now comment out the profiling code sampling until its exact location is decided upon. cpu/base.hh: Kernel stats are now in the BaseCPU instead of the ExecContext. cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: cpu/memtest/memtest.cc: cpu/memtest/memtest.hh: Changes to support rename of old ExecContext to CPUExecContext. See changeset for more details. cpu/exetrace.cc: Remove unneeded include of exec_context.hh. cpu/intr_control.hh: cpu/o3/alpha_cpu_builder.cc: Remove unneeded include of exec_context.hh cpu/o3/alpha_cpu.hh: cpu/o3/alpha_cpu_impl.hh: cpu/o3/cpu.cc: cpu/o3/cpu.hh: cpu/simple/cpu.cc: cpu/simple/cpu.hh: Changes to support rename of old ExecContext to CPUExecContext. See changeset for more details. Also avoid accessing anything directly from the XC. cpu/pc_event.cc: Avoid accessing objects directly from the XC. dev/tsunami_cchip.cc: Avoid accessing objects directly within the XC> kern/freebsd/freebsd_system.cc: kern/linux/linux_system.cc: kern/linux/linux_threadinfo.hh: kern/tru64/dump_mbuf.cc: kern/tru64/tru64.hh: kern/tru64/tru64_events.cc: sim/syscall_emul.cc: sim/syscall_emul.hh: Avoid accessing objects directly within the XC. kern/kernel_stats.cc: kern/kernel_stats.hh: Kernel stats no longer exist within the XC. kern/system_events.cc: Avoid accessing objects directly within the XC. Also kernel stats are now in the BaseCPU. sim/process.cc: sim/process.hh: Avoid accessing regs directly within an ExecContext. Instead use a CPUExecContext to initialize the registers and copy them over. cpu/cpu_exec_context.cc: Rename old ExecContext to CPUExecContext. This is used by the old CPU models to store any necessary architectural state. Also include the ProxyExecContext, which is used to access the CPUExecContext's state in code outside of the CPU. cpu/cpu_exec_context.hh: Rename old ExecContext to CPUExecContext. This is used by the old CPU models to store any necessary architectural state. Also include the ProxyExecContext, which is used to access the CPUExecContext's state in code outside of the CPU. Remove kernel stats from the ExecContext. sim/pseudo_inst.cc: Kernel stats now live within the CPU. Avoid accessing objects directly within the XC. --HG-- rename : cpu/exec_context.cc => cpu/cpu_exec_context.cc rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh extra : convert_revision : a75393a8945c80cca225b5e9d9c22a16609efb85
2006-03-04Merge ktlim@zizzer:/bk/m5Kevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/m5-shadowregs arch/alpha/ev5.cc: Remove intr_post, it is no longer used. arch/alpha/isa_traits.hh: Hand merge. --HG-- extra : convert_revision : 94f14539a9e5646f8c368b15b2dff18ab2f492cf
2006-03-04we REALLY don't want to use system headers for libelf...Ali Saidi
use "" not <> targetarch->arch arch/alpha/system.cc: targetarch -> arch base/loader/elf_object.cc: we REALLY don't want to use system headers for libelf... use "" not <> --HG-- extra : convert_revision : d0e1672dc655dca3081e36b2158e7b19ef54af40
2006-03-04Filled out the object file loader so it can load object files for several ↵Gabe Black
OSs and architectures. SConscript: Added ./libelf as an include search directory. There might be a better spot for this than where I put it. arch/SConscript: Combined the linux_process.h and tru64_process.h into process.h. This allows each ISA to support processes from arbitrary OSs. arch/alpha/SConscript: Added process.cc as a source file. It provides an implementation of createProcess, which takes an object_file object and creates the appropriate process object, or dies. base/loader/elf_object.cc: Actually extract the OS and architecture from the elf file, rather than always guessing Alpha and Linux. base/loader/object_file.hh: Added constants for SPARC, MIPS, and Solaris, and changed the include for the Addr type. sim/process.cc: Pushed creation of specific process objects into the ISA specific code. --HG-- extra : convert_revision : b4754e7ca8328672d07e1394c4d162e199606b53
2006-03-03Changes to support automatic renaming of the shadow registers at decode ↵Kevin Lim
time. This requires using an ExtMachInst (uint64_t) instead of the normal MachInst; the ExtMachInst is packed with extra decode context information. In the case of Alpha, the PAL mode is included. The shadow registers are folded into the normal integer registers to ease renaming indexing. Include the removed Opcdec class of instructions for faulting when a pal mode only instruction is decoded in non-pal mode. arch/alpha/ev5.cc: Changes to automatically map the shadow registers if the instruction is in PAL mode. arch/alpha/isa/branch.isa: arch/alpha/isa/decoder.isa: arch/alpha/isa/fp.isa: arch/alpha/isa/int.isa: arch/alpha/isa/mem.isa: arch/alpha/isa/pal.isa: arch/alpha/isa/unimp.isa: Changes for automatically using the shadow registers. Now instructions must decode based on an ExtMachInst, which is a MachInst with any decode context information concatenated onto the higher order bits. arch/alpha/isa/main.isa: Changes for automatically using the shadow registers. Now instructions must decode based on an ExtMachInst, which is a MachInst with any decode context information concatenated onto the higher order bits. The decoder (for Alpha) uses the 32nd bit in order to determine if the machine is in PAL mode. If it is, then it refers to the reg_redir table to determine the true index of the register it is using. Also include the opcdec instruction definition. arch/alpha/isa_traits.hh: Define ExtMachInst type that is used by the static inst in order to decode the instruction, given the context of being in pal mode or not. Redefine the number of Int registers, splitting it into NumIntArchRegs (32) and NumIntRegs (32 + 8 shadow registers). Change the dependence tags to reflect the integer registers include the 8 shadow registers. Define function to make an ExtMachInst. Currently it is somewhat specific to Alpha; in the future it must be decided to make this more generic and possibly slower, or leave it specific to each architecture and ifdef it within the CPU. arch/isa_parser.py: Have static insts decode on the ExtMachInst. base/remote_gdb.cc: Support the automatic remapping of shadow registers. Remote GDB must now look at the PC being read in order to tell if it should use the normal register indices or the shadow register indices. cpu/o3/regfile.hh: Comment out the pal registers; they are now a part of the integer registers. cpu/simple/cpu.cc: Create an ExtMachInst to decode on, based on the normal MachInst and the PC of the instructoin. cpu/static_inst.hh: Change from MachInst to ExtMachInst to support shadow register renaming. --HG-- extra : convert_revision : 1d23eabf735e297068e1917445a6348e9f8c88d5
2006-03-02Simple program runs with sendAtomic!Steve Reinhardt
Ignoring returned latency for now. Refactored loadSections in ObjectFile hierarchy. base/loader/aout_object.cc: base/loader/aout_object.hh: base/loader/ecoff_object.cc: base/loader/ecoff_object.hh: base/loader/elf_object.cc: base/loader/elf_object.hh: base/loader/object_file.hh: Have each section record a pointer to image data. This allows us to move common loadSections code into ObjectFile. base/loader/object_file.cc: Have each section record a pointer to image data. This allows us to move common loadSections code into ObjectFile. Also explicitly load BSS now since we need to allocate the translations for it in syscall emulation. cpu/base.hh: Don't need memPort (just pass port in to ExecContext constructor). cpu/exec_context.cc: cpu/exec_context.hh: mem/port.cc: mem/translating_port.cc: mem/translating_port.hh: Pass syscall emulation Port into constructor instead of getting it from BaseCPU. cpu/simple/cpu.cc: Explicitly choose one of three timing models. Statically allocate request and packet objects when possible. Several more minor bug fixes. Works for simple program with SIMPLE_CPU_MEM_IMMEDIATE model now. Probably have memory leaks with SIMPLE_CPU_MEM_TIMING (if it works at all). Pass syscall emulation Port into constructor instead of getting it from BaseCPU. cpu/simple/cpu.hh: Explicitly choose one of three timing models. Statically allocate request and packet objects when possible. Pass syscall emulation Port into constructor instead of getting it from BaseCPU. mem/physical.cc: Set packet result field. --HG-- extra : convert_revision : 359d0ebe4b4665867f4e26e7394ec0f1d17cfc26
2006-03-02More progress... run a few instructions now, but die on the secondSteve Reinhardt
memory access (I think because we're deallocating our one and only CpuRequest object). base/loader/aout_object.cc: base/loader/ecoff_object.cc: base/loader/elf_object.cc: Add flag to force allocation of new pages on data writes. cpu/simple/cpu.cc: Several minor fixes. Switch to atomic mode for now. mem/physical.hh: Don't copy the packet to the response event, just keep a reference to the original. mem/translating_port.cc: mem/translating_port.hh: Add parameter to writeBlobFunctional() to force allocation of unallocated pages on writes. --HG-- extra : convert_revision : 05cb31c7b0047b492dcfa0d12ddee690ef762b44
2006-03-01More progress toward actually running a program.Steve Reinhardt
See configs/test.py for test config (using simple binary in my home directory on zizzer). base/chunk_generator.hh: Fix assertion for chunkSize == 0 (not a power of 2) base/intmath.hh: Fix roundDown to take integer alignments. cpu/base.cc: Register exec contexts regardless of state (not sure why this check was in here in the first place). mem/physical.cc: Add breaks to switch. python/m5/objects/BaseCPU.py: Default mem to Parent.any (e.g. get from System). python/m5/objects/Ethernet.py: python/m5/objects/Root.py: HierParams is gone. python/m5/objects/PhysicalMemory.py: mmu param is full-system only. sim/process.cc: Stack mapping request must be page-aligned and page-sized. Don't delete objFile object in create since we are counting on it being around for startup(). --HG-- extra : convert_revision : 90c43ee927e7d82a045d6e10302d965797d006f7
2006-02-28Merge ktlim@zizzer:/bk/m5Kevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/m5-clean arch/alpha/ev5.cc: cpu/o3/regfile.hh: Hand merge. --HG-- rename : arch/alpha/alpha_memory.cc => arch/alpha/tlb.cc extra : convert_revision : c941dd2198851398820b38a66471372ed8454891
2006-02-27Changes to put all the misc regs within the misc reg file. This includes ↵Kevin Lim
the FPCR, Uniq, lock flag, lock addr, and IPRs. They are now accessed by calling readMiscReg()/setMiscReg() on the XC. Old IPR accesses are supported by using readMiscRegWithEffect() and setMiscRegWithEffect() (names may change in the future). arch/alpha/alpha_memory.cc: Change accesses to IPR to go through the XC. arch/alpha/ev5.cc: Change accesses for IPRs to go through the misc regs. arch/alpha/isa/decoder.isa: Change accesses to IPRs to go through the misc regs. readIpr() and setIpr() are now changed to calls to readMiscRegWithEffect() and setMiscRegWithEffect(). arch/alpha/isa/fp.isa: Change accesses to IPRs and Fpcr to go through the misc regs. arch/alpha/isa/main.isa: Add support for all misc regs being accessed through readMiscReg() and setMiscReg(). Instead of readUniq and readFpcr, they are replaced by calls with Uniq_DepTag and Fpcr_DepTag passed in as the register index. arch/alpha/isa_traits.hh: Change the MiscRegFile to a class that handles all accesses to MiscRegs, which in Alpha include the FPCR, Uniq, Lock Addr, Lock Flag, and IPRs. Two flavors of accesses are supported: normal register reads/writes, and reads/writes with effect. The latter are basically the original read/write IPR functions, while the former are normal reads/writes. The lock flag and lock addr registers are added to the dependence tags in order to support being accessed through the misc regs. arch/alpha/stacktrace.cc: cpu/simple/cpu.cc: dev/sinic.cc: Change accesses to the IPRs to go through the XC. arch/alpha/vtophys.cc: Change access to the IPR to go through the XC. arch/isa_parser.py: Change generation of code for control registers to use the readMiscReg and setMiscReg functions. base/remote_gdb.cc: Change accesses to the IPR to go through the XC. cpu/exec_context.hh: Use the miscRegs to access the lock addr, lock flag, and other misc registers. cpu/o3/alpha_cpu.hh: cpu/simple/cpu.hh: Support interface for reading and writing misc registers, which replaces readUniq, readFpcr, readIpr, and their set functions. cpu/o3/alpha_cpu_impl.hh: Change accesses to the IPRs to go through the miscRegs. For now comment out some of the accesses to the misc regs until the proxy exec context is completed. cpu/o3/alpha_dyn_inst.hh: Change accesses to misc regs to use readMiscReg and setMiscReg. cpu/o3/alpha_dyn_inst_impl.hh: Remove old misc reg accessors. cpu/o3/cpu.cc: Comment out old misc reg accesses until the proxy exec context is completed. cpu/o3/cpu.hh: Change accesses to the misc regs. cpu/o3/regfile.hh: Remove old access methods for the misc regs, replace them with readMiscReg and setMiscReg. They are dummy functions for now until the proxy exec context is completed. kern/kernel_stats.cc: kern/system_events.cc: Have accesses to the IPRs go through the XC. kern/tru64/tru64.hh: Have accesses to the misc regs use the new access methods. --HG-- extra : convert_revision : e32e0a3fe99522e17294bbe106ff5591cb1a9d76
2006-02-27Changed targetarch to just arch.Gabe Black
SConscript: Changed all of the "targetarch" files to be "arch" files arch/SConscript: Added all of the remaining targetarch files to isa_switch_hdrs --HG-- extra : convert_revision : a37d18349e27cf92dce12814f21944daa7fe9480
2006-02-24Changed Fault from a FaultBase * to a RefCountingPtr, added "new"s where ↵Gabe Black
appropriate, and took away the constant examples of each fault which where for comparing to a fault to determine its type. arch/alpha/alpha_memory.cc: arch/alpha/isa/decoder.isa: Added news where faults are created. arch/alpha/ev5.cc: Changed places where a fault was compared to a fault type to use isA rather than == arch/alpha/faults.cc: arch/alpha/faults.hh: Changed Fault to be a RefCountingPtr arch/alpha/isa/fp.isa: Added a new where a FloatEnableFault was created. arch/alpha/isa/unimp.isa: arch/alpha/isa/unknown.isa: Added a new where an UnimplementedFault is created. base/refcnt.hh: Added include of stddef.h for the NULL macro cpu/base_dyn_inst.cc: Added a new where an UnimplementedOpcodeFault is created. cpu/o3/alpha_cpu_impl.hh: Changed places where a fault was compared to a fault type to use isA rather than ==. Also changed fault->name to fault->name() cpu/o3/regfile.hh: Added new where UnimplementedOpcodeFaults are created. cpu/simple/cpu.cc: Changed places where a fault was compared to a fault type to use isA rather than ==. Also added a new where an Interrupt fault is created. dev/alpha_console.cc: Added news where MachineCheckFaults are created. dev/pcidev.hh: Added news where MachineCheckFaults are generated. dev/sinic.cc: Changed places where a fault was compared to a fault type to use isA rather than ==. Added news where MachineCheckFaults are created. Fixed a problem where m5.fast had unused variables. kern/kernel_stats.cc: Commented out where _faults is initialized. This statistic will probably be moved elsewhere in the future. kern/kernel_stats.hh: Commented out the declaration of _fault. when fault() is called, the fault increments its own stat. sim/faults.cc: sim/faults.hh: Changed Fault from a FaultBase * to a RefCountingPtr. --HG-- extra : convert_revision : b40ccfc42482d5a115e111dd897fa378d23c6c7d
2006-02-23Update functional memory to have a response eventRon Dreslinski
Clean out old memory python files, move them into old_mem directory. Maybe we should just delete them, they are under revision control. Add new py files for new objects. SConscript: Update because memory is just a header file now base/chunk_generator.hh: Make Chunk Generator return the entire size if the chunk_size is set to zero. Useful when trying to chunck on blocksize of memory, which can write large pieces of data. cpu/simple/cpu.cc: Make sure to delete the pkt. mem/physical.cc: mem/physical.hh: Set up response event. mem/port.cc: Rename rqst to req to conform to same standard naming convention. python/m5/objects/PhysicalMemory.py: Update the params, inheritence --HG-- extra : convert_revision : 857154ec256522baf423b715833930497999549b
2006-02-21Made Addr a global typeGabe Black
--HG-- extra : convert_revision : 869bd9fa5d8591115ac9b4a7401eb2490986b835
2006-02-20Make loaders use translation port instead of proxy memory.Ron Dreslinski
Also start compiling Simple CPU again. SConscript: Start Compiling Simple CPU as well base/loader/aout_object.cc: base/loader/aout_object.hh: base/loader/ecoff_object.cc: base/loader/ecoff_object.hh: base/loader/elf_object.cc: base/loader/elf_object.hh: base/loader/object_file.hh: sim/process.cc: sim/process.hh: Convert loaders to used translation port instead of proxy memory --HG-- extra : convert_revision : 63275071f6a0e0d71935641205b203d94381ee44
2006-02-19Changes to untemplate StaticInst and StaticInstPtr, change the isa to a ↵Gabe Black
namespace instead of a class, an improvement to the architecture specific header file selection system, and fixed up a few include paths. arch/alpha/alpha_linux_process.cc: Added using directive for AlphaISA namespace arch/alpha/alpha_memory.hh: arch/alpha/isa/branch.isa: cpu/pc_event.hh: Added typedefs for Addr arch/alpha/alpha_tru64_process.cc: arch/alpha/arguments.cc: Added using directive for AlphaISA arch/alpha/ev5.hh: Added an include of arch/alpha/isa_traits.hh, and a using directive for the AlphaISA namespace. arch/alpha/faults.hh: Added a typedef for the Addr type, and changed the formatting of the faults slightly. arch/alpha/isa/main.isa: Untemplatized StaticInst, added a using for namespace AlphaISA to show up in decoder.cc and the exec.ccs, relocated makeNop to decoder.hh arch/alpha/isa/mem.isa: Untemplatized StaticInst and StaticInstPtr arch/alpha/isa/pal.isa: cpu/base_dyn_inst.cc: Untemplatized StaticInstPtr arch/alpha/isa_traits.hh: Changed variables to be externs instead of static since they are part of a namespace and not a class. arch/alpha/stacktrace.cc: Untemplatized StaticInstPtr, and added a using directive for AlphaISA. arch/alpha/stacktrace.hh: Added some typedefs for Addr and MachInst, and untemplatized StaticInstPtr arch/alpha/vtophys.cc: Added a using directive for AlphaISA arch/alpha/vtophys.hh: Added the AlphaISA namespace specifier where needed arch/isa_parser.py: Changed the placement of the definition of the decodeInst function to be outside the namespaceInst namespace. base/loader/object_file.hh: cpu/o3/bpred_unit.hh: Added a typedef for Addr base/loader/symtab.hh: Added a typedef for Addr, and added a TheISA to Addr in another typedef base/remote_gdb.cc: Added a using namespace TheISA, and untemplatized StaticInstPtr base/remote_gdb.hh: Added typedefs for Addr and MachInst cpu/base.cc: Added TheISA specifier to some variables exported from the isa. cpu/base.hh: Added a typedef for Addr, and TheISA to some variables from the ISA cpu/base_dyn_inst.hh: Untemplatized StaticInstPtr, and added TheISA specifier to some variables from the ISA. cpu/exec_context.hh: Added some typedefs for types from the isa, and added TheISA specifier to some variables from the isa cpu/exetrace.hh: Added typedefs for some types from the ISA, and untemplatized StaticInstPtr cpu/memtest/memtest.cc: cpu/o3/btb.cc: dev/baddev.cc: dev/ide_ctrl.cc: dev/ide_disk.cc: dev/isa_fake.cc: dev/ns_gige.cc: dev/pciconfigall.cc: dev/platform.cc: dev/sinic.cc: dev/uart8250.cc: kern/freebsd/freebsd_system.cc: kern/linux/linux_system.cc: kern/system_events.cc: kern/tru64/dump_mbuf.cc: kern/tru64/tru64_events.cc: sim/process.cc: sim/pseudo_inst.cc: sim/system.cc: Added using namespace TheISA cpu/memtest/memtest.hh: cpu/trace/opt_cpu.hh: cpu/trace/reader/itx_reader.hh: dev/ide_disk.hh: dev/pcidev.hh: dev/platform.hh: dev/tsunami.hh: sim/system.hh: sim/vptr.hh: Added typedef for Addr cpu/o3/2bit_local_pred.hh: Changed the include to use arch/isa_traits.hh instead of arch/alpha/isa_traits.hh. Added typedef for Addr cpu/o3/alpha_cpu.hh: Added typedefs for Addr and IntReg cpu/o3/alpha_cpu_impl.hh: Added this-> to setNextPC to fix a problem since it didn't depend on template parameters any more. Removed "typename" where it was no longer needed. cpu/o3/alpha_dyn_inst.hh: Cleaned up some typedefs, and untemplatized StaticInst cpu/o3/alpha_dyn_inst_impl.hh: untemplatized StaticInstPtr cpu/o3/alpha_impl.hh: Fixed up a typedef of MachInst cpu/o3/bpred_unit_impl.hh: Added a using TheISA::MachInst to a function cpu/o3/btb.hh: Changed an include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr cpu/o3/commit.hh: Removed a typedef of Impl::ISA as ISA, since TheISA takes care of this now. cpu/o3/cpu.cc: Cleaned up namespace issues cpu/o3/cpu.hh: Cleaned up namespace usage cpu/o3/decode.hh: Removed typedef of ISA, and changed it to TheISA cpu/o3/fetch.hh: Fized up typedefs, and changed ISA to TheISA cpu/o3/free_list.hh: Changed include of arch/alpha/isa_traits.hh to arch/isa_traits.hh cpu/o3/iew.hh: Removed typedef of ISA cpu/o3/iew_impl.hh: Added TheISA namespace specifier to MachInst cpu/o3/ras.hh: Changed include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr. cpu/o3/regfile.hh: Changed ISA to TheISA, and added some typedefs for Addr, IntReg, FloatReg, and MiscRegFile cpu/o3/rename.hh: Changed ISA to TheISA, and added a typedef for RegIndex cpu/o3/rename_map.hh: Added an include for arch/isa_traits.hh, and a typedef for RegIndex cpu/o3/rob.hh: Added a typedef for RegIndex cpu/o3/store_set.hh: cpu/o3/tournament_pred.hh: Changed an include of arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef of Addr cpu/ozone/cpu.hh: Changed ISA into TheISA, and untemplatized StaticInst cpu/pc_event.cc: Added namespace specifier TheISA to Addr types cpu/profile.hh: kern/kernel_stats.hh: Added typedef for Addr, and untemplatized StaticInstPtr cpu/simple/cpu.cc: Changed using directive from LittleEndianGuest to AlphaISA, which will contain both namespaces. Added TheISA where needed, and untemplatized StaticInst cpu/simple/cpu.hh: Added a typedef for MachInst, and untemplatized StaticInst cpu/static_inst.cc: Untemplatized StaticInst cpu/static_inst.hh: Untemplatized StaticInst by using the TheISA namespace dev/alpha_console.cc: Added using namespace AlphaISA dev/simple_disk.hh: Added typedef for Addr and fixed up some formatting dev/sinicreg.hh: Added TheISA namespace specifier where needed dev/tsunami.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: Added using namespace TheISA. It might be better for it to be AlphaISA dev/tsunami_cchip.cc: Added typedef for TheISA. It might be better for it to be AlphaISA kern/linux/aligned.hh: sim/pseudo_inst.hh: Added TheISA namespace specifier to Addr kern/linux/linux_threadinfo.hh: Added typedef for Addr, and TheISA namespace specifier to StackPointerReg kern/tru64/mbuf.hh: Added TheISA to Addr type in structs sim/process.hh: Added typedefs of Addr, RegFile, and MachInst sim/syscall_emul.cc: Added using namespace TheISA, and a cast of VMPageSize to the int type sim/syscall_emul.hh: Added typecast for Addr, and TheISA namespace specifier for where needed --HG-- extra : convert_revision : 91d4f6ca33a73b21c1f1771d74bfdea3b80eff45
2006-02-15More progress toward compiling... partly bySteve Reinhardt
fixing things, partly by ignoring CPU models that don't currently compile. SConscript: Split sources for fast, simple, and o3 CPU models into separate source lists. For now none of these are included in the base source list, so you won't get any CPU models at all... but we still can't compile the other stuff so it's not an issue. Also get rid of obsolete encumbered/mem file. base/loader/aout_object.cc: base/loader/aout_object.hh: base/loader/ecoff_object.cc: base/loader/ecoff_object.hh: base/loader/elf_object.cc: base/loader/elf_object.hh: base/loader/object_file.hh: cpu/exec_context.cc: sim/process.cc: sim/system.cc: sim/system.hh: FunctionalMemory -> Memory cpu/pc_event.hh: Get rid of unused badpc. cpu/simple/cpu.cc: cpu/simple/cpu.hh: Move Port functions into .cc file. mem/port.hh: Make recvAddressRangesQuery panic by default instead of being abstract... do CPUs need to implement this? mem/request.hh: Add prefetch flags. sim/syscall_emul.hh: Start to fix... --HG-- extra : convert_revision : ece53b3855f20916caaa381598ac37e8c7adfba7
2006-02-12Removed isa_traits.hh from targetarch, moved vptr.hh from arch/alpha to sim, ↵Gabe Black
fixed an include to have the new location, and removed an ambiguating function declaration in byteswap.hh. SConscript: Moved isa_fullsys_traits.hh out of targetarch, since the only place it's included, and the only place the comments in the file say it should be included, is in the alpha isa_traits.hh targetarch/isa_traits.hh is now included through arch/isa_traits.hh vptr.hh was removed from targetarch, and moved to sim arch/alpha/pseudo_inst.cc: Moved vptr.hh from targetarch to sim base/loader/object_file.hh: base/loader/symtab.hh: cpu/base.hh: dev/ide_disk.cc: Changed the include of isa_traits.hh from targetarch to arch cpu/static_inst.hh: dev/platform.hh: dev/simple_disk.hh: kern/tru64/dump_mbuf.cc: kern/tru64/mbuf.hh: kern/tru64/tru64_events.cc: kern/tru64/tru64_system.cc: kern/tru64/tru64_system.hh: sim/process.hh: sim/syscall_emul.hh: Changed the include of isa_traits.hh from targetarch to arch. kern/linux/linux_threadinfo.hh: Changed the include of vptr.hh from targetarch to sim. sim/byteswap.hh: Removed the line declaring swap_byte(long), since it ambiguates with swap_byte(int32_t) sim/vptr.hh: Fixed the assert in the equals operator. Changed the AlphaISA namespace reference to TheISA. Changed arch/alpha/vtophys.hh to targetarch/vtophys.hh, since this file is now for all architectures. Added an include of arch/isa_traits.hh so that TheISA would be defined. --HG-- extra : convert_revision : e3c6ac17ed0277cfeba1d35cd63eba66eba5996f
2006-02-10fix problems on darwin/*BSD for syscall emulation modeAli Saidi
arch/alpha/alpha_linux_process.cc: arch/alpha/alpha_tru64_process.cc: fixup for bsd hosts. Some headers are included by default which means that more variables need TGT_ prefixes and there isn't a stat call (everything is a stat64 call) so we have to work around that a bit base/intmath.hh: base/socket.cc: this is no longer needed with mac os 10.4 cpu/inst_seq.hh: just use a uint64_t instead of long long cpu/o3/inst_queue_impl.hh: I much cleaner way to get max int sim/syscall_emul.hh: fix stat64 problems on *BSD --HG-- extra : convert_revision : 9eef5f896e083ae1774e818a9765dd83e0305942
2006-02-08Replace ad-hoc or locally defined power-of-2 testsSteve Reinhardt
with isPowerOf2() from intmath.hh. base/sched_list.hh: Use isPowerOf2() from intmath.hh. --HG-- extra : convert_revision : 7b2409531d8ed194aa7e1cfcd1ecb8460c797a16
2005-12-23Add ChunkGenerator object for breaking arbitrary regionsSteve Reinhardt
into block- or page-sized chunks. --HG-- extra : convert_revision : 3ebdd496f9ffc6d1fcd1847c33e98ac23f1bfe66
2005-12-23Fix roundUp function template so explicit arg is notSteve Reinhardt
needed in a few more cases. base/intmath.hh: align arg to roundUp should be int, not template class sim/process.cc: sim/syscall_emul.hh: No need for explicit template arg now that roundUp is fixed. --HG-- extra : convert_revision : f9f4639e022acb9f427e8d30d81c782504437c53
2005-12-23Change base/intmath.{cc,hh} to follow m5 style.Steve Reinhardt
arch/alpha/alpha_tru64_process.cc: base/intmath.hh: base/statistics.cc: base/str.cc: cpu/o3/btb.cc: sim/process.cc: sim/syscall_emul.hh: Rename intmath.hh functions to follow m5 style (RoundUp -> roundUp, etc.). base/intmath.cc: Rename intmath.hh functions to follow m5 style (RoundUp -> roundUp, etc.). Also reindent code in m5 style. --HG-- extra : convert_revision : 57b853002bc3c9911e122599d9062b41a06d8e6a
2005-11-28Make the debugger a bit more useful with m5.opt by moving stuffNathan Binkert
from #ifdef DEBUG to #ifndef NDEBUG base/remote_gdb.cc: make the remote debugger gdb stuff work in m5.opt sim/system.cc: sim/system.hh: make the console panic break event happen in m5.opt --HG-- extra : convert_revision : 044a9b7cdacb058112388a31315e45c5d8cf70fd
2005-11-20Serialize the symbol tablesNathan Binkert
base/loader/symtab.cc: Add support for clearing out the symbol table Add support for serializing the symbol table (clear on unserialize) Don't allow empty symbols to be entered into the table base/loader/symtab.hh: Add support for clearing out the symbol table Add support for serializing the symbol table sim/system.cc: Serialize the kernel, console, and palcode symbol tables so that we can capture any dynamic symbols that are added and so that we don't have to have the same kernel binary around to get the symbols right --HG-- extra : convert_revision : 779888c88aa530f3adcd37dc7600a335951d05f7
2005-11-20better placement of database commitsNathan Binkert
better mysql error messages base/stats/mysql.cc: better placement of commit() calls to avoid failing transactions due to what I think are timeouts. print out the mysql error with every panic --HG-- extra : convert_revision : bfc5ae172bcff733461adceffe2b381601839e82
2005-11-11Update random come to always have explict min/maxAli Saidi
--HG-- extra : convert_revision : a2d1f6f8aa1df24ea524792f687f4d3ee31101f0