gem5 - gem5

Age	Commit message (Expand)	Author
2015-04-08	config: Support full-system with SST's memory system	Curtis Dunham
2015-03-02	mem: Move crossbar default latencies to subclasses	Andreas Hansson
2014-12-23	config: Add --memchecker option	Marco Elver
2014-09-20	mem: Rename Bus to XBar to better reflect its behaviour	Andreas Hansson
2013-07-18	config: Update script to set cache line size on system	Andreas Hansson
2013-06-27	sim: Add the notion of clock domains to all ClockedObjects	Akash Bagdia
2013-06-27	config: Add a CPU clock command-line option	Akash Bagdia
2013-02-15	config: Remove O3 dependencies	Andreas Sandberg
2012-10-15	Regression: Use CPU clock and 32-byte width for L1-L2 bus	Andreas Hansson
2012-05-31	Bus: Split the bus into a non-coherent and coherent bus	Andreas Hansson
2012-03-01	x86: Fix switching of CPUs	Nilay Vaish
2012-02-14	Script: Fix the scripts that use the num_cpus cache parameter	Andreas Hansson
2012-02-13	MEM: Introduce the master/slave port roles in the Python classes	Andreas Hansson
2012-01-26	configs: A more realistic configuration of an ARM-like processor	Ronald Dreslinski
2011-02-23	configs: cache: add cache line size option	Korey Sewell
2011-02-23	configs: set default cache params	Korey Sewell
2011-02-03	Config: Keep track of uncached and cached ports separately.	Gabe Black
2011-02-01	X86: Add L1 caches for the TLB walkers.	Gabe Black
2010-02-25	configs: pull out cache configuration code from se.py and fs.py.	Lisa Hsu