gem5 - gem5

Age	Commit message (Collapse)	Author
2012-03-01	x86: Fix switching of CPUs	Nilay Vaish
	This patch prevents creation of interrupt controller for cpus that will be switched in later
2012-02-14	Script: Fix the scripts that use the num_cpus cache parameter	Andreas Hansson
	This patch merely removes the use of the num_cpus cache parameter which no longer exists after the introduction of the masterIds. The affected scripts fail when trying to set the parameter. Note that this patch does not update the regression stats.
2012-02-13	MEM: Introduce the master/slave port roles in the Python classes	Andreas Hansson
	This patch classifies all ports in Python as either Master or Slave and enforces a binding of master to slave. Conceptually, a master (such as a CPU or DMA port) issues requests, and receives responses, and conversely, a slave (such as a memory or a PIO device) receives requests and sends back responses. Currently there is no differentiation between coherent and non-coherent masters and slaves. The classification as master/slave also involves splitting the dual role port of the bus into a master and slave port and updating all the system assembly scripts to use the appropriate port. Similarly, the interrupt devices have to have their int_port split into a master and slave port. The intdev and its children have minimal changes to facilitate the extra port. Note that this patch does not enforce any port typing in the C++ world, it merely ensures that the Python objects have a notion of the port roles and are connected in an appropriate manner. This check is carried when two ports are connected, e.g. bus.master = memory.port. The following patches will make use of the classifications and specialise the C++ ports into masters and slaves.
2012-01-26	configs: A more realistic configuration of an ARM-like processor	Ronald Dreslinski

2011-02-23	configs: cache: add cache line size option	Korey Sewell

2011-02-23	configs: set default cache params	Korey Sewell
	It's confusing (especially to new users), when you are setting some standard parameters (as defined in Options.py) and they aren't reflected in the simulations so we might as well link the settings in CacheConfig.py to those in Options.py
2011-02-03	Config: Keep track of uncached and cached ports separately.	Gabe Black
	This makes sure that the address ranges requested for caches and uncached ports don't conflict with each other, and that accesses which are always uncached (message signaled interrupts for instance) don't waste time passing through caches.
2011-02-01	X86: Add L1 caches for the TLB walkers.	Gabe Black
	Small L1 caches are connected to the TLB walkers when caches are used. This allows them to participate in the coherence protocol properly.
2010-02-25	configs: pull out cache configuration code from se.py and fs.py.	Lisa Hsu
	Most of these frontend configurations share cache configuration code, pull it out so that changes to caches don't have to require changing multiple config files.