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path: root/configs/common/CacheConfig.py
AgeCommit message (Expand)Author
2014-09-20mem: Rename Bus to XBar to better reflect its behaviourAndreas Hansson
2013-07-18config: Update script to set cache line size on systemAndreas Hansson
2013-06-27sim: Add the notion of clock domains to all ClockedObjectsAkash Bagdia
2013-06-27config: Add a CPU clock command-line optionAkash Bagdia
2013-02-15config: Remove O3 dependenciesAndreas Sandberg
2012-10-15Regression: Use CPU clock and 32-byte width for L1-L2 busAndreas Hansson
2012-05-31Bus: Split the bus into a non-coherent and coherent busAndreas Hansson
2012-03-01x86: Fix switching of CPUsNilay Vaish
2012-02-14Script: Fix the scripts that use the num_cpus cache parameterAndreas Hansson
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
2012-01-26configs: A more realistic configuration of an ARM-like processorRonald Dreslinski
2011-02-23configs: cache: add cache line size optionKorey Sewell
2011-02-23configs: set default cache paramsKorey Sewell
2011-02-03Config: Keep track of uncached and cached ports separately.Gabe Black
2011-02-01X86: Add L1 caches for the TLB walkers.Gabe Black
2010-02-25configs: pull out cache configuration code from se.py and fs.py.Lisa Hsu