gem5 - gem5

Age	Commit message (Collapse)	Author
2011-12-01	O3: Remove hardcoded tgts_per_mshr in O3CPU.py.	Chander Sudanthi
	There are two lines in O3CPU.py that set the dcache and icache tgts_per_mshr to 20, ignoring any pre-configured value of tgts_per_mshr. This patch removes these hardcoded lines from O3CPU.py and sets the default L1 cache mshr targets to 20. --HG-- extra : rebase_source : 6f92d950e90496a3102967442814e97dc84db08b
2011-03-17	Mem: Fix issue with dirty block being lost when entire block transferred to ↵	Ali Saidi
	non-cache. This change fixes the problem for all the cases we actively use. If you want to try more creative I/O device attachments (E.g. sharing an L2), this won't work. You would need another level of caching between the I/O device and the cache (which you actually need anyway with our current code to make sure writes propagate). This is required so that you can mark the cache in between as top level and it won't try to send ownership of a block to the I/O device. Asserts have been added that should catch any issues.
2011-02-01	X86: Add L1 caches for the TLB walkers.	Gabe Black
	Small L1 caches are connected to the TLB walkers when caches are used. This allows them to participate in the coherence protocol properly.
2009-09-22	python: Move more code into m5.util allow SCons to use that code.	Nathan Binkert
	Get rid of misc.py and just stick misc things in __init__.py Move utility functions out of SCons files and into m5.util Move utility type stuff from m5/__init__.py to m5/util/__init__.py Remove buildEnv from m5 and allow access only from m5.defines Rename AddToPath to addToPath while we're moving it to m5.util Rename read_command to readCommand while we're moving it Rename compare_versions to compareVersions while we're moving it. --HG-- rename : src/python/m5/convert.py => src/python/m5/util/convert.py rename : src/python/m5/smartdict.py => src/python/m5/util/smartdict.py
2008-07-16	mem: use single BadAddr responder per system.	Steve Reinhardt
	Previously there was one per bus, which caused some coherence problems when more than one decided to respond. Now there is just one on the main memory bus. The default bus responder on all other buses is now the downstream cache's cpu_side port. Caches no longer need to do address range filtering; instead, we just have a simple flag to prevent snoops from propagating to the I/O bus.
2007-08-10	DMA: Add IOCache and fix bus bridge to optionally only send requests one	Ali Saidi
	way so a cache can handle partial block requests for i/o devices. --HG-- extra : convert_revision : a68b5ae826731bc87ed93eb7ef326a2393053964
2007-06-30	Get rid of remaining traces of obsolete CoherenceProtocol object.	Steve Reinhardt
	--HG-- extra : convert_revision : c5555b00bef1b304a84886188ad2c0dcb4d7c5b9
2007-05-10	remove hit_latency and make latency do the right thing	Ali Saidi
	set the latency parameter in terms of a latency add caches to tsunami-simple configs configs/common/Caches.py: tests/configs/memtest.py: tests/configs/o3-timing-mp.py: tests/configs/o3-timing.py: tests/configs/simple-atomic-mp.py: tests/configs/simple-timing-mp.py: tests/configs/simple-timing.py: set the latency parameter in terms of a latency configs/common/FSConfig.py: give the bridge a default latency too src/mem/cache/cache_builder.cc: src/python/m5/objects/BaseCache.py: remove hit_latency and make latency do the right thing tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-atomic.py: tests/configs/tsunami-simple-timing-dual.py: tests/configs/tsunami-simple-timing.py: add caches to tsunami-simple configs --HG-- extra : convert_revision : 37bef7c652e97c8cdb91f471fba62978f89019f1
2006-11-15	Add L2 cache option to fs.py --l2cache	Ron Dreslinski
	--HG-- extra : convert_revision : 5bdd1129c3b23e91d441e7b83f6a824ef7740fab
2006-10-27	factor out common run code from se.py and fs.py.	Lisa Hsu
	configs/example/fs.py: factor out common code. configs/example/se.py: factor out common code --HG-- extra : convert_revision : 72a1f653c84eae1b7d281e0a5e60ee116ad6b27d