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path: root/configs/common/Caches.py
AgeCommit message (Expand)Author
2015-07-03mem: Remove redundant is_top_level cache parameterAndreas Hansson
2015-07-03mem: Allow read-only caches and check complianceAndreas Hansson
2015-05-05arch, cpu: Do not forward snoops to table walkerAndreas Hansson
2013-07-18config: Update script to set cache line size on systemAndreas Hansson
2012-10-30config: Unify caches used in regressions and adjust L2 MSHRsAndreas Hansson
2012-10-26config: Fix the cache class naming in regression scriptsAndreas Hansson
2012-10-25config: Use shared cache config for regressionsAndreas Hansson
2012-10-15Mem: Use cycles to express cache-related latenciesAndreas Hansson
2012-09-25Cache: add a response latency to the cachesMrinmoy Ghosh
2011-12-01O3: Remove hardcoded tgts_per_mshr in O3CPU.py.Chander Sudanthi
2011-03-17Mem: Fix issue with dirty block being lost when entire block transferred to n...Ali Saidi
2011-02-01X86: Add L1 caches for the TLB walkers.Gabe Black
2009-09-22python: Move more code into m5.util allow SCons to use that code.Nathan Binkert
2008-07-16mem: use single BadAddr responder per system.Steve Reinhardt
2007-08-10DMA: Add IOCache and fix bus bridge to optionally only send requests oneAli Saidi
2007-06-30Get rid of remaining traces of obsolete CoherenceProtocol object.Steve Reinhardt
2007-05-10remove hit_latency and make latency do the right thingAli Saidi
2006-11-15Add L2 cache option to fs.py --l2cacheRon Dreslinski
2006-10-27factor out common run code from se.py and fs.py.Lisa Hsu