| Age | Commit message (Expand) | Author |
|---|---|---|
| 2012-10-15 | Mem: Use cycles to express cache-related latencies | Andreas Hansson |
| 2012-09-25 | Cache: add a response latency to the caches | Mrinmoy Ghosh |
| 2011-12-01 | O3: Remove hardcoded tgts_per_mshr in O3CPU.py. | Chander Sudanthi |
| 2011-03-17 | Mem: Fix issue with dirty block being lost when entire block transferred to n... | Ali Saidi |
| 2011-02-01 | X86: Add L1 caches for the TLB walkers. | Gabe Black |
| 2009-09-22 | python: Move more code into m5.util allow SCons to use that code. | Nathan Binkert |
| 2008-07-16 | mem: use single BadAddr responder per system. | Steve Reinhardt |
| 2007-08-10 | DMA: Add IOCache and fix bus bridge to optionally only send requests one | Ali Saidi |
| 2007-06-30 | Get rid of remaining traces of obsolete CoherenceProtocol object. | Steve Reinhardt |
| 2007-05-10 | remove hit_latency and make latency do the right thing | Ali Saidi |
| 2006-11-15 | Add L2 cache option to fs.py --l2cache | Ron Dreslinski |
| 2006-10-27 | factor out common run code from se.py and fs.py. | Lisa Hsu |
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