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path: root/configs/common/FSConfig.py
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2015-04-08config: Support full-system with SST's memory systemCurtis Dunham
This patch adds an example configuration in ext/sst/tests/ that allows an SST/gem5 instance to simulate a 4-core AArch64 system with SST's memHierarchy components providing all the caches and memories.
2015-03-19config: Specify OS type and release on command lineChris Emmons
This patch enables users to speficy --os-type on the command line. This option is used to take specific actions for an OS type, such as changing the kernel command line. This patch is part of the Android KitKat enablement.
2015-03-09config: Fix for 'android' lookup in disk nameRizwana Begum
This patch modifies FSConfig.py to look for 'android' only in disk image name. Before this patch, 'android' was searched in full disk path. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-03-02mem: Move crossbar default latencies to subclassesAndreas Hansson
This patch introduces a few subclasses to the CoherentXBar and NoncoherentXBar to distinguish the different uses in the system. We use the crossbar in a wide range of places: interfacing cores to the L2, as a system interconnect, connecting I/O and peripherals, etc. Needless to say, these crossbars have very different performance, and the clock frequency alone is not enough to distinguish these scenarios. Instead of trying to capture every possible case, this patch introduces dedicated subclasses for the three primary use-cases: L2XBar, SystemXBar and IOXbar. More can be added if needed, and the defaults can be overridden.
2015-01-16config: add --root-device machine parameterCurtis Dunham
In case /dev/sda1 is not actually the boot partition for an image, we can override it on the command line or in a benchmark definition.
2015-01-30config: arm: fix os_flagsMalek Musleh
Fix the makeArmSystem routine to reflect recent changes that support kernel commandline option when running android. Without this fix, trying to run android encounters a 'reference before assignment' error. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-12-04config: Add two options for setting the kernel command line.Gabe Black
Both options accept template which will, through python string formatting, have "mem", "disk", and "script" values substituted in from the mdesc. Additional values can be used on a case by case basis by passing them as keyword arguments to the fillInCmdLine function. That makes it possible to have specialized parameters for a particular ISA, for instance. The first option lets you specify the template directly, and the other lets you specify a file which has the template in it.
2014-12-03config: Get rid of some extra spaces around default arguments.Gabe Black
2014-10-29arm, tests: Update config files to more recent kernels and create 64-bit ↵Ali Saidi
regressions. This changes the default ARM system to a Versatile Express-like system that supports 2GB of memory and PCI devices and updates the default kernels/file-systems for AArch64 ARM systems (64-bit) to support up to 32GB of memory and PCI devices. Some platforms that are no longer supported have been pruned from the configuration files. In addition a set of 64-bit ARM regressions have been added to the regression system.
2014-10-29arm: fix bare-metal memory setup.Ali Saidi
The bare-metal configuration option still configured memory with the old scheme that no-longer works. This change unifies the code so there aren't any differences.
2014-07-17config, x86: Ensure that PCI devs get bridged to the memory busJiuyue Ma
This patch force IO device to be mapped to 0xC0000000-0xFFFF0000 by reserve anything between the end of memory and 3GB if memory is less than 3GB. It also statically bridge these address range to the IO bus, which guaranty access to pci address space will pass though bridge to iobus. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-07-17config, x86: swap bus_id of ISA/PCI in X86 IntelMPTableJiuyue Ma
This patch assign bus_id=0 to PCI bus and bus_id=1 to ISA bus for X86 platform. Because PCI device get config space address using Pc::calcPciConfigAddr() which requires "assert(bus==0)". This fixes PCI interrupt routing and discovery on Linux. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-09-20mem: Rename Bus to XBar to better reflect its behaviourAndreas Hansson
This patch changes the name of the Bus classes to XBar to better reflect the actual timing behaviour. The actual instances in the config scripts are not renamed, and remain as e.g. iobus or membus. As part of this renaming, the code has also been clean up slightly, making use of range-based for loops and tidying up some comments. The only changes outside the bus/crossbar code is due to the delay variables in the packet. --HG-- rename : src/mem/Bus.py => src/mem/XBar.py rename : src/mem/coherent_bus.cc => src/mem/coherent_xbar.cc rename : src/mem/coherent_bus.hh => src/mem/coherent_xbar.hh rename : src/mem/noncoherent_bus.cc => src/mem/noncoherent_xbar.cc rename : src/mem/noncoherent_bus.hh => src/mem/noncoherent_xbar.hh rename : src/mem/bus.cc => src/mem/xbar.cc rename : src/mem/bus.hh => src/mem/xbar.hh
2014-09-03arm: Support >2GB of memory for AArch64 systemsAli Saidi
2014-09-03arm: Assume we have a kernel that supports pci devicesAli Saidi
Change the default kernel for AArch64 and since it supports PCI devices remove the hack that made it use CF. Unfortunately, there isn't really a half-way here and we need to switch. Current users will get an error message that the kernel isn't found and hopefully go download a new kernel that supports PCI.
2014-09-03config: Refactor RealviewEMM to fit into new config systemGeoffrey Blake
This eliminates some default devices and adds in helper functions to connect the devices defined here to associate with the proper clock domains.
2014-05-15config: remove unecessary assignment of etherlink interfacesAnthony Gutierrez
in makeDualRoot() the etherlink interfaces are set using the tsunami interface however, they are set again a few lines later based on whether or not the system is a realview or tsunami system; the original assignment is always overwritten or there will be a fatal. this seems like an artifact from when tsunami was the only type of system capable of running with the dual option.
2014-04-14arm: set default kernels for VExpress_EMM and VExpress_EMM64Anthony Gutierrez
2014-03-20config: remove ruby_fs.pyNilay Vaish
The patch removes the ruby_fs.py file. The functionality is being moved to fs.py. This would being ruby fs simulations in line with how ruby se simulations are started (using --ruby option). The alpha fs config functions are being combined for classing and ruby memory systems. This required renaming the piobus in ruby to iobus. So, we will have stats being renamed in the stats file for ruby fs regression.
2014-02-18arm: armv8 boot options to enable v8Anthony Gutierrez
Modifies FSConfig.py to enable ARMv8 compatibility. To boot gem5 with ARMv8: Download the v8 kernel, .dtb file, and root FS from: http://gem5.org/Download Download the ARMv8 toolchain, and add the bin dir to your path: http://www.linaro.org/engineering/engineering-projects/armv8 Build gem5 for ARM Build the v8 bootloader (in gem5/system/arm/aarch64_bootloader) Make script in gem5/system/arm/aarch64_bootloader will require v8 toolchain, drop the produced boot_emm.arm64 in $(M5_PATH)/binaries/ Run: $ build/ARM/gem5.fast configs/example/fs.py --machine-type=VExpress_EMM64 \ --kernel=/path/to/kernel/vmlinux-linaro-tracking \ --dtb-filename=/path/to/dtb/rtsm_ve-aemv8a.dtb \ --disk-image=/path/to/img/linaro-minimal-armv8.img
2014-01-28x86: add a warning about the number of memory controllersNilay Vaish
When memory size > 3GB, print a warning that twice the number of memory controllers would be created.
2014-01-27config: allow more than 3GB of memory for x86 simulationsNilay Vaish
This patch edits the configuration files so that x86 simulations can have more than 3GB of memory. It also corrects a bug in the MemConfig.py script.
2014-01-24arm: Add support for ARMv8 (AArch64 & AArch32)ARM gem5 Developers
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black
2014-01-03config, x86: move kernel specification from tests to FSConfig.pySteve Reinhardt
For some reason, the default x86 kernel is specified in tests/configs/x86_generic.py and not in configs/common/FSConfig.py, where the kernels for all the other ISAs are. This means that running configs/example/fs.py for x86 fails because no kernel is specified. Moving the specification over fixes this problem. There is another problem that this uncovers, which is that going past the init stage (i.e., past where the regression test stops) fails because the fsck test on the disk device fails, but that's a separate issue.
2013-10-17arm, config: Fix a small issue with the dtb file being specifiedAli Saidi
2013-09-30x86: Add support for m5ops through a memory mapped interfaceAndreas Sandberg
In order to support m5ops in virtualized environments, we need to use a memory mapped interface. This changeset adds support for that by reserving 0xFFFF0000-0xFFFFFFFF and mapping those to the generic IPR interface for m5ops. The mapping is done in the X86ISA::TLB::finalizePhysical() which means that it just works for all of the CPU models, including virtualized ones.
2013-08-26ARM: Fix configuration files for bare-metal binaries.Ali Saidi
2013-08-19config: Move the memory instantiation outside FSConfigAndreas Hansson
This patch moves the instantiation of the memory controller outside FSConfig and instead relies on the mem_ranges to pass the information to the caller (e.g. fs.py or one of the regression scripts). The main motivation for this change is to expose the structural composition of the memory system and allow more tuning and configuration without adding a large number of options to the makeSystem functions. The patch updates the relevant example scripts to maintain the current functionality. As the order that ports are connected to the memory bus changes (in certain regresisons), some bus stats are shuffled around. For example, what used to be layer 0 is now layer 1. Going forward, options will be added to support the addition of multi-channel memory controllers.
2013-05-30mem: Avoid explicitly zeroing the memory backing storeAndreas Hansson
This patch removes the explicit memset as it is redundant and causes the simulator to touch the entire space, forcing the host system to allocate the pages. Anonymous pages are mapped on the first access, and the page-fault handler is responsible for zeroing them. Thus, the pages are still zeroed, but we avoid touching the entire allocated space which enables us to use much larger memory sizes as long as not all the memory is actually used.
2013-04-22config: Add a mem-type config option to se/fs scriptsAndreas Hansson
This patch enables selection of the memory controller class through a mem-type command-line option. Behind the scenes, this option is treated much like the cpu-type, and a similar framework is used to resolve the valid options, and translate the short-hand description to a valid class. The regression scripts are updated with a hardcoded memory class for the moment. The best solution going forward is probably to get the memory out of the makeSystem functions, but Ruby complicates things as it does not connect the memory controller to the membus. --HG-- rename : configs/common/CpuConfig.py => configs/common/MemConfig.py
2013-03-28x86: create space in bios memory mapNilay Vaish
As of now, we mark the top 1MB of memory space as unusable. Part of it is actually usable and is required to be marked so by some of the newer versions of linux kernel. This patch marks the top 639KB as usable. This value was chosen by looking at QEMU's output for bios memory map.
2013-02-15options: add command line option for dtb fileAnthony Gutierrez
2013-01-31mem: Add DDR3 and LPDDR2 DRAM controller configurationsAndreas Hansson
This patch moves the default DRAM parameters from the SimpleDRAM class to two different subclasses, one for DDR3 and one for LPDDR2. More can be added as we go forward. The regressions that previously used the SimpleDRAM are now using SimpleDDR3 as this is the most similar configuration.
2013-01-07config: Do not use hardcoded physmem in fs scriptAndreas Hansson
This patch generalises the address range resolution for the I/O cache and I/O bridge such that they do not assume a single memory. The patch involves adding a parameter to the system which is then defined based on the memories that are to be visible from the I/O subsystem, whether behind a cache or a bridge. The change is needed to allow interleaved memory controllers in the system.
2012-10-25config: Use SimpleDRAM in full-system, and with o3 and inorderAndreas Hansson
This patch favours using SimpleDRAM with the default timing instead of SimpleMemory for all regressions that involve the o3 or inorder CPU, or are full system (in other words, where the actual performance of the memory is important for the overall performance). Moving forward, the solution for FSConfig and the users of fs.py and se.py is probably something similar to what we use to choose the CPU type. I envision a few pre-set configurations SimpleLPDDR2, SimpleDDR3, etc that can be choosen by a dram_type option. Feedback on this part is welcome. This patch changes plenty stats and adds all the DRAM controller related stats. A follow-on patch updates the relevant statistics. The total run-time for the entire regression goes up with ~5% with this patch due to the added complexity of the SimpleDRAM model. This is a concious trade-off to ensure that the model is properly tested.
2012-09-19AddrRange: Simplify AddrRange params Python hierarchyAndreas Hansson
This patch simplifies the Range object hierarchy in preparation for an address range class that also allows striping (e.g. selecting a few bits as matching in addition to the range). To extend the AddrRange class to an AddrRegion, the first step is to simplify the hierarchy such that we can make it as lean as possible before adding the new functionality. The only class using Range and MetaRange is AddrRange, and the three classes are now collapsed into one.
2012-08-22Bridge: Remove NACKs in the bridge and unify with packet queueAndreas Hansson
This patch removes the NACKing in the bridge, as the split request/response busses now ensure that protocol deadlocks do not occur, i.e. the message-dependency chain is broken by always allowing responses to make progress without being stalled by requests. The NACKs had limited support in the system with most components ignoring their use (with a suitable call to panic), and as the NACKs are no longer needed to avoid protocol deadlocks, the cleanest way is to simply remove them. The bridge is the starting point as this is the only place where the NACKs are created. A follow-up patch will remove the code that deals with NACKs in the endpoints, e.g. the X86 table walker and DMA port. Ultimately the type of packet can be complete removed (until someone sees a need for modelling more complex protocols, which can now be done in parts of the system since the port and interface is split). As a consequence of the NACK removal, the bridge now has to send a retry to a master if the request or response queue was full on the first attempt. This change also makes the bridge ports very similar to QueuedPorts, and a later patch will change the bridge to use these. A first step in this direction is taken by aligning the name of the member functions, as done by this patch. A bit of tidying up has also been done as part of the simplifications. Surprisingly, this patch has no impact on any of the regressions. Hence, there was never any NACKs issued. In a follow-up patch I would suggest changing the size of the bridge buffers set in FSConfig.py to also test the situation where the bridge fills up.
2012-06-07Config: Remove setMipsOptionsNilay Vaish
As status matrix, MIPS fs does not work. Hence, these options are not required. Secondly, the function is setting param values for a CPU class. This seems strange, should probably be done in a different way.
2012-05-31Bus: Split the bus into a non-coherent and coherent busAndreas Hansson
This patch introduces a class hierarchy of buses, a non-coherent one, and a coherent one, splitting the existing bus functionality. By doing so it also enables further specialisation of the two types of buses. A non-coherent bus connects a number of non-snooping masters and slaves, and routes the request and response packets based on the address. The request packets issued by the master connected to a non-coherent bus could still snoop in caches attached to a coherent bus, as is the case with the I/O bus and memory bus in most system configurations. No snoops will, however, reach any master on the non-coherent bus itself. The non-coherent bus can be used as a template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses, and is typically used for the I/O buses. A coherent bus connects a number of (potentially) snooping masters and slaves, and routes the request and response packets based on the address, and also forwards all requests to the snoopers and deals with the snoop responses. The coherent bus can be used as a template for modelling QPI, HyperTransport, ACE and coherent OCP buses, and is typically used for the L1-to-L2 buses and as the main system interconnect. The configuration scripts are updated to use a NoncoherentBus for all peripheral and I/O buses. A bit of minor tidying up has also been done. --HG-- rename : src/mem/bus.cc => src/mem/coherent_bus.cc rename : src/mem/bus.hh => src/mem/coherent_bus.hh rename : src/mem/bus.cc => src/mem/noncoherent_bus.cc rename : src/mem/bus.hh => src/mem/noncoherent_bus.hh
2012-04-06MEM: Enable multiple distributed generalized memoriesAndreas Hansson
This patch removes the assumption on having on single instance of PhysicalMemory, and enables a distributed memory where the individual memories in the system are each responsible for a single contiguous address range. All memories inherit from an AbstractMemory that encompasses the basic behaviuor of a random access memory, and provides untimed access methods. What was previously called PhysicalMemory is now SimpleMemory, and a subclass of AbstractMemory. All future types of memory controllers should inherit from AbstractMemory. To enable e.g. the atomic CPU and RubyPort to access the now distributed memory, the system has a wrapper class, called PhysicalMemory that is aware of all the memories in the system and their associated address ranges. This class thus acts as an infinitely-fast bus and performs address decoding for these "shortcut" accesses. Each memory can specify that it should not be part of the global address map (used e.g. by the functional memories by some testers). Moreover, each memory can be configured to be reported to the OS configuration table, useful for populating ATAG structures, and any potential ACPI tables. Checkpointing support currently assumes that all memories have the same size and organisation when creating and resuming from the checkpoint. A future patch will enable a more flexible re-organisation. --HG-- rename : src/mem/PhysicalMemory.py => src/mem/AbstractMemory.py rename : src/mem/PhysicalMemory.py => src/mem/SimpleMemory.py rename : src/mem/physical.cc => src/mem/abstract_mem.cc rename : src/mem/physical.hh => src/mem/abstract_mem.hh rename : src/mem/physical.cc => src/mem/simple_mem.cc rename : src/mem/physical.hh => src/mem/simple_mem.hh
2012-04-05Config: corrects the way Ruby attaches to the DMA portsNilay Vaish
With recent changes to the memory system, a port cannot be assigned a peer port twice. While making use of the Ruby memory system in FS mode, DMA ports were assigned peer twice, once for the classic memory system and once for the Ruby memory system. This patch removes this double assignment of peer ports.
2012-03-27Config: Move setWorkCountOptions() to Simulation.pyNilay Vaish
The function is presently defined in FSConfig.py, which does not seem to be the correct place for it.
2012-03-16FSConfig.py: fix a typo makeLinuxAlphaRubySystemNilay Vaish
2012-03-09ARM: Fix memory starting at non-zero address and exceeding max mem for a system.Ali Saidi
2012-03-01ARM: Add support for Versatile Express extended memory mapAli Saidi
Also clean up how we create boot loader memory a bit.
2012-02-26Make the IO bridge accept address headed to all the local APICs.Gabe Black
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
This patch classifies all ports in Python as either Master or Slave and enforces a binding of master to slave. Conceptually, a master (such as a CPU or DMA port) issues requests, and receives responses, and conversely, a slave (such as a memory or a PIO device) receives requests and sends back responses. Currently there is no differentiation between coherent and non-coherent masters and slaves. The classification as master/slave also involves splitting the dual role port of the bus into a master and slave port and updating all the system assembly scripts to use the appropriate port. Similarly, the interrupt devices have to have their int_port split into a master and slave port. The intdev and its children have minimal changes to facilitate the extra port. Note that this patch does not enforce any port typing in the C++ world, it merely ensures that the Python objects have a notion of the port roles and are connected in an appropriate manner. This check is carried when two ports are connected, e.g. bus.master = memory.port. The following patches will make use of the classifications and specialise the C++ ports into masters and slaves.
2012-02-05X86: Rename the bridge which allows commnication back to the local APICs.Gabe Black
There was a collision with a name used in fs.py, and that causes that script not to work when used with x86.
2012-01-28SE/FS: Make SE vs. FS mode a runtime parameter.Gabe Black
2012-01-17MEM: Removing the default port peer from Python portsAndreas Hansson
In preparation for the introduction of Master and Slave ports, this patch removes the default port parameter in the Python port and thus forces the argument list of the Port to contain only the description. The drawback at this point is that the config port and dma port of PCI and DMA devices have to be connected explicitly. This is key for future diversification as the pio and config port are slaves, but the dma port is a master.