gem5 - gem5

Age	Commit message (Expand)	Author
2007-05-10	remove hit_latency and make latency do the right thing	Ali Saidi
2007-05-07	fix partial writes with a functional memory hack	Ali Saidi
2007-03-06	Move all of the parameters of the Root SimObject so they are	Nathan Binkert
2007-03-03	Add Iob and remove the fake device	Ali Saidi
2007-03-03	Implement Niagara I/O interface and rework interrupts	Ali Saidi
2007-02-21	Get rid of the ConsoleListener SimObject and just fold the	Nathan Binkert
2007-01-09	add memory mapped disk device	Ali Saidi
2006-12-06	Many more fixes for SPARC_FS. Gets us to the point where SOFTINT starts	Ali Saidi
2006-12-04	More changes to get SPARC fs closer. Now at 1.2M cycles before difference	Ali Saidi
2006-11-30	Load the hypervisor symbols twice, once with an address mask so that we can g...	Ali Saidi
2006-11-22	Added a parameter to set memory to zero. This is to support Legion, and once ...	Gabe Black
2006-11-20	Add in rom/rams for the nvram, hypervisor description, and partition descript...	Gabe Black
2006-11-16	Fixes for SPARC_FS	Gabe Black
2006-11-09	Get SPARC to the point that it starts running. Add ability to load the ROM bi...	Ali Saidi
2006-10-30	FSConfig.py:	Lisa Hsu
2006-10-30	se.py, fs.py:	Lisa Hsu
2006-10-17	Rename 'Machine' to 'SysConfig'.	Steve Reinhardt
2006-10-08	Clean up configs.	Kevin Lim
2006-09-05	Enable proxies (Self/Parent) for specifying ports.	Steve Reinhardt
2006-08-16	add etherdump file option	Ali Saidi
2006-08-16	Finish test clean-up & reorg.	Steve Reinhardt
2006-08-16	More restructuring of regression tests.	Steve Reinhardt
2006-08-15	implement benchmark selection code	Ali Saidi
2006-07-27	Clean up some more config stuff.	Kevin Lim
2006-07-22	Last minute check in. Very few functional changes other than some minor conf...	Kevin Lim
2006-07-21	Rearrange the FS configs to be more shared. Also check in the full-system te...	Kevin Lim