gem5 - gem5

Age	Commit message (Expand)	Author
2015-11-06	mem: Add an option to perform clean writebacks from caches	Andreas Hansson
2015-11-06	mem: Add cache clusivity	Andreas Hansson
2015-08-21	mem: Add explicit Cache subclass and make BaseCache abstract	Andreas Hansson
2015-07-03	mem: Remove redundant is_top_level cache parameter	Andreas Hansson
2015-07-03	mem: Allow read-only caches and check compliance	Andreas Hansson
2015-05-05	arch, cpu: Do not forward snoops to table walker	Andreas Hansson
2015-04-29	cpu: o3: replace issueLatency with bool pipelined	Nilay Vaish
2015-04-13	cpu: re-organizes the branch predictor structure.	Dibakar Gope
2015-03-27	arm, configs: Do not forward snoops from I cache	Andreas Hansson
2014-09-03	cpu: Change writeback modeling for outstanding instructions	Mitch Hayenga
2014-07-28	arm: make the PseudoLRU tags the default for the O3_ARM_v7aL2	Anthony Gutierrez
2014-06-30	arm: make the bi-mode predictor the default for O3_ARM_v7a_BP	Anthony Gutierrez
2014-01-24	arm: Add support for ARMv8 (AArch64 & AArch32)	ARM gem5 Developers
2013-11-15	cpu: allow the fetch buffer to be smaller than a cache line	Anthony Gutierrez
2013-07-18	config: Update script to set cache line size on system	Andreas Hansson
2013-05-14	cpu: remove local/globalHistoryBits params from branch pred	Anthony Gutierrez
2013-01-24	branch predictor: move out of o3 and inorder cpus	Nilay Vaish ext:(%2C%20Timothy%20Jones%20%3Ctimothy.jones%40cl.cam.ac.uk%3E)
2013-01-07	cpu: Rename defer_registration->switched_out	Andreas Sandberg
2012-12-06	TournamentBP: Fix some bugs with table sizes and counters	Erik Tomusk
2012-10-15	Mem: Use cycles to express cache-related latencies	Andreas Hansson
2012-09-25	Cache: add a response latency to the caches	Mrinmoy Ghosh
2012-02-12	prefetcher: Make prefetcher a sim object instead of it being a parameter on c...	Mrinmoy Ghosh
2012-01-26	configs: actually add ARMv7a-like cpu/cache file	Ronald Dreslinski