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path: root/configs/common/O3_ARM_v7a.py
AgeCommit message (Expand)Author
2015-11-06mem: Add an option to perform clean writebacks from cachesAndreas Hansson
2015-11-06mem: Add cache clusivityAndreas Hansson
2015-08-21mem: Add explicit Cache subclass and make BaseCache abstractAndreas Hansson
2015-07-03mem: Remove redundant is_top_level cache parameterAndreas Hansson
2015-07-03mem: Allow read-only caches and check complianceAndreas Hansson
2015-05-05arch, cpu: Do not forward snoops to table walkerAndreas Hansson
2015-04-29cpu: o3: replace issueLatency with bool pipelinedNilay Vaish
2015-04-13cpu: re-organizes the branch predictor structure.Dibakar Gope
2015-03-27arm, configs: Do not forward snoops from I cacheAndreas Hansson
2014-09-03cpu: Change writeback modeling for outstanding instructionsMitch Hayenga
2014-07-28arm: make the PseudoLRU tags the default for the O3_ARM_v7aL2Anthony Gutierrez
2014-06-30arm: make the bi-mode predictor the default for O3_ARM_v7a_BPAnthony Gutierrez
2014-01-24arm: Add support for ARMv8 (AArch64 & AArch32)ARM gem5 Developers
2013-11-15cpu: allow the fetch buffer to be smaller than a cache lineAnthony Gutierrez
2013-07-18config: Update script to set cache line size on systemAndreas Hansson
2013-05-14cpu: remove local/globalHistoryBits params from branch predAnthony Gutierrez
2013-01-24branch predictor: move out of o3 and inorder cpusNilay Vaish ext:(%2C%20Timothy%20Jones%20%3Ctimothy.jones%40cl.cam.ac.uk%3E)
2013-01-07cpu: Rename defer_registration->switched_outAndreas Sandberg
2012-12-06TournamentBP: Fix some bugs with table sizes and countersErik Tomusk
2012-10-15Mem: Use cycles to express cache-related latenciesAndreas Hansson
2012-09-25Cache: add a response latency to the cachesMrinmoy Ghosh
2012-02-12prefetcher: Make prefetcher a sim object instead of it being a parameter on c...Mrinmoy Ghosh
2012-01-26configs: actually add ARMv7a-like cpu/cache fileRonald Dreslinski