| Age | Commit message (Expand) | Author |
|---|---|---|
| 2014-01-24 | arm: Add support for ARMv8 (AArch64 & AArch32) | ARM gem5 Developers |
| 2013-11-15 | cpu: allow the fetch buffer to be smaller than a cache line | Anthony Gutierrez |
| 2013-07-18 | config: Update script to set cache line size on system | Andreas Hansson |
| 2013-05-14 | cpu: remove local/globalHistoryBits params from branch pred | Anthony Gutierrez |
| 2013-01-24 | branch predictor: move out of o3 and inorder cpus | Nilay Vaish ext:(%2C%20Timothy%20Jones%20%3Ctimothy.jones%40cl.cam.ac.uk%3E) |
| 2013-01-07 | cpu: Rename defer_registration->switched_out | Andreas Sandberg |
| 2012-12-06 | TournamentBP: Fix some bugs with table sizes and counters | Erik Tomusk |
| 2012-10-15 | Mem: Use cycles to express cache-related latencies | Andreas Hansson |
| 2012-09-25 | Cache: add a response latency to the caches | Mrinmoy Ghosh |
| 2012-02-12 | prefetcher: Make prefetcher a sim object instead of it being a parameter on c... | Mrinmoy Ghosh |
| 2012-01-26 | configs: actually add ARMv7a-like cpu/cache file | Ronald Dreslinski |
 |
index : gem5 | |
| gem5 |
| summaryrefslogtreecommitdiff |