Age | Commit message (Collapse) | Author |
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information about an error.
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doesn't exist
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CPU).
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them easily
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than the original class. Without this changes elsewhere in the config script (e.g. the DriveSys frequency can change the TestSys frequency.
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standard switch and change some ifs to work with the default port since every port is now connected to something.
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that isn't set use cwd.
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before the number of checkpoints requested are created.
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directly configured by python. Move stuff from root.(cc|hh) to
core.(cc|hh) since it really belogs there now.
In the process, simplify how ticks are used in the python code.
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extra : convert_revision : cf82ee1ea20f9343924f30bacc2a38d4edee8df3
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-m works as you think it should
Ctrl-C actually ends the simulation now
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into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix
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the TimingCPU. Now the Atomic CPU works with caches.
configs/common/Simulation.py:
Atomic CPU now works properly with caches, so we don't have to do extra parsing to hook up caches only to the timing CPU.
However the O3CPU must always use caches, so a check for that must still exist.
Also change the switch_cpus to be placed at the system level, now that Steve changed how the IntrController gets its CPU.
configs/example/fs.py:
configs/example/se.py:
Atomic CPU now handles caches.
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configs/common/Simulation.py:
simplify maxtick code a little bit - instead of checking for -1, just set it at MaxTick.
src/python/m5/__init__.py:
make a new m5 param called MaxTick.
src/sim/host.hh:
fix the M5 def. of MaxTick
src/sim/main.cc:
Simplify the MaxTick/num_cycles parsing within main.cc
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arbitrary CPU with or without caches.
configs/common/Simulation.py:
enable going from checkpoint into arbitrary CPU with or without caches.
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extra : convert_revision : 02e7ff8982fdb3a08bc609f89bd58df5b3a581b2
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this will have only the o3 cpu have a cache, rather than timing (warmup) + o3 have cache.
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doens't get confused.
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configs/common/Simulation.py:
Remove mem parameter.
configs/example/se.py:
Remove debug output that got included in my other push.
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import Caches
Simulation.py:
Fix typo - L2Cache --> L1Cache
configs/common/Simulation.py:
Fix typo - L2Cache --> L1Cache
configs/example/fs.py:
configs/example/se.py:
import Caches
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confused otherwise, oops.
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configs/common/Options.py:
make the warmup period in a standard switch part of the option.
configs/common/Simulation.py:
add some comments and also make the warmup period an option.
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extra : convert_revision : 0fa587291b97ff87c3b3a617e7359ac6d9bed7a5
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configs/example/fs.py:
factor out common code.
configs/example/se.py:
factor out common code
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