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path: root/configs/common/Simulation.py
AgeCommit message (Expand)Author
2017-12-15mem-ruby: Support atomic_noncaching acceses in rubySwapnil Haria
2017-12-12config: Fix need to set ISA of switch cpus.Austin Harris
2016-10-26config: Break out base options for usage with NULL ISAAndreas Hansson
2016-02-06style: remove trailing whitespaceSteve Reinhardt
2015-12-07config: Enable elastic trace capture and replay in se/fsRadhika Jagtap
2015-04-14config, cpu: fix progress interval for switched CPUsMalek Musleh
2015-03-23config: Add ability to exit simulation after initializationCurtis Dunham
2014-12-23config: Add options to take/resume from SimPoint checkpointsDam Sunwoo
2014-04-10config: add num-work-ids command line optionGedare Bloom
2013-09-11config: Initialize and check cpt_starttickJoel Hestness
2013-07-18Configs: Fix up maxtick and maxtimeJoel Hestness
2013-06-27sim: Add the notion of clock domains to all ClockedObjectsAkash Bagdia
2013-04-22config: Add a mem-type config option to se/fs scriptsAndreas Hansson
2013-04-09Configs: Fix handling of maxtick and take_checkpointsJoel Hestness
2013-03-22config: return exit event instead of causeNilay Vaish
2013-02-15config: Move CPU handover logic to m5.switchCpus()Andreas Sandberg
2013-02-15config: Cleanup CPU configurationAndreas Sandberg
2013-02-15cpu: Add CPU metadata om the Python classesAndreas Sandberg
2013-02-10config: Don't call sys.exit in interactive mode in run()Andreas Sandberg
2013-01-08config: Fix issue with changeset: a4739b6f799d.Ali Saidi
2013-01-08util: add m5_fail op.LluĂ­s Vilanova
2013-01-07cpu: Rename defer_registration->switched_outAndreas Sandberg
2012-11-02python: Rename doDrain()->drain() and make it do the right thingAndreas Sandberg
2012-11-02Partly revert [4f54b0f229b5] and move draining to m5.changeToTimingAndreas Sandberg
2012-09-12Standard Switch: Drain the system before switching CPUsJoel Hestness
2012-09-11Checkpoint: Pass maxtick to avoid undefined variableAndreas Hansson
2012-08-21Checkpoint: Fix broken checkpointing functionalityAndreas Hansson
2012-08-15configs: add option for repeatedly switching back-and-forth between cpu types.Anthony Gutierrez
2012-08-06Simulation.py: move code related to checkpointing to functionsNilay Vaish
2012-08-06Config: change how cpu class is setNilay Vaish
2012-07-23Config: Use clock option in se/fs script and pass to switch_cpusAndreas Hansson
2012-03-27Config: Move setWorkCountOptions() to Simulation.pyNilay Vaish
2012-03-09CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectableGeoffrey Blake
2012-01-28SE/FS: Get rid of FULL_SYSTEM in the configs directoryGabe Black
2012-01-26configs: A more realistic configuration of an ARM-like processorRonald Dreslinski
2012-01-23Config: Enable using O3 CPU and Ruby in SE modeNilay Vaish
2012-01-11Config: Add support for restoring using a timing CPUNilay Vaish
2012-01-05Config: Add an option of type 'choice' for cpu typeNilay Vaish
2011-05-23configs: missed spot progress-interval changeKorey Sewell
2011-05-20configs: cleanup redundant/unused optionsKorey Sewell
2011-04-04Sim: Fix Simulation.py to allow more than 1 core for standard switching.Anthony Gutierrez
2010-11-17Config: Change misleading "cycle" message to say "tick".Gabe Black
2010-08-17misc: add some AMD copyright noticesSteve Reinhardt
2010-08-17sim: fold checkpoint restore code into instantiate()Steve Reinhardt
2010-08-17configs: clean up checkpoint code in Simulation.pySteve Reinhardt
2010-08-17sim: make Python Root object a singletonSteve Reinhardt
2010-07-05util: add a script for testing checkpointingSteve Reinhardt
2009-11-18m5: Added option to take a checkpoint at the end of simulationBrad Beckmann
2009-09-22python: Move more code into m5.util allow SCons to use that code.Nathan Binkert
2009-09-16configs: add maxinsts option on command lineKorey Sewell