gem5 - gem5

Age	Commit message (Expand)	Author
2012-09-12	Standard Switch: Drain the system before switching CPUs	Joel Hestness
2012-09-11	Checkpoint: Pass maxtick to avoid undefined variable	Andreas Hansson
2012-08-21	Checkpoint: Fix broken checkpointing functionality	Andreas Hansson
2012-08-15	configs: add option for repeatedly switching back-and-forth between cpu types.	Anthony Gutierrez
2012-08-06	Simulation.py: move code related to checkpointing to functions	Nilay Vaish
2012-08-06	Config: change how cpu class is set	Nilay Vaish
2012-07-23	Config: Use clock option in se/fs script and pass to switch_cpus	Andreas Hansson
2012-03-27	Config: Move setWorkCountOptions() to Simulation.py	Nilay Vaish
2012-03-09	CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable	Geoffrey Blake
2012-01-28	SE/FS: Get rid of FULL_SYSTEM in the configs directory	Gabe Black
2012-01-26	configs: A more realistic configuration of an ARM-like processor	Ronald Dreslinski
2012-01-23	Config: Enable using O3 CPU and Ruby in SE mode	Nilay Vaish
2012-01-11	Config: Add support for restoring using a timing CPU	Nilay Vaish
2012-01-05	Config: Add an option of type 'choice' for cpu type	Nilay Vaish
2011-05-23	configs: missed spot progress-interval change	Korey Sewell
2011-05-20	configs: cleanup redundant/unused options	Korey Sewell
2011-04-04	Sim: Fix Simulation.py to allow more than 1 core for standard switching.	Anthony Gutierrez
2010-11-17	Config: Change misleading "cycle" message to say "tick".	Gabe Black
2010-08-17	misc: add some AMD copyright notices	Steve Reinhardt
2010-08-17	sim: fold checkpoint restore code into instantiate()	Steve Reinhardt
2010-08-17	configs: clean up checkpoint code in Simulation.py	Steve Reinhardt
2010-08-17	sim: make Python Root object a singleton	Steve Reinhardt
2010-07-05	util: add a script for testing checkpointing	Steve Reinhardt
2009-11-18	m5: Added option to take a checkpoint at the end of simulation	Brad Beckmann
2009-09-22	python: Move more code into m5.util allow SCons to use that code.	Nathan Binkert
2009-09-16	configs: add maxinsts option on command line	Korey Sewell
2009-05-05	cpus: fix cpu progress event	Korey Sewell
2009-04-21	Minor tweaks for future Ruby compatibility.	Steve Reinhardt
2009-02-10	Configs: Add support for the InOrder CPU model	Korey Sewell
2009-01-30	Errors: Print a URL with a hash of the format string to find more information...	Ali Saidi
2008-03-15	Simpoints: Fix regression bug/Don't set process.simpoint, if simpoint doesn't...	Ali Saidi
2008-02-29	Error out if -s is used without --caches (instead of saying you must specify a	Lisa Hsu
2008-02-29	Configs: Make sure options don't conflict	Ali Saidi
2008-02-28	Configs: Fix some bugs we introduced in the simpoints code	Ali Saidi
2008-02-27	Configs: Make using Simpoints easier with some config files that support them...	Rick Strong
2008-02-22	add instruction count fast forwaing and max instruction options	Vilas Sridharan
2008-02-14	Configs: Change Simulation.py to return a subclass of the CPU models rather t...	Ali Saidi
2007-12-18	Checkpointing: Fix a bug in the simulation script when restoring without stan...	Ali Saidi
2007-11-03	Checkpoint: Use checkpoint_dir, if that is not set use outdir (-d), and if th...	Ali Saidi
2007-10-25	Checkpoints: Change Simulation.py to not go crazy if the simulation ends befo...	Ali Saidi
2007-09-12	Checkpointing: Fix directory regex	Ali Saidi
2007-09-12	Checkpointing: Force drain/resume when switching a CPU	Ali Saidi
2007-03-06	Move all of the parameters of the Root SimObject so they are	Nathan Binkert
2007-01-30	fix some checkpointing annoyances	Ali Saidi
2006-11-26	Include check for making sure caches are enabled.	Kevin Lim
2006-11-09	Merge ktlim@zizzer:/bk/newmem	Kevin Lim
2006-11-09	Clean up config scripts to not have to worry about attaching a cache only to ...	Kevin Lim
2006-11-08	simplify maxtick parsing in both the python and the c++.	Lisa Hsu
2006-11-08	change to os.path.join like nate wanted.	Lisa Hsu
2006-11-01	factor some more commone code and enable going from checkpoint into arbitrary...	Lisa Hsu