gem5 - gem5

Age	Commit message (Collapse)	Author
2006-11-09	Merge ktlim@zizzer:/bk/newmem	Kevin Lim
	into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix --HG-- extra : convert_revision : dafe2d4a032b277c219ea13faf20567c20c1f2f4
2006-11-09	Clean up config scripts to not have to worry about attaching a cache only to ↵	Kevin Lim
	the TimingCPU. Now the Atomic CPU works with caches. configs/common/Simulation.py: Atomic CPU now works properly with caches, so we don't have to do extra parsing to hook up caches only to the timing CPU. However the O3CPU must always use caches, so a check for that must still exist. Also change the switch_cpus to be placed at the system level, now that Steve changed how the IntrController gets its CPU. configs/example/fs.py: configs/example/se.py: Atomic CPU now handles caches. --HG-- extra : convert_revision : 534ded558ef96cafd76b4b5c5317bd8f4d05076e
2006-11-08	simplify maxtick parsing in both the python and the c++.	Lisa Hsu
	configs/common/Simulation.py: simplify maxtick code a little bit - instead of checking for -1, just set it at MaxTick. src/python/m5/__init__.py: make a new m5 param called MaxTick. src/sim/host.hh: fix the M5 def. of MaxTick src/sim/main.cc: Simplify the MaxTick/num_cycles parsing within main.cc --HG-- extra : convert_revision : f800addfbc1323591c2e05b892276b439b671668
2006-11-08	change to os.path.join like nate wanted.	Lisa Hsu
	--HG-- extra : convert_revision : 6e8a0153adf04f0cc07904434e4cb6a83fe900eb
2006-11-01	factor some more commone code and enable going from checkpoint into ↵	Lisa Hsu
	arbitrary CPU with or without caches. configs/common/Simulation.py: enable going from checkpoint into arbitrary CPU with or without caches. --HG-- extra : convert_revision : 02e7ff8982fdb3a08bc609f89bd58df5b3a581b2
2006-11-01	make it so that you can do a standard switch without the caches option. ↵	Lisa Hsu
	this will have only the o3 cpu have a cache, rather than timing (warmup) + o3 have cache. --HG-- extra : convert_revision : d733de7ebb362bbd7376a0235ee7f117df2d6d37
2006-11-01	change name of 2nd switch_cpu so that ckpt recovery with multiple cpus ↵	Lisa Hsu
	doens't get confused. --HG-- extra : convert_revision : 16c710c4196c520d03c1993a26f38cf1f04ab637
2006-10-31	Fix up configs.	Kevin Lim
	configs/common/Simulation.py: Remove mem parameter. configs/example/se.py: Remove debug output that got included in my other push. --HG-- extra : convert_revision : 643c34147f6c6cbb98b8e6d6e8206b9859593ab0
2006-10-30	se.py, fs.py:	Lisa Hsu
	import Caches Simulation.py: Fix typo - L2Cache --> L1Cache configs/common/Simulation.py: Fix typo - L2Cache --> L1Cache configs/example/fs.py: configs/example/se.py: import Caches --HG-- extra : convert_revision : 4292225b322c069665262eab7c83b5341844fba0
2006-10-30	ensure that there is a "/" between the cptdir and the cpt.%d.	Lisa Hsu
	--HG-- extra : convert_revision : 9aed7c3aecad10b039f3cfb26e04a7950be6bed1
2006-10-30	decouple the switch option from the warmup period option - parsing was ↵	Lisa Hsu
	confused otherwise, oops. --HG-- extra : convert_revision : 951fc664c59363df5f5e026aa791d83c26f050ec
2006-10-30	add some comments and make the warmup period in a switchover parameterizable.	Lisa Hsu
	configs/common/Options.py: make the warmup period in a standard switch part of the option. configs/common/Simulation.py: add some comments and also make the warmup period an option. --HG-- extra : convert_revision : 0fa587291b97ff87c3b3a617e7359ac6d9bed7a5
2006-10-27	factor out common run code from se.py and fs.py.	Lisa Hsu
	configs/example/fs.py: factor out common code. configs/example/se.py: factor out common code --HG-- extra : convert_revision : 72a1f653c84eae1b7d281e0a5e60ee116ad6b27d