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2012-01-10Config: Remove short option string for cpu typeNilay Vaish
2012-01-09ARM: Add support for running multiple systemsAli Saidi
2012-01-09ARM: Add support for initparam m5 opAli Saidi
2012-01-09cpu2000: Add missing art benchmark to allAli Saidi
2012-01-05Config: Add an option of type 'choice' for cpu typeNilay Vaish
This patch adds a new option for cpu type. This option is of type 'choice' which is similar to a C++ enum, except that it takes string values as possible choices. Following options are being removed -- detailed, timing, inorder. --HG-- extra : rebase_source : 58885e2e8a88b6af8e6ff884a5922059dbb1a6cb
2011-12-15ARM: Update config files for Android/BBench images available on website.Anthony Gutierrez
--HG-- extra : rebase_source : ca98021c3f96422374fbd4500da312a5a9dd00df
2011-12-01O3: Remove hardcoded tgts_per_mshr in O3CPU.py.Chander Sudanthi
There are two lines in O3CPU.py that set the dcache and icache tgts_per_mshr to 20, ignoring any pre-configured value of tgts_per_mshr. This patch removes these hardcoded lines from O3CPU.py and sets the default L1 cache mshr targets to 20. --HG-- extra : rebase_source : 6f92d950e90496a3102967442814e97dc84db08b
2011-10-19ARM: Fix small bug in config script that prevents android from bootingAli Saidi
2011-08-19ARM: Add some MP regressions and clean up the disk images and kernels a bitAli Saidi
2011-08-19ARM: Add VExpress_E support with PCIe to gem5Ali Saidi
2011-08-19ARM: Add support for Versatile Express boardsAli Saidi
2011-05-23config: revamp x86 config to avoid appending to SimObjectVectorsSteve Reinhardt
A significant contributor to the need for adoptOrphanParams() is the practice of appending to SimObjectVectors which have already been assigned as children. This practice sidesteps the assignment operation for those appended SimObjects, which is where parent/child relationships are typically established. This patch reworks the config scripts that use append() on SimObjectVectors, which all happen to be in the x86 system configuration. At some point in the future, I hope to make SimObjectVectors immutable (by deriving from tuple rather than list), at which time this patch will be necessary for correct operation. For now, it just avoids some of the warning messages that get printed in adoptOrphanParams().
2011-05-23configs: missed spot progress-interval changeKorey Sewell
2011-05-20configs: cleanup redundant/unused optionsKorey Sewell
maxinsts & max_inst redundant prog_intvl and profile seem redundant, but profile looks to be unused add -p option for progress intervals
2011-05-04ARM: Configure bootloader parametersAli Saidi
2011-04-20python: fix another bug from changes to main.pyNathan Binkert
2011-04-04ARM: Include IDE/CF controller by default in PBX model.Ali Saidi
Frame buffer and boot linux: ./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxFrameBuf --kernel=vmlinux.touchkit Linux from a CF card: ./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxCflash --kernel=vmlinux.touchkit Run Android ./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmAndroid --kernel=vmlinux.android Run MP ./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxCflash --kernel=vmlinux.mp-2.6.38
2011-04-04Sim: Fix Simulation.py to allow more than 1 core for standard switching.Anthony Gutierrez
This patch moves the assignment of testsys.switch_cpus, testsys.switch_cpus_1, switch_cpu_list, and switch_cpu_list1 outside of the for loop so they are assigned only once, after switch_cpus and switch_cpus_1 are constructed.
2011-03-17ARM: Bare metal system should have 256MB of RAM.Ali Saidi
2011-03-17Mem: Fix issue with dirty block being lost when entire block transferred to ↵Ali Saidi
non-cache. This change fixes the problem for all the cases we actively use. If you want to try more creative I/O device attachments (E.g. sharing an L2), this won't work. You would need another level of caching between the I/O device and the cache (which you actually need anyway with our current code to make sure writes propagate). This is required so that you can mark the cache in between as top level and it won't try to send ownership of a block to the I/O device. Asserts have been added that should catch any issues.
2011-02-24Configs: Explicitly import env in Benchmarks.pyGabe Black
env was being implicitly imported into Benchmarks.py through SysPaths.py. This change brings it in explicitly in the file where it's used.
2011-02-23ARM: Clarifies creation of Linux and baremetal ARM systems.Ali Saidi
makeArmSystem creates both bare-metal and Linux systems more cleanly. machine_type was never optional though listed as an optional argument; a system such as "RealView_PBX" must now be explicitly specified. Now that it is a required argument, the placement of the arguments has changed slightly requiring some changes to calls that create ARM systems.
2011-02-23configs: cache: add cache line size optionKorey Sewell
2011-02-23configs: set default cache paramsKorey Sewell
It's confusing (especially to new users), when you are setting some standard parameters (as defined in Options.py) and they aren't reflected in the simulations so we might as well link the settings in CacheConfig.py to those in Options.py
2011-02-11VNC: Add VNC server to M5Ali Saidi
2011-02-08config: fixed minor bug connecting dma devices to rubyBrad Beckmann
2011-02-07X86, Config: Move the setting of work count options to a separate function.Gabe Black
This way things that don't care about work count options and/or aren't called by something that has those command line options set up doesn't have to build a fake object to carry in inert values.
2011-02-06m5: added work completed monitoring supportBrad Beckmann
2011-02-06ruby: x86 fs config supportBrad Beckmann
2011-02-03Config: Keep track of uncached and cached ports separately.Gabe Black
This makes sure that the address ranges requested for caches and uncached ports don't conflict with each other, and that accesses which are always uncached (message signaled interrupts for instance) don't waste time passing through caches.
2011-02-02X86: Change how the default disk image gets set up.Gabe Black
The disk image to use was always being forced to a particular value. This change changes what disk image is selected as the default based on the architecture being built. In the future, a more sophisticated system might be used that selected a path based on certain rules instead of relying on one off file names.
2011-02-01X86: Add L1 caches for the TLB walkers.Gabe Black
Small L1 caches are connected to the TLB walkers when caches are used. This allows them to participate in the coherence protocol properly.
2010-11-17Config: Change misleading "cycle" message to say "tick".Gabe Black
Most of the messages in the config scripts that report a time value already print "@ tick" followed by the current tick value, but a few were printing "@ cycle". Since this is a distinction that's frequently confusing to new users, this changes those message to the more accurate and consistent "@ tick".
2010-11-15ARM: Add support for a dumb IDE controllerAli Saidi
2010-11-08Mem: Finish half-baked support for mmaping file in physmem.Ali Saidi
Physmem has a parameter to be able to mem map a file, however it isn't actually used. This changeset utilizes the parameter so a file can be mmapped.
2010-08-24config: fixed ruby dma device connectionsBrad Beckmann
2010-08-23ARM: Add configuration for Linux/Full SystemAli Saidi
2010-08-20ruby: Reduced ruby latenciesBrad Beckmann
The previous slower ruby latencies created a mismatch between the faster M5 cpu models and the much slower ruby memory system. Specifically smp interrupts were much slower and infrequent, as well as cpus moving in and out of spin locks. The result was many cpus were idle for large periods of time. These changes fix the latency mismatch.
2010-08-20config: reorganized how ruby specifies command-line optionsBrad Beckmann
2010-08-17misc: add some AMD copyright noticesSteve Reinhardt
Meant to add these with the previous batch of csets.
2010-08-17sim: fold checkpoint restore code into instantiate()Steve Reinhardt
The separate restoreCheckpoint() call is gone; just pass the checkpoint dir as an optional arg to instantiate(). This change is a precursor to some more extensive reworking of the startup code.
2010-08-17configs: clean up checkpoint code in Simulation.pySteve Reinhardt
Small change to clean up some redundant code. Should not have any functional impact.
2010-08-17sim: make Python Root object a singletonSteve Reinhardt
Enforce that the Python Root SimObject is instantiated only once. The C++ Root object already panics if more than one is created. This change avoids the need to track what the root object is, since it's available from Root.getInstance() (if it exists). It's now redundant to have the user pass the root object to functions like instantiate(), checkpoint(), and restoreCheckpoint(), so that arg is gone. Users who use configs/common/Simulate.py should not notice.
2010-08-08None, not noneNathan Binkert
2010-07-05util: add a script for testing checkpointingSteve Reinhardt
See comments in util/checkpoint-tester.py for details.
2010-06-02ARM: fix sizes of structs for ARM LinuxAli Saidi
2010-04-18config: fix assertion for x86 in FSConfig.pyNathan Binkert
2010-03-21ruby: Reorganized Ruby topology and protocol filesBrad Beckmann
--HG-- rename : configs/ruby/MESI_CMP_directory.py => configs/ruby/protocols/MESI_CMP_directory.py rename : configs/ruby/MI_example.py => configs/ruby/protocols/MI_example.py rename : configs/ruby/MOESI_CMP_directory.py => configs/ruby/protocols/MOESI_CMP_directory.py rename : configs/ruby/MOESI_CMP_token.py => configs/ruby/protocols/MOESI_CMP_token.py rename : configs/ruby/MOESI_hammer.py => configs/ruby/protocols/MOESI_hammer.py rename : configs/ruby/networks/MeshDirCorners.py => src/mem/ruby/network/topologies/MeshDirCorners.py
2010-03-21ruby: Adds configurable bit selection for numa mappingBrad Beckmann
2010-03-21ruby: Ruby support for sparse memoryBrad Beckmann
The patch includes direct support for the MI example protocol.
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