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2012-06-11configs: add run scripts for ics/gb versions of android and bbenchAnthony Gutierrez
1) Modifies Benchmarks.py to add support for Android ICS and BBench on Android ICS. 2) An rcS script is added for BBench on ICS. 3) Separates benchmark entries and rcS scripts for GB/ICS 4) Removes the debugging output from the existing BBench run script. These print statements were used for debugging and they seemed to confuse users into believing they should see some terminal output.
2012-06-07Config: Remove setMipsOptionsNilay Vaish
As status matrix, MIPS fs does not work. Hence, these options are not required. Secondly, the function is setting param values for a CPU class. This seems strange, should probably be done in a different way.
2012-06-07Config: changes to a couple of error msgsNilay Vaish
2012-05-31Bus: Split the bus into a non-coherent and coherent busAndreas Hansson
This patch introduces a class hierarchy of buses, a non-coherent one, and a coherent one, splitting the existing bus functionality. By doing so it also enables further specialisation of the two types of buses. A non-coherent bus connects a number of non-snooping masters and slaves, and routes the request and response packets based on the address. The request packets issued by the master connected to a non-coherent bus could still snoop in caches attached to a coherent bus, as is the case with the I/O bus and memory bus in most system configurations. No snoops will, however, reach any master on the non-coherent bus itself. The non-coherent bus can be used as a template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses, and is typically used for the I/O buses. A coherent bus connects a number of (potentially) snooping masters and slaves, and routes the request and response packets based on the address, and also forwards all requests to the snoopers and deals with the snoop responses. The coherent bus can be used as a template for modelling QPI, HyperTransport, ACE and coherent OCP buses, and is typically used for the L1-to-L2 buses and as the main system interconnect. The configuration scripts are updated to use a NoncoherentBus for all peripheral and I/O buses. A bit of minor tidying up has also been done. --HG-- rename : src/mem/bus.cc => src/mem/coherent_bus.cc rename : src/mem/bus.hh => src/mem/coherent_bus.hh rename : src/mem/bus.cc => src/mem/noncoherent_bus.cc rename : src/mem/bus.hh => src/mem/noncoherent_bus.hh
2012-05-03Config: Fix help msg for option --mem-sizeJayneel Gandhi
2012-04-16Config: Add command line options for disk image and memory sizeJayneel Gandhi
Added the options to Options.py for FS mode with backward compatibility. It is good to provide an option to specify the disk image and the memory size from command line since a lot of disk images are created to support different benchmark suites as well as per user needs. Change in program also leads to change in memory requirements. These options provide the interface to provide both disk image and memory size from the command line and gives more flexibility.
2012-04-06MEM: Enable multiple distributed generalized memoriesAndreas Hansson
This patch removes the assumption on having on single instance of PhysicalMemory, and enables a distributed memory where the individual memories in the system are each responsible for a single contiguous address range. All memories inherit from an AbstractMemory that encompasses the basic behaviuor of a random access memory, and provides untimed access methods. What was previously called PhysicalMemory is now SimpleMemory, and a subclass of AbstractMemory. All future types of memory controllers should inherit from AbstractMemory. To enable e.g. the atomic CPU and RubyPort to access the now distributed memory, the system has a wrapper class, called PhysicalMemory that is aware of all the memories in the system and their associated address ranges. This class thus acts as an infinitely-fast bus and performs address decoding for these "shortcut" accesses. Each memory can specify that it should not be part of the global address map (used e.g. by the functional memories by some testers). Moreover, each memory can be configured to be reported to the OS configuration table, useful for populating ATAG structures, and any potential ACPI tables. Checkpointing support currently assumes that all memories have the same size and organisation when creating and resuming from the checkpoint. A future patch will enable a more flexible re-organisation. --HG-- rename : src/mem/PhysicalMemory.py => src/mem/AbstractMemory.py rename : src/mem/PhysicalMemory.py => src/mem/SimpleMemory.py rename : src/mem/physical.cc => src/mem/abstract_mem.cc rename : src/mem/physical.hh => src/mem/abstract_mem.hh rename : src/mem/physical.cc => src/mem/simple_mem.cc rename : src/mem/physical.hh => src/mem/simple_mem.hh
2012-04-05Config: corrects the way Ruby attaches to the DMA portsNilay Vaish
With recent changes to the memory system, a port cannot be assigned a peer port twice. While making use of the Ruby memory system in FS mode, DMA ports were assigned peer twice, once for the classic memory system and once for the Ruby memory system. This patch removes this double assignment of peer ports.
2012-03-28Config: Change the way options are addedNilay Vaish
I am not too happy with the way options are added in files se.py and fs.py currently. This patch moves all the options to the file Options.py, functions from which are called when required.
2012-03-27Config: Move setWorkCountOptions() to Simulation.pyNilay Vaish
The function is presently defined in FSConfig.py, which does not seem to be the correct place for it.
2012-03-16FSConfig.py: fix a typo makeLinuxAlphaRubySystemNilay Vaish
2012-03-09ARM: Fix memory starting at non-zero address and exceeding max mem for a system.Ali Saidi
2012-03-09CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectableGeoffrey Blake
Enables the CheckerCPU to be selected at runtime with the --checker option from the configs/example/fs.py and configs/example/se.py configuration files. Also merges with the SE/FS changes.
2012-03-01ARM: Add support for Versatile Express extended memory mapAli Saidi
Also clean up how we create boot loader memory a bit.
2012-03-01x86: Fix switching of CPUsNilay Vaish
This patch prevents creation of interrupt controller for cpus that will be switched in later
2012-03-01Config: make option ruby available alwaysNilay Vaish
2012-02-26Make the IO bridge accept address headed to all the local APICs.Gabe Black
2012-02-14Script: Fix the scripts that use the num_cpus cache parameterAndreas Hansson
This patch merely removes the use of the num_cpus cache parameter which no longer exists after the introduction of the masterIds. The affected scripts fail when trying to set the parameter. Note that this patch does not update the regression stats.
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
This patch classifies all ports in Python as either Master or Slave and enforces a binding of master to slave. Conceptually, a master (such as a CPU or DMA port) issues requests, and receives responses, and conversely, a slave (such as a memory or a PIO device) receives requests and sends back responses. Currently there is no differentiation between coherent and non-coherent masters and slaves. The classification as master/slave also involves splitting the dual role port of the bus into a master and slave port and updating all the system assembly scripts to use the appropriate port. Similarly, the interrupt devices have to have their int_port split into a master and slave port. The intdev and its children have minimal changes to facilitate the extra port. Note that this patch does not enforce any port typing in the C++ world, it merely ensures that the Python objects have a notion of the port roles and are connected in an appropriate manner. This check is carried when two ports are connected, e.g. bus.master = memory.port. The following patches will make use of the classifications and specialise the C++ ports into masters and slaves.
2012-02-12configs: fix minor config bugs posted on the mailing listAli Saidi
2012-02-12prefetcher: Make prefetcher a sim object instead of it being a parameter on ↵Mrinmoy Ghosh
cache
2012-02-05X86: Rename the bridge which allows commnication back to the local APICs.Gabe Black
There was a collision with a name used in fs.py, and that causes that script not to work when used with x86.
2012-01-28SE/FS: Get rid of FULL_SYSTEM in the configs directoryGabe Black
2012-01-28SE/FS: Make SE vs. FS mode a runtime parameter.Gabe Black
2012-01-26configs: actually add ARMv7a-like cpu/cache fileRonald Dreslinski
2012-01-26configs: A more realistic configuration of an ARM-like processorRonald Dreslinski
2012-01-23Config: Enable using O3 CPU and Ruby in SE modeNilay Vaish
2012-01-17MEM: Removing the default port peer from Python portsAndreas Hansson
In preparation for the introduction of Master and Slave ports, this patch removes the default port parameter in the Python port and thus forces the argument list of the Port to contain only the description. The drawback at this point is that the config port and dma port of PCI and DMA devices have to be connected explicitly. This is key for future diversification as the pio and config port are slaves, but the dma port is a master.
2012-01-17MEM: Make the bus bridge unidirectional and fixed address rangeAndreas Hansson
This patch makes the bus bridge uni-directional and specialises the bus ports to be a master port and a slave port. This greatly simplifies the assumptions on both sides as either port only has to deal with requests or responses. The following patches introduce the notion of master and slave ports, and would not be possible without this split of responsibilities. In making the bridge unidirectional, the address range mechanism of the bridge is also changed. For the cases where communication is taking place both ways, an additional bridge is needed. This causes issues with the existing mechanism, as the busses cannot determine when to stop iterating the address updates from the two bridges. To avoid this issue, and also greatly simplify the specification, the bridge now has a fixed set of address ranges, specified at creation time.
2012-01-17MEM: Add port proxies instead of non-structural portsAndreas Hansson
Port proxies are used to replace non-structural ports, and thus enable all ports in the system to correspond to a structural entity. This has the advantage of accessing memory through the normal memory subsystem and thus allowing any constellation of distributed memories, address maps, etc. Most accesses are done through the "system port" that is used for loading binaries, debugging etc. For the entities that belong to the CPU, e.g. threads and thread contexts, they wrap the CPU data port in a port proxy. The following replacements are made: FunctionalPort > PortProxy TranslatingPort > SETranslatingPortProxy VirtualPort > FSTranslatingPortProxy --HG-- rename : src/mem/vport.cc => src/mem/fs_translating_port_proxy.cc rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh
2012-01-11Config: Add support for restoring using a timing CPUNilay Vaish
Currently there is an assumption that restoration from a checkpoint will happen by first restoring to an atomic CPU and then switching to a timing CPU. This patch adds support for directly restoring to a timing CPU. It adds a new option '--restore-with-cpu' which is used to specify the type of CPU to which the checkpoint should be restored to. It defaults to 'atomic' which was the case before.
2012-01-10Config: Remove short option string for cpu typeNilay Vaish
2012-01-09ARM: Add support for running multiple systemsAli Saidi
2012-01-09ARM: Add support for initparam m5 opAli Saidi
2012-01-09cpu2000: Add missing art benchmark to allAli Saidi
2012-01-05Config: Add an option of type 'choice' for cpu typeNilay Vaish
This patch adds a new option for cpu type. This option is of type 'choice' which is similar to a C++ enum, except that it takes string values as possible choices. Following options are being removed -- detailed, timing, inorder. --HG-- extra : rebase_source : 58885e2e8a88b6af8e6ff884a5922059dbb1a6cb
2011-12-15ARM: Update config files for Android/BBench images available on website.Anthony Gutierrez
--HG-- extra : rebase_source : ca98021c3f96422374fbd4500da312a5a9dd00df
2011-12-01O3: Remove hardcoded tgts_per_mshr in O3CPU.py.Chander Sudanthi
There are two lines in O3CPU.py that set the dcache and icache tgts_per_mshr to 20, ignoring any pre-configured value of tgts_per_mshr. This patch removes these hardcoded lines from O3CPU.py and sets the default L1 cache mshr targets to 20. --HG-- extra : rebase_source : 6f92d950e90496a3102967442814e97dc84db08b
2011-10-19ARM: Fix small bug in config script that prevents android from bootingAli Saidi
2011-08-19ARM: Add some MP regressions and clean up the disk images and kernels a bitAli Saidi
2011-08-19ARM: Add VExpress_E support with PCIe to gem5Ali Saidi
2011-08-19ARM: Add support for Versatile Express boardsAli Saidi
2011-05-23config: revamp x86 config to avoid appending to SimObjectVectorsSteve Reinhardt
A significant contributor to the need for adoptOrphanParams() is the practice of appending to SimObjectVectors which have already been assigned as children. This practice sidesteps the assignment operation for those appended SimObjects, which is where parent/child relationships are typically established. This patch reworks the config scripts that use append() on SimObjectVectors, which all happen to be in the x86 system configuration. At some point in the future, I hope to make SimObjectVectors immutable (by deriving from tuple rather than list), at which time this patch will be necessary for correct operation. For now, it just avoids some of the warning messages that get printed in adoptOrphanParams().
2011-05-23configs: missed spot progress-interval changeKorey Sewell
2011-05-20configs: cleanup redundant/unused optionsKorey Sewell
maxinsts & max_inst redundant prog_intvl and profile seem redundant, but profile looks to be unused add -p option for progress intervals
2011-05-04ARM: Configure bootloader parametersAli Saidi
2011-04-20python: fix another bug from changes to main.pyNathan Binkert
2011-04-04ARM: Include IDE/CF controller by default in PBX model.Ali Saidi
Frame buffer and boot linux: ./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxFrameBuf --kernel=vmlinux.touchkit Linux from a CF card: ./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxCflash --kernel=vmlinux.touchkit Run Android ./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmAndroid --kernel=vmlinux.android Run MP ./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxCflash --kernel=vmlinux.mp-2.6.38
2011-04-04Sim: Fix Simulation.py to allow more than 1 core for standard switching.Anthony Gutierrez
This patch moves the assignment of testsys.switch_cpus, testsys.switch_cpus_1, switch_cpu_list, and switch_cpu_list1 outside of the for loop so they are assigned only once, after switch_cpus and switch_cpus_1 are constructed.
2011-03-17ARM: Bare metal system should have 256MB of RAM.Ali Saidi