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AgeCommit message (Expand)Author
2011-05-23config: revamp x86 config to avoid appending to SimObjectVectorsSteve Reinhardt
2011-05-23configs: missed spot progress-interval changeKorey Sewell
2011-05-20configs: cleanup redundant/unused optionsKorey Sewell
2011-05-04ARM: Configure bootloader parametersAli Saidi
2011-04-20python: fix another bug from changes to main.pyNathan Binkert
2011-04-04ARM: Include IDE/CF controller by default in PBX model.Ali Saidi
2011-04-04Sim: Fix Simulation.py to allow more than 1 core for standard switching.Anthony Gutierrez
2011-03-17ARM: Bare metal system should have 256MB of RAM.Ali Saidi
2011-03-17Mem: Fix issue with dirty block being lost when entire block transferred to n...Ali Saidi
2011-02-24Configs: Explicitly import env in Benchmarks.pyGabe Black
2011-02-23ARM: Clarifies creation of Linux and baremetal ARM systems.Ali Saidi
2011-02-23configs: cache: add cache line size optionKorey Sewell
2011-02-23configs: set default cache paramsKorey Sewell
2011-02-11VNC: Add VNC server to M5Ali Saidi
2011-02-08config: fixed minor bug connecting dma devices to rubyBrad Beckmann
2011-02-07X86, Config: Move the setting of work count options to a separate function.Gabe Black
2011-02-06m5: added work completed monitoring supportBrad Beckmann
2011-02-06ruby: x86 fs config supportBrad Beckmann
2011-02-03Config: Keep track of uncached and cached ports separately.Gabe Black
2011-02-02X86: Change how the default disk image gets set up.Gabe Black
2011-02-01X86: Add L1 caches for the TLB walkers.Gabe Black
2010-11-17Config: Change misleading "cycle" message to say "tick".Gabe Black
2010-11-15ARM: Add support for a dumb IDE controllerAli Saidi
2010-11-08Mem: Finish half-baked support for mmaping file in physmem.Ali Saidi
2010-08-24config: fixed ruby dma device connectionsBrad Beckmann
2010-08-23ARM: Add configuration for Linux/Full SystemAli Saidi
2010-08-20ruby: Reduced ruby latenciesBrad Beckmann
2010-08-20config: reorganized how ruby specifies command-line optionsBrad Beckmann
2010-08-17misc: add some AMD copyright noticesSteve Reinhardt
2010-08-17sim: fold checkpoint restore code into instantiate()Steve Reinhardt
2010-08-17configs: clean up checkpoint code in Simulation.pySteve Reinhardt
2010-08-17sim: make Python Root object a singletonSteve Reinhardt
2010-08-08None, not noneNathan Binkert
2010-07-05util: add a script for testing checkpointingSteve Reinhardt
2010-06-02ARM: fix sizes of structs for ARM LinuxAli Saidi
2010-04-18config: fix assertion for x86 in FSConfig.pyNathan Binkert
2010-03-21ruby: Reorganized Ruby topology and protocol filesBrad Beckmann
2010-03-21ruby: Adds configurable bit selection for numa mappingBrad Beckmann
2010-03-21ruby: Ruby support for sparse memoryBrad Beckmann
2010-03-21ruby: fixed how ruby_fs creates phsyical memoryBrad Beckmann
2010-02-25configs: pull out cache configuration code from se.py and fs.py.Lisa Hsu
2010-01-29ruby: Converted Garnet to M5 configurationBrad Beckmann
2010-01-29ruby: Added a mesh topologyBrad Beckmann
2010-01-29ruby: MOESI_CMP_token updates to use the new config systemBrad Beckmann
2010-01-29ruby: FS support using the new configuration systemBrad Beckmann
2010-01-29ruby: reorganized ruby python configurationBrad Beckmann
2009-12-19X86: Record the memory mode when building an X86 system.Gabe Black
2009-11-18m5: Added option to take a checkpoint at the end of simulationBrad Beckmann
2009-11-18m5: Moved profile option since Simulation depends on it.Brad Beckmann
2009-11-18ruby: Support for merging ALPHA_FS and rubyBrad Beckmann
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