gem5 - gem5

Age	Commit message (Expand)	Author
2012-05-31	Bus: Split the bus into a non-coherent and coherent bus	Andreas Hansson
2012-05-03	Config: Fix help msg for option --mem-size	Jayneel Gandhi
2012-04-16	Config: Add command line options for disk image and memory size	Jayneel Gandhi
2012-04-06	MEM: Enable multiple distributed generalized memories	Andreas Hansson
2012-04-05	Config: corrects the way Ruby attaches to the DMA ports	Nilay Vaish
2012-03-28	Config: Change the way options are added	Nilay Vaish
2012-03-27	Config: Move setWorkCountOptions() to Simulation.py	Nilay Vaish
2012-03-16	FSConfig.py: fix a typo makeLinuxAlphaRubySystem	Nilay Vaish
2012-03-09	ARM: Fix memory starting at non-zero address and exceeding max mem for a system.	Ali Saidi
2012-03-09	CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable	Geoffrey Blake
2012-03-01	ARM: Add support for Versatile Express extended memory map	Ali Saidi
2012-03-01	x86: Fix switching of CPUs	Nilay Vaish
2012-03-01	Config: make option ruby available always	Nilay Vaish
2012-02-26	Make the IO bridge accept address headed to all the local APICs.	Gabe Black
2012-02-14	Script: Fix the scripts that use the num_cpus cache parameter	Andreas Hansson
2012-02-13	MEM: Introduce the master/slave port roles in the Python classes	Andreas Hansson
2012-02-12	configs: fix minor config bugs posted on the mailing list	Ali Saidi
2012-02-12	prefetcher: Make prefetcher a sim object instead of it being a parameter on c...	Mrinmoy Ghosh
2012-02-05	X86: Rename the bridge which allows commnication back to the local APICs.	Gabe Black
2012-01-28	SE/FS: Get rid of FULL_SYSTEM in the configs directory	Gabe Black
2012-01-28	SE/FS: Make SE vs. FS mode a runtime parameter.	Gabe Black
2012-01-26	configs: actually add ARMv7a-like cpu/cache file	Ronald Dreslinski
2012-01-26	configs: A more realistic configuration of an ARM-like processor	Ronald Dreslinski
2012-01-23	Config: Enable using O3 CPU and Ruby in SE mode	Nilay Vaish
2012-01-17	MEM: Removing the default port peer from Python ports	Andreas Hansson
2012-01-17	MEM: Make the bus bridge unidirectional and fixed address range	Andreas Hansson
2012-01-17	MEM: Add port proxies instead of non-structural ports	Andreas Hansson
2012-01-11	Config: Add support for restoring using a timing CPU	Nilay Vaish
2012-01-10	Config: Remove short option string for cpu type	Nilay Vaish
2012-01-09	ARM: Add support for running multiple systems	Ali Saidi
2012-01-09	ARM: Add support for initparam m5 op	Ali Saidi
2012-01-09	cpu2000: Add missing art benchmark to all	Ali Saidi
2012-01-05	Config: Add an option of type 'choice' for cpu type	Nilay Vaish
2011-12-15	ARM: Update config files for Android/BBench images available on website.	Anthony Gutierrez
2011-12-01	O3: Remove hardcoded tgts_per_mshr in O3CPU.py.	Chander Sudanthi
2011-10-19	ARM: Fix small bug in config script that prevents android from booting	Ali Saidi
2011-08-19	ARM: Add some MP regressions and clean up the disk images and kernels a bit	Ali Saidi
2011-08-19	ARM: Add VExpress_E support with PCIe to gem5	Ali Saidi
2011-08-19	ARM: Add support for Versatile Express boards	Ali Saidi
2011-05-23	config: revamp x86 config to avoid appending to SimObjectVectors	Steve Reinhardt
2011-05-23	configs: missed spot progress-interval change	Korey Sewell
2011-05-20	configs: cleanup redundant/unused options	Korey Sewell
2011-05-04	ARM: Configure bootloader parameters	Ali Saidi
2011-04-20	python: fix another bug from changes to main.py	Nathan Binkert
2011-04-04	ARM: Include IDE/CF controller by default in PBX model.	Ali Saidi
2011-04-04	Sim: Fix Simulation.py to allow more than 1 core for standard switching.	Anthony Gutierrez
2011-03-17	ARM: Bare metal system should have 256MB of RAM.	Ali Saidi
2011-03-17	Mem: Fix issue with dirty block being lost when entire block transferred to n...	Ali Saidi
2011-02-24	Configs: Explicitly import env in Benchmarks.py	Gabe Black
2011-02-23	ARM: Clarifies creation of Linux and baremetal ARM systems.	Ali Saidi