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AgeCommit message (Expand)Author
2013-04-22cpu: generate SimPoint basic block vector profilesDam Sunwoo
2013-04-09Configs: Fix handling of maxtick and take_checkpointsJoel Hestness
2013-03-28x86: create space in bios memory mapNilay Vaish
2013-03-22config: return exit event instead of causeNilay Vaish
2013-02-20config: Fix --prog-interval command line optionAli Saidi
2013-02-15options: add command line option for dtb fileAnthony Gutierrez
2013-02-15config: Remove O3 dependenciesAndreas Sandberg
2013-02-15config: Move CPU handover logic to m5.switchCpus()Andreas Sandberg
2013-02-15config: Cleanup CPU configurationAndreas Sandberg
2013-02-15cpu: Add CPU metadata om the Python classesAndreas Sandberg
2013-02-10config: Don't call sys.exit in interactive mode in run()Andreas Sandberg
2013-01-31mem: Add DDR3 and LPDDR2 DRAM controller configurationsAndreas Hansson
2013-01-24branch predictor: move out of o3 and inorder cpusNilay Vaish ext:(%2C%20Timothy%20Jones%20%3Ctimothy.jones%40cl.cam.ac.uk%3E)
2013-01-08config: Fix issue with changeset: a4739b6f799d.Ali Saidi
2013-01-08util: add m5_fail op.LluĂ­s Vilanova
2013-01-07cpu: Rename defer_registration->switched_outAndreas Sandberg
2013-01-07config: Do not use hardcoded physmem in fs scriptAndreas Hansson
2012-12-06TournamentBP: Fix some bugs with table sizes and countersErik Tomusk
2012-11-19config: Fix description of checkpoint option from cycle to tickAndreas Hansson
2012-11-02python: Rename doDrain()->drain() and make it do the right thingAndreas Sandberg
2012-11-02Partly revert [4f54b0f229b5] and move draining to m5.changeToTimingAndreas Sandberg
2012-10-30config: Unify caches used in regressions and adjust L2 MSHRsAndreas Hansson
2012-10-26config: Fix the cache class naming in regression scriptsAndreas Hansson
2012-10-25config: Use SimpleDRAM in full-system, and with o3 and inorderAndreas Hansson
2012-10-25config: Use shared cache config for regressionsAndreas Hansson
2012-10-15Mem: Use cycles to express cache-related latenciesAndreas Hansson
2012-10-15Regression: Use CPU clock and 32-byte width for L1-L2 busAndreas Hansson
2012-09-25Cache: add a response latency to the cachesMrinmoy Ghosh
2012-09-19AddrRange: Simplify AddrRange params Python hierarchyAndreas Hansson
2012-09-12Standard Switch: Drain the system before switching CPUsJoel Hestness
2012-09-11Checkpoint: Pass maxtick to avoid undefined variableAndreas Hansson
2012-09-09se.py: support specifying multiple programs via command lineNilay Vaish
2012-08-22Bridge: Remove NACKs in the bridge and unify with packet queueAndreas Hansson
2012-08-21Checkpoint: Fix broken checkpointing functionalityAndreas Hansson
2012-08-15configs: add option for repeatedly switching back-and-forth between cpu types.Anthony Gutierrez
2012-08-06Simulation.py: move code related to checkpointing to functionsNilay Vaish
2012-08-06Config: change how cpu class is setNilay Vaish
2012-07-23Config: Use clock option in se/fs script and pass to switch_cpusAndreas Hansson
2012-06-11configs: add run scripts for ics/gb versions of android and bbenchAnthony Gutierrez
2012-06-07Config: Remove setMipsOptionsNilay Vaish
2012-06-07Config: changes to a couple of error msgsNilay Vaish
2012-05-31Bus: Split the bus into a non-coherent and coherent busAndreas Hansson
2012-05-03Config: Fix help msg for option --mem-sizeJayneel Gandhi
2012-04-16Config: Add command line options for disk image and memory sizeJayneel Gandhi
2012-04-06MEM: Enable multiple distributed generalized memoriesAndreas Hansson
2012-04-05Config: corrects the way Ruby attaches to the DMA portsNilay Vaish
2012-03-28Config: Change the way options are addedNilay Vaish
2012-03-27Config: Move setWorkCountOptions() to Simulation.pyNilay Vaish
2012-03-16FSConfig.py: fix a typo makeLinuxAlphaRubySystemNilay Vaish
2012-03-09ARM: Fix memory starting at non-zero address and exceeding max mem for a system.Ali Saidi