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2010-08-24config: fixed ruby dma device connectionsBrad Beckmann
2010-08-23ARM: Add configuration for Linux/Full SystemAli Saidi
2010-08-20ruby: Reduced ruby latenciesBrad Beckmann
The previous slower ruby latencies created a mismatch between the faster M5 cpu models and the much slower ruby memory system. Specifically smp interrupts were much slower and infrequent, as well as cpus moving in and out of spin locks. The result was many cpus were idle for large periods of time. These changes fix the latency mismatch.
2010-08-20config: reorganized how ruby specifies command-line optionsBrad Beckmann
2010-08-17misc: add some AMD copyright noticesSteve Reinhardt
Meant to add these with the previous batch of csets.
2010-08-17sim: fold checkpoint restore code into instantiate()Steve Reinhardt
The separate restoreCheckpoint() call is gone; just pass the checkpoint dir as an optional arg to instantiate(). This change is a precursor to some more extensive reworking of the startup code.
2010-08-17configs: clean up checkpoint code in Simulation.pySteve Reinhardt
Small change to clean up some redundant code. Should not have any functional impact.
2010-08-17sim: make Python Root object a singletonSteve Reinhardt
Enforce that the Python Root SimObject is instantiated only once. The C++ Root object already panics if more than one is created. This change avoids the need to track what the root object is, since it's available from Root.getInstance() (if it exists). It's now redundant to have the user pass the root object to functions like instantiate(), checkpoint(), and restoreCheckpoint(), so that arg is gone. Users who use configs/common/Simulate.py should not notice.
2010-08-08None, not noneNathan Binkert
2010-07-05util: add a script for testing checkpointingSteve Reinhardt
See comments in util/checkpoint-tester.py for details.
2010-06-02ARM: fix sizes of structs for ARM LinuxAli Saidi
2010-04-18config: fix assertion for x86 in FSConfig.pyNathan Binkert
2010-03-21ruby: Reorganized Ruby topology and protocol filesBrad Beckmann
--HG-- rename : configs/ruby/MESI_CMP_directory.py => configs/ruby/protocols/MESI_CMP_directory.py rename : configs/ruby/MI_example.py => configs/ruby/protocols/MI_example.py rename : configs/ruby/MOESI_CMP_directory.py => configs/ruby/protocols/MOESI_CMP_directory.py rename : configs/ruby/MOESI_CMP_token.py => configs/ruby/protocols/MOESI_CMP_token.py rename : configs/ruby/MOESI_hammer.py => configs/ruby/protocols/MOESI_hammer.py rename : configs/ruby/networks/MeshDirCorners.py => src/mem/ruby/network/topologies/MeshDirCorners.py
2010-03-21ruby: Adds configurable bit selection for numa mappingBrad Beckmann
2010-03-21ruby: Ruby support for sparse memoryBrad Beckmann
The patch includes direct support for the MI example protocol.
2010-03-21ruby: fixed how ruby_fs creates phsyical memoryBrad Beckmann
Now ruby_fs creates physical memory of the right size.
2010-02-25configs: pull out cache configuration code from se.py and fs.py.Lisa Hsu
Most of these frontend configurations share cache configuration code, pull it out so that changes to caches don't have to require changing multiple config files.
2010-01-29ruby: Converted Garnet to M5 configurationBrad Beckmann
2010-01-29ruby: Added a mesh topologyBrad Beckmann
2010-01-29ruby: MOESI_CMP_token updates to use the new config systemBrad Beckmann
2010-01-29ruby: FS support using the new configuration systemBrad Beckmann
2010-01-29ruby: reorganized ruby python configurationBrad Beckmann
Reorganized ruby python configuration so that protocol and ruby memory system configuration code can be shared by multiple front-end configuration files (i.e. memory tester, full system, and hopefully the regression tester). This code works for memory tester, but have not tested fs mode.
2009-12-19X86: Record the memory mode when building an X86 system.Gabe Black
2009-11-18m5: Added option to take a checkpoint at the end of simulationBrad Beckmann
2009-11-18m5: Moved profile option since Simulation depends on it.Brad Beckmann
2009-11-18ruby: Support for merging ALPHA_FS and rubyBrad Beckmann
Connects M5 cpu and dma ports directly to ruby sequencers and dma sequencers. Rubymem also includes a pio port so that pio requests and be forwarded to a special pio bus connecting to device pio ports.
2009-09-22python: Move more code into m5.util allow SCons to use that code.Nathan Binkert
Get rid of misc.py and just stick misc things in __init__.py Move utility functions out of SCons files and into m5.util Move utility type stuff from m5/__init__.py to m5/util/__init__.py Remove buildEnv from m5 and allow access only from m5.defines Rename AddToPath to addToPath while we're moving it to m5.util Rename read_command to readCommand while we're moving it Rename compare_versions to compareVersions while we're moving it. --HG-- rename : src/python/m5/convert.py => src/python/m5/util/convert.py rename : src/python/m5/smartdict.py => src/python/m5/util/smartdict.py
2009-09-16configs: add maxinsts option on command lineKorey Sewell
-option to allow threads to run to a max_inst_any_thread which is more useful/quicker in a lot of cases then always having to figure out what tick to run your simulation to.
2009-05-05cpus: fix cpu progress eventKorey Sewell
this was double scheduling itself (once in constructor and once in cpu code). also add support for stopping / starting progress events through repeatEvent flag and also changing the interval of the progress event as well
2009-04-26X86, Config: Make makeX86System consider the number of CPUs, and clean up ↵Gabe Black
interrupt assignment.
2008-07-16mem: use single BadAddr responder per system.Steve Reinhardt
Previously there was one per bus, which caused some coherence problems when more than one decided to respond. Now there is just one on the main memory bus. The default bus responder on all other buses is now the downstream cache's cpu_side port. Caches no longer need to do address range filtering; instead, we just have a simple flag to prevent snoops from propagating to the I/O bus.
2009-04-21Minor tweaks for future Ruby compatibility.Steve Reinhardt
2009-04-19X86: Actually put the PCI INTA entry into the MP tables.Gabe Black
2009-04-19X86: Make E820 report nice, round (and correct) numbers.Gabe Black
2009-04-19X86: Automatically make the IO APIC in an N CPU system have id N+1.Gabe Black
2009-04-15configs: Allow M5_CPU2000 env var to set CPU2K binary path.Steve Reinhardt
It would be nice to have a more comprehensive mechanism but this is a big improvement over manually editing the script.
2009-02-25X86: Add IRQ4 to the Intel MP tables.Gabe Black
2009-02-10Configs: Add support for the InOrder CPU modelKorey Sewell
2009-02-01X86: Find the natural lpj for this configuration.Gabe Black
2009-02-01X86: Add a root device to the kernel command line.Gabe Black
2009-02-01X86: Configure the first PCI interrupt.Gabe Black
2009-02-01X86: Hook in a hard drive image.Gabe Black
2009-02-01X86: Take out the IDE noprobe kernel arguments.Gabe Black
2009-02-01X86: Plug in an IDE controller.Gabe Black
2009-01-31X86: Add some interrupt info to the intel MP tables.Gabe Black
2009-01-30Errors: Print a URL with a hash of the format string to find more ↵Ali Saidi
information about an error.
2009-01-25X86: Prevent Linux for probing for non-existant IDE controllers.Gabe Black
2008-10-11X86: Add entries for the IO APIC to the MP table.Gabe Black
2008-10-11X86: Add an Intel MP table to the simulation.Gabe Black
2008-10-11X86: Rename the PC device to Pc.Gabe Black
--HG-- rename : src/dev/x86/PC.py => src/dev/x86/Pc.py
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