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AgeCommit message (Expand)Author
2012-10-30config: Unify caches used in regressions and adjust L2 MSHRsAndreas Hansson
2012-10-26config: Fix the cache class naming in regression scriptsAndreas Hansson
2012-10-25config: Use SimpleDRAM in full-system, and with o3 and inorderAndreas Hansson
2012-10-25config: Use shared cache config for regressionsAndreas Hansson
2012-10-15Mem: Use cycles to express cache-related latenciesAndreas Hansson
2012-10-15Regression: Use CPU clock and 32-byte width for L1-L2 busAndreas Hansson
2012-09-25Cache: add a response latency to the cachesMrinmoy Ghosh
2012-09-19AddrRange: Simplify AddrRange params Python hierarchyAndreas Hansson
2012-09-12Standard Switch: Drain the system before switching CPUsJoel Hestness
2012-09-11Checkpoint: Pass maxtick to avoid undefined variableAndreas Hansson
2012-09-09se.py: support specifying multiple programs via command lineNilay Vaish
2012-08-22Bridge: Remove NACKs in the bridge and unify with packet queueAndreas Hansson
2012-08-21Checkpoint: Fix broken checkpointing functionalityAndreas Hansson
2012-08-15configs: add option for repeatedly switching back-and-forth between cpu types.Anthony Gutierrez
2012-08-06Simulation.py: move code related to checkpointing to functionsNilay Vaish
2012-08-06Config: change how cpu class is setNilay Vaish
2012-07-23Config: Use clock option in se/fs script and pass to switch_cpusAndreas Hansson
2012-06-11configs: add run scripts for ics/gb versions of android and bbenchAnthony Gutierrez
2012-06-07Config: Remove setMipsOptionsNilay Vaish
2012-06-07Config: changes to a couple of error msgsNilay Vaish
2012-05-31Bus: Split the bus into a non-coherent and coherent busAndreas Hansson
2012-05-03Config: Fix help msg for option --mem-sizeJayneel Gandhi
2012-04-16Config: Add command line options for disk image and memory sizeJayneel Gandhi
2012-04-06MEM: Enable multiple distributed generalized memoriesAndreas Hansson
2012-04-05Config: corrects the way Ruby attaches to the DMA portsNilay Vaish
2012-03-28Config: Change the way options are addedNilay Vaish
2012-03-27Config: Move setWorkCountOptions() to Simulation.pyNilay Vaish
2012-03-16FSConfig.py: fix a typo makeLinuxAlphaRubySystemNilay Vaish
2012-03-09ARM: Fix memory starting at non-zero address and exceeding max mem for a system.Ali Saidi
2012-03-09CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectableGeoffrey Blake
2012-03-01ARM: Add support for Versatile Express extended memory mapAli Saidi
2012-03-01x86: Fix switching of CPUsNilay Vaish
2012-03-01Config: make option ruby available alwaysNilay Vaish
2012-02-26Make the IO bridge accept address headed to all the local APICs.Gabe Black
2012-02-14Script: Fix the scripts that use the num_cpus cache parameterAndreas Hansson
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
2012-02-12configs: fix minor config bugs posted on the mailing listAli Saidi
2012-02-12prefetcher: Make prefetcher a sim object instead of it being a parameter on c...Mrinmoy Ghosh
2012-02-05X86: Rename the bridge which allows commnication back to the local APICs.Gabe Black
2012-01-28SE/FS: Get rid of FULL_SYSTEM in the configs directoryGabe Black
2012-01-28SE/FS: Make SE vs. FS mode a runtime parameter.Gabe Black
2012-01-26configs: actually add ARMv7a-like cpu/cache fileRonald Dreslinski
2012-01-26configs: A more realistic configuration of an ARM-like processorRonald Dreslinski
2012-01-23Config: Enable using O3 CPU and Ruby in SE modeNilay Vaish
2012-01-17MEM: Removing the default port peer from Python portsAndreas Hansson
2012-01-17MEM: Make the bus bridge unidirectional and fixed address rangeAndreas Hansson
2012-01-17MEM: Add port proxies instead of non-structural portsAndreas Hansson
2012-01-11Config: Add support for restoring using a timing CPUNilay Vaish
2012-01-10Config: Remove short option string for cpu typeNilay Vaish
2012-01-09ARM: Add support for running multiple systemsAli Saidi