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AgeCommit message (Expand)Author
2007-11-03Checkpoint: Use checkpoint_dir, if that is not set use outdir (-d), and if th...Ali Saidi
2007-10-25Checkpoints: Change Simulation.py to not go crazy if the simulation ends befo...Ali Saidi
2007-10-07X86: Adjust the config scripts for x86 fs.Gabe Black
2007-09-12Checkpointing: Fix directory regexAli Saidi
2007-09-12Checkpointing: Force drain/resume when switching a CPUAli Saidi
2007-08-16PCI: Move PCI Configuration data into devices now that we can inherit paramet...Ali Saidi
2007-08-16Devices: Make EtherInts connect in the same way memory ports currently do.Ali Saidi
2007-08-12Regression: fix configuration for SPARC_FSAli Saidi
2007-08-08Added fastmem option.Vincentius Robby
2007-08-10DMA: Add IOCache and fix bus bridge to optionally only send requests oneAli Saidi
2007-06-30Get rid of remaining traces of obsolete CoherenceProtocol object.Steve Reinhardt
2007-06-10the cmd argument is supposed to be an array of parameters, not one stringNathan Binkert
2007-06-04fix SPARC....Ali Saidi
2007-05-27Move SimObject python files alongside the C++ and fixNathan Binkert
2007-05-15add an l2 cache option to se example configAli Saidi
2007-05-10remove hit_latency and make latency do the right thingAli Saidi
2007-05-07fix partial writes with a functional memory hackAli Saidi
2007-04-30add a udp stream benchmark and a udp loopback benchmarkAli Saidi
2007-03-22Fix mcf benchmark object so it gets the arguments it expects.Gabe Black
2007-03-06Move all of the parameters of the Root SimObject so they areNathan Binkert
2007-03-03Merge zizzer:/bk/newmemAli Saidi
2007-03-03Add Iob and remove the fake deviceAli Saidi
2007-03-03Implement Niagara I/O interface and rework interruptsAli Saidi
2007-03-03Keep around which input set was used for a benchmark, and make vortex work wi...Gabe Black
2007-02-21Get rid of the ConsoleListener SimObject and just fold theNathan Binkert
2007-01-30fix some checkpointing annoyancesAli Saidi
2007-01-09add memory mapped disk deviceAli Saidi
2006-12-06Many more fixes for SPARC_FS. Gets us to the point where SOFTINT startsAli Saidi
2006-12-04More changes to get SPARC fs closer. Now at 1.2M cycles before differenceAli Saidi
2006-11-30Load the hypervisor symbols twice, once with an address mask so that we can g...Ali Saidi
2006-11-29Merge zizzer:/bk/sparcfsGabe Black
2006-11-26Include check for making sure caches are enabled.Kevin Lim
2006-11-22Added a parameter to set memory to zero. This is to support Legion, and once ...Gabe Black
2006-11-22Merge zizzer:/bk/sparcfsGabe Black
2006-11-20Add in rom/rams for the nvram, hypervisor description, and partition descript...Gabe Black
2006-11-16Implement a single config file to encompass all of the SPECNathan Binkert
2006-11-16Merge zower.eecs.umich.edu:/home/gblack/m5/newmemmemopsGabe Black
2006-11-16Fixes for SPARC_FSGabe Black
2006-11-15Add L2 cache option to fs.py --l2cacheRon Dreslinski
2006-11-10Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-11-09Get SPARC to the point that it starts running. Add ability to load the ROM bi...Ali Saidi
2006-11-09Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-11-09Clean up config scripts to not have to worry about attaching a cache only to ...Kevin Lim
2006-11-08simplify maxtick parsing in both the python and the c++.Lisa Hsu
2006-11-08make rcS files read from the m5 source directory, not /dist.Lisa Hsu
2006-11-08change to os.path.join like nate wanted.Lisa Hsu
2006-11-01factor some more commone code and enable going from checkpoint into arbitrary...Lisa Hsu
2006-11-01make it so that you can do a standard switch without the caches option. this...Lisa Hsu
2006-11-01change name of 2nd switch_cpu so that ckpt recovery with multiple cpus doens'...Lisa Hsu
2006-10-31Fix up configs.Kevin Lim
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